TW200921821A - Manufacturing method of semiconductor apparatus and semiconductor apparatus - Google Patents

Manufacturing method of semiconductor apparatus and semiconductor apparatus Download PDF

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Publication number
TW200921821A
TW200921821A TW097143009A TW97143009A TW200921821A TW 200921821 A TW200921821 A TW 200921821A TW 097143009 A TW097143009 A TW 097143009A TW 97143009 A TW97143009 A TW 97143009A TW 200921821 A TW200921821 A TW 200921821A
Authority
TW
Taiwan
Prior art keywords
substrate
wiring
semiconductor wafer
semiconductor device
semiconductor
Prior art date
Application number
TW097143009A
Other languages
English (en)
Chinese (zh)
Inventor
Kiyoshi Oi
Masahiro Sunohara
Tomoharu Fujii
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200921821A publication Critical patent/TW200921821A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/4334—Auxiliary members in encapsulations
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
TW097143009A 2007-11-09 2008-11-07 Manufacturing method of semiconductor apparatus and semiconductor apparatus TW200921821A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007292142A JP2009117767A (ja) 2007-11-09 2007-11-09 半導体装置の製造方法及びそれにより製造した半導体装置

Publications (1)

Publication Number Publication Date
TW200921821A true TW200921821A (en) 2009-05-16

Family

ID=40622940

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097143009A TW200921821A (en) 2007-11-09 2008-11-07 Manufacturing method of semiconductor apparatus and semiconductor apparatus

Country Status (4)

Country Link
US (1) US20090121334A1 (enExample)
JP (1) JP2009117767A (enExample)
KR (1) KR20090048362A (enExample)
TW (1) TW200921821A (enExample)

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CN114582731A (zh) * 2022-05-05 2022-06-03 华进半导体封装先导技术研发中心有限公司 一种层叠封装的下封装体结构及其形成方法
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