TW200913222A - Multi layer low cost cavity substrate fabrication for PoP packages - Google Patents

Multi layer low cost cavity substrate fabrication for PoP packages Download PDF

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Publication number
TW200913222A
TW200913222A TW097118236A TW97118236A TW200913222A TW 200913222 A TW200913222 A TW 200913222A TW 097118236 A TW097118236 A TW 097118236A TW 97118236 A TW97118236 A TW 97118236A TW 200913222 A TW200913222 A TW 200913222A
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Taiwan
Prior art keywords
substrate
die
barrier element
package
cavity
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TW097118236A
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English (en)
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TWI366911B (en
Inventor
Prema Palaniappan
Masood Murtuza
Satyendra Singh Chauhan
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Texas Instruments Inc
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Publication of TW200913222A publication Critical patent/TW200913222A/zh
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Publication of TWI366911B publication Critical patent/TWI366911B/zh

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Description

200913222 九、發明說明： 【發明所屬之技術領域】 本發明整體而言係關於半導體裝置總成及封裝之領域， 且特定而言係關於製造具有三維封裝之積體電路（Ic)裝 置。 【先前技術】 眾所周知，下一代電子裝置之消費者將會增加對能裝於 一較小尺寸、耗電量小、及成本低於上一代的功能及特點 S 之需求。半導體裝置廠商則係以合併諸如封裝系統（Sip)、 多晶片封裝（MCPs)、封裝層疊封裝（PoP)、及類似其他可 提供縱向疊加一個或多個晶粒及或封裝並被整合以操作為 一半導體裝置之經改良的三維封裝技術之方式來因應。舉 例而言’ PoP封裝係通常被用於在能減少尺寸之情況下 亦希望能有效地存取於記憶體之產品中，諸如蜂巢式電 話。
Pop通常包含至少一諸如位在底封裝内的邏輯晶片之晶 ^ 粒。基板之頂表面係用作為一受體以安裝一諸如一記憶體 曰曰片之頂封裝。該頂封裝係藉由球柵陣列（BGA)或其他類 似方式電性地耦合於底基板。如果在底封裝上具有多於一 個晶粒，則可採用一空腔基板，因為其允許一不干擾於頂 封裝之較小模蓋。該空腔基板係可製造為一單塊基板或為 共同附接以形成一中心空腔之多個基板。以一單塊基板形 成的中〜空腔通常比較昂貴且複雜，但利用多個基板形成 的中。二腔較具有成本效益。然而，在PoP封裝之總成期 131561.doc 200913222 一^利用权塑化合物對晶粒的封裝常常導致模塑化合物以 不可預知與不均勻的方式在多層基板之間流動’從而潛 在地包含不均勻壓力。 【發明内容】 本案申請人認為現需具有製造一具有封裝層疊封裝 (P〇一p)型封裝技術的半導體裝置之方法及系統；並需要含 有由利用多層基板所建立之中心空腔範圍内的模塑化合 物二不存在上述先前技術所發現的缺點。 一述目的需要藉由本發明教示的技術來解決，其係關於 用於半導體裝置之總成及封裝之系統及方法。根據—實 施例’在-用於製造具有一封裝層疊封裝結構之半導體裝 置之方法及系統中，—底積層基板（BLS)係形成以包含_ 底中心部分及一周圍部分，纟由一阻障元件分離。該阻障 -件形成-周圍壁以包圍該底中心部分一框形頂積層基 ，(TLS)係配置於BLS之周圍部分之上。該似具有一開頂 部分，其相配於由周圍壁所包圍的底中心部分以形 成-空腔。複數個導電凸塊之每一者係配置於Μ之頂觸 之周圍部分的底觸片之間，以在其之間提供電性 “合。阻障元件在空腔與複數個導電凸塊之間形成 一密封。 "士;/之$樣中’—種用於製造一具有封裝層疊封 :一構的半導體裝置之方法係包含：在一底積層基板上形 障几件，從而使底積層基板分離成—底中心部分及 周圍。P分。阻障元件之形成係包含形成—周圍壁，以包 131561.doc 200913222 圍能安裝至少一晶粒的底中心部分。一框形頂積層基板係 藉由結合頂積層基板之頂觸片及底積層基板之周圍部分之 底觸片至配置於該等之間的複數個導電凸塊之其中一導電 凸塊進行附接於底積層基板。頂積層基板包含一開頂式中 心部分’其相配於底中心部分以形成一具有一開頂式空 腔。至少有一個晶粒係被安裝至底中心部分上。該空腔係 以-模塑化合物填滿以封裝至少—晶粒。—頂封袈係被安 裝於頂積層基板之上以提供封裝層疊封裝結構。 f 若干個優點係由根據存在於文中的說明性實施例之方法 及系統it到。肖等實施例有利於藉由提供一㈣成一密封 以充分防止模塑化合物流出於空腔外之阻障元件進行提供 一經改良的PoP結構。具有經改良p〇p結構的該半導體裝置 藉由利用現有的積層基板材料及方法，及利用現有的^連 材料及方法，諸如在關於黏貼上的焊料，係可有利地製 造。利用現有的材料及方法有利於使多層基板承包人執行 l 與單片基板設計或沒有阻障元件的情況下黏附兩 個積層基板相比，藉由利用兩個積層基板與—阻 =係更具有成本效率。該空腔係有利地能夠覆蓋-個 :=晶粒’該等晶粒係經由諸如引線接合及覆晶或料 、，·。合的可選擇的互連技術進行連接至底積層 、 【實施方式】 ::製造-具有Μ結構的半導雜裝置 使"於安裝晶…腔基板。用於自： 氣造空腔之傳統技術通常成本高且複雜。藉由利^ 131561.doc 200913222 塊基板製造一空腔基板係可能在成本上有效性但其常常具 有局限性。舉例說明’藉由一模塑化合物對晶粒的封裝係 常常導致模塑化合物以未預知及不均勻方式在頂基板下流 動，從而潛在 一
經改良的用於製造一具有一 PoP結構之半導體裝置之系統 及方法解決。根據一實施例，在用於製造一具有封裝層疊 封裝結構之半導體裝置之方法及系統内，一底積層"基板 (BLS)係形成以包含一底中心部分及一周圍部分，其由一 阻障元件分離。該阻障元件形成一周圍壁以包圍該底中心 部分。一框形頂積層基板（TLS)係配置於BLS之周圍部分之 上。該TLS具有一開頂式中心部分，其相配於由周圍壁所 包圍的底中心部分以形成一空腔。複數個導電凸塊之每一 者係配置於TLS之頂觸片與BLS之周圍部分的底觸片之 間，以在其之間提供電性及機械耦合。阻障元件在空腔盘 複數個導電凸塊之間形成-密封。具有—PqP結構之半導 體裝置之製造係參照以圖1A、1B、lc、1D、ie及圖2描 述0 、下列術語係可有利於對本發明之理解。請明白在文中所 述的術語係只用於描述之目的而並不應視為對其限制。 半導體封褒（或封裝）：一半導體封裝提供實體及電性界 面至至少-積體電路（IC)或晶粒以連接IC至外部電路。封 ，保護1C免受由諸如處理、加熱及製冷之因素所產生的損 二、:可染、及壓力Q為使其可靠及便於使用把扣放入封裝 的過程係被稱為半導體封裝總成，或簡單地稱為”總成"。、 13I56l.d〇, 200913222 積層基板：一基板係為一用於製造一半導體裝置之下層 材料。除提供底支撐外’基板係亦用於提供IC晶片與外部 電路之間的電性互連。被用於球栅陣列（BGA)封裝内以製 造半導體裝置之兩種基板包含剛性及帶式（tape)基板。剛 性基板係通常由薄層或積層之堆疊所組合，且常稱為積層 基板。該積層基板係通常由以諸如FR-4的聚合物為基礎的 材料所製成，或諸如BT(雙馬來醯亞胺三嗪之纖維增強 材料。其他類型的積層基板係包含一有機基板及一陶竟基 板。積層基板係通常包含多個導電層，例如，一，丨/2/1, 4 金屬層基板。在一些應用中，積層基板係包含一單一的電 介質層及一單一的金屬層。諸如各種通道之互連模式提供 電性耦合於多層之間。該等導電層通常包含結合至一聚合 物基板之金屬箱片的跡線。 球栅陣列（BGA): —積體電路表面安裝封裝以一附接於 具有線路層的基板之底側的焊球之區域陣列。該晶粒底係 利用晶粒與引線接合或覆晶互連以附接至基板。 圖1A根據一實施例係說明一具有封裝層疊封裝結構之半 導體裝置100的一多層空腔基板的簡化及示意橫截面圖。 圖1B根據一實施例對參照圖丨A所述之半導體裝置1〇〇之底 積層基板之頂視圖之進一步描述。參考圖丨A，半導體裝置 100之多層空腔基板包含一具有一阻障元件12〇的底積層基 板110。阻障元件120分離底積層基板11〇為一底中心部分 112及一周圍部分114。參考圖1B，底積層基板11〇之該阻 障元件120係形成一周圍壁118，其沿著底中心部分112之 131561.doc -10· 200913222 周長，從而包圍該底中心部分112。該阻障元件12〇可包含 任一經提鬲的結構，其自底中心部分112之平面上延伸。 該底中心部分112適以安裝至少一晶粒。底積層基板11〇之 周圍部分114係包含複數個觸片，其包含一底觸片116。
U 請回到圖1A，一圖框形頂積層基板13〇係經由複數個導 電凸塊150配置於及附接於底積層基板11〇之周圍部分 上。该頂積層基板130具有一開頂式中心部分丨32，其相配 於由周圍壁118所圍繞的底中心部分lu以形成一空腔 140。複數個導電凸塊15〇之每一者係配置於頂積層基板 130之頂觸片134與底積層基板110之周圍部分114之底觸片 116之間，從而在其間提供電性及機械耦合。其他用於附 接底積層基板1丨0至頂積層基板130之技術係可包含黏合劑 耦合。然巾，黏合劑耦合技術係需要在兩個積層基板之間 應用新的黏合劑材料，及使用新的互連技術，其兩者都承 受著一較高的費用及因此與經由複數個導電凸塊15〇之耦 合相比其存在更大的風險。 在一貫施例中，底積層基板110及頂積層基板13〇皆係為 剛性、多層積層基板。如上所述，剛性基板通常係由薄層 層疊或積層層之堆疊所組成，且其常常稱為積層基板。該 積層基板通常係由諸如FR_4之以聚合物為主之材料或諸如 BT(雙馬來醯亞胺三嗓）之纖維強化材料所製成。1他類型 的積層基板可包含-有機基板m基板4層基板之 厚度大約為15〇微米’同時更薄的或更厚的基板係可能基 於包含於-積層基板内的層之數量。在—示例性之未描述 13156I.doc 200913222 由—導電黏合 複數個導電跡 結合線區域、 的實施例中，
劑、一熱壓縮焊接、一高熔點焊接觸點、 線、連接、金屬平面、結合線、金屬連接、 導電片及其他類似方式所互連。在一實施例中，互連模式 係可能由各種諸如一導電黏合劑、一熱壓縮焊接、一高熔 點焊接觸點、複數個導電跡線、連接、金屬平面、結合 線金屬連接、結合線區域、導電片之電性連接技術所建 立。在一實施例令，底積層基板110係為一兩個或兩個以 上的金屬層基板’例如，-1/2/1基板，及頂積層基板13〇 係為至少一金屬層基板。 如文中所述之導電凸塊可以係在兩個基板之間提供互連 的任一導電元件。一導電凸塊係可藉由施加一可回熔的導 電材料至一觸片（諸如呈膏狀、粉末或薄膜形式之可回熔 焊料）所形成。其他用於形成導電凸塊的材料係可包含非 等向導電性膠。金屬諸如銅、金或其他合金係亦可被用於 形成導電凸塊。此外，傳統機械連接技術諸如彈簧、插 座及銷，可被用於提供互連。導電凸塊之形狀係可為凸 面之形式。除導電表面（諸如頂觸片134)以外，該頂積層基 板130之底表面係以一焊阻材料層136予以塗層。類似的， 除導電表面（諸如底觸片116)以外，該底積層基板110之頂 表面係以焊阻材料層13 6予以塗層。 阻障元件120在空腔14〇與複數個導電凸塊15〇之間形成 一密封。特別地，阻障元件12〇在頂積層基板13〇之底表面 上鄰接焊阻材料丨36以封閉任一間隙及開口，從而形成密 131561.doc •12· 200913222 封。阻障元件120之高度係等於複數個導電凸塊15〇之其中 -者與頂觸片134及底觸片116之其中每一者之高度所相加 之高度。在-實施例中，阻障元件12〇係自焊阻材料及黏 合材料中之一者形成。用於阻障元件120的材料係可能用 於硬化，從而使其變成一底積層基板11〇之主要部分。 下面所述係為以下的附加細節：製造底積層基板ιι〇之 過程’以焊阻材料形成的阻障元件12〇製造底積層基板ιι〇 之過程，及一以黏合劑材料形成的阻障元件1 20製造底積 層基板110之過程。在一實施例中，與使用黏合劑材料相 比在阻障元件12〇上使用焊阻材料係為可取，纟由於利用 焊阻材料的過程係為一分步過程，丨更均―，且在尺寸上 提供一更緊密的控制。 ，在特疋實施例中，底積層基板丨1 〇係利用下列流程進行 製造。引入材料4鑽孔—去汙—電鍍—感光膠膜（DF)積層 —曝光—顯影〜電鍍—去膜及蝕刻—外層積層—鑽孔—電 鍍S成像―去臈及蝕刻—塗覆焊阻劑（可採用薄膜或液體 焊阻劑卜可選用之部分固化(若需要，只適用於使用液體 焊阻劑曝光4顯影—完全固化。 在特定實施例中，具有阻障元件120的底積層基板110係 由—焊阻材料所形成且係可利用下列流程製造。引入材料 —鑽孔—去鑽汙〜電鍍—感光膠膜（DF)壓臈—曝光—顯影 電錢―去膜及钮刻—外層壓膜—鑽孔—電鍍—成像〜去 膜及蝕刻—塗覆焊阻劑—可選用之部分固化（若需要，只 適用於使用液體焊阻劑）—曝光—顯影—充分固化。因 131561.doc 200913222 此，除增加形成多層焊阻材料，每次一層、及曝光、顯 影、充分固化該等層之步驟外，用於製造阻障元件12〇之 過程係與製造底積層基板110之過程一樣。該成像及顯影 過程允S午非所希望的焊阻材料被移除。焊阻材料之層係建 立直至達到所希望的阻障元件120之高度。基板係被完全 固化（例如藉由利用紫外光線），以達到橫向連接至焊阻材 料。例如焊阻材料係可包含PFR 800，AUS 703，及AUS 705 〇 在一特定實施例中，具有阻障元件12〇的底積層基板11〇 係由一黏合劑材料形成且可利用下列流程進行製造。引入 材料—鑽孔—去鑽汙—電鍍—感光膠膜（DF)積層—曝光— 顯影—電鍍—去膜及蝕刻—外層積層—鑽孔—電鍍—成像 —去膜及餘刻—焊阻劑應用—可選用之部分固化（若需 要’只適用於使用液體焊阻劑曝光―顯影—充分固化 —分配黏合劑材料於頂中心部分之邊緣（例如位於周圍壁） 口化例如黏性阻障材料係可包含諸如住友Sumitomo CRP 3300T之環氧材料。 圖1C說明以參照圖iA及圖1B所述之覆蓋半導體裝置1〇〇 之至少一晶粒之多層空腔基板之簡化及示意橫截面圖。空 腔140係由底中心部分112、一阻障元件12〇之内表面及一 頂中心部分132之内表面所形成，其覆蓋至少一晶粒。在 所描述之實施例中’第一晶粒1 6〇係藉由晶粒附著化合物 (未顯示）附接至底中心部分112。第二晶粒162係附接至第 一晶粒160上。雖然所示之第一晶粒16〇及第二晶粒162係 131561.doc -14· 200913222 被連接至底中心部分112例如線結合連接，請明白諸如覆 晶或在某一晶粒及覆晶上的組合之不同的連接技術可被用 於將該等晶粒彼此相互地電性耦合或耦合至觸片。在一實 施例中，阻障元件120之高度係可為調整，其基於晶粒之 數量及使用的連接技術，諸如覆晶或線結合。在一實施例 中（未描述的實施例），包含在半導體裝置1 〇〇内之至少一晶 粒係為一微處理器、一數位信號處理器、一射頻晶片、一 記憶體、一微控制器、一特定應用積體電路、及一在一晶 片之系統或其結合之其中一者。 圖1D根據一實施例說明以參照圖1A、1B及圖⑴所述之 由一模塑化合物所填滿的半導體裝置1〇〇之空腔的簡化及 示意橫截面圖。在所述之實施例中，空腔14〇係以一聚合 或模塑化合物丨7〇填滿以保護第一及第二晶粒16〇及162。 該模塑化合物170係有利於防止空腔14〇由阻障元件12〇所 形成的密封之洩漏。該阻障元件12〇基本防止模塑化合物 170與複數個導電凸塊15〇接觸。即’阻障元件12〇建立一 配置於頂積層基板、底積層基板及密封之間的區域，其係 模塑化合物1 7 0之空隙。 圖1E根據一實施例說明以參照圖丨八、ib、ic及圖IQ所 述之具有一封裝層疊封裝結構之半導體裝置100之簡化及 w橫截面圖。諸如-記憶體晶片之頂封裝刚係被安裝 於頂積層基板130上以達到具有封裝層疊封裝結構之半導 體裝置100之總成。該頂封裝18〇係可能利用一球柵陣列 (BGA)麵合至頂積層基板13()。在—實施例中（未描述的實 131561.doc -15- 200913222 1)半導體裝置100可利用一球栅陣列（BGA)進行安 裝。 圖2係為說明—用於製造—具有封裝層疊封裝結構之半 導體裝置之方法的流程圖。在—特定實施例中，圖2說明 -用於製造描述於圖1A、1B、1C、丨咖之半導體裝置 100之過程。在步驟中 鄉1ϋ中形成具有一阻障元件之底積層 基板。4阻障元件使底積層基板分離成—底中心部分及一 周圍4分。阻障元件之形成係包含周圍壁圍繞底中心部分 =周長之形成以使其包圍該底中心部分。纟中心部分係可 安裝至^曰曰粒。該周圍部分包含複數個底觸片。在步驟 中，一框形頂積層基板係藉由結合一頂積層基板之頂 觸片及底積層基板之周圍部分之底觸片至配置於其中的複 數個導電凸塊之其中—個導電凸塊而附接於底積層基板。 忒頂積層基板係包含一開頂式中心部分，其相配於底中心 部分以形成-空腔。根據其中一種片上焊接方法來執行該 頂與底觸片結合至配置於其中的複數個導電凸塊。該結合 提供該底積層基板與該頂積層基板之間之機械及電性柄 合。在步驟230中，利用覆晶與線結合型互連之其中一者 將该至少一晶粒安裝於該底中心部分上。在步驟240中， 由模塑化合物填滿空腔以封裝該至少一晶粒。該阻障元件 基本防止模塑化合物與複數個導電凸塊的接觸。在步驟 250上，一頂封裝被安裝於頂積層基板以完成具有封裝層 疊封裝結構之半導體裝置之總成。 上述各種步驟係可以被增加、省略 '組合、改變、或以 131561.doc -16· 200913222 其他順序來執行。舉例說明，步驟22〇係可能分成用於形 成一頂積層基板之步驟及經由複數個導電凸塊用於附接頂 積層基板至底積層基板之步驟。 若干優點係由根據存在於文中的說明性實施例之方法及 系統所完成。該等實施例有利於藉由提供一阻障元件提供 一經改良的PoP結構，阻障元件係形成一密封以大體上防 止模塑化合物不流出於空腔。該半導體裝置具有經改良的 PoP結構，其藉由利用現有的積層基板材料及製程，及利 用現有的互連材料及製程（諸如片上焊接）可有利於對該裝 置的製造。利用現有的材料及製程係有利於多層材料承包 商執行該製造。與單塊基板設計或在無阻障元件之情況下 藉由黏附兩個積層基板相比，藉由利用兩個具有一阻障元 件的積層基板對空腔之形成係更具有成本效率。經由可選 擇的互連技術，諸如線結合及覆晶或其組合，空腔係可有 利於覆蓋連接至底積層基板之一個或多個晶粒。 對涉及本發明之熟練此項技術者應明白，所述之實施例 ^ 係僅為典型實例的執行，其他的實施例及變化係可包含於 所主張之本發明的範疇内。 【圖式簡單說明】 圖1A係根據一實施例說明一具有封裝層疊封裝結構之半 導體裝置的一多層空腔基板的簡化及示意橫載面圖； 圖1B係根據一實施例針對參照圖1A所述之半導體裝置 之底積層基板之俯視圖之詳細描述； 圖1C係根據一實施例說明覆蓋參照圖1A及圖1B所述之 131561.doc -17- 200913222 半導體裝置之至少一晶粒的多層空腔基板之簡化及示意橫 截面圖； 圖1D係根據一實施例說明針對參照圖〗A、汨及圖⑴所 述之由-帛塑化合物所填滿的半導體纟置之空腔的簡化及 示意橫戴面圖； 圖1E係根據-實施例說明針對纟照圖…及圖 ID所述之具有-封裝層4封裝之半導體裝置的簡化及示意 橫截面圖；及
一用於製造一具有一封裝層疊 圖2係根據一實施例說明 封裝之半導體裝置的方法。 【主要元件符號說明】 100 半導體裝置 110 底積層基板 112 底中心部分 114 周圍部分 116 低觸片 120 阻障元件 130 71積層基板 132 開頂式中心部分 134 了貝觸片 136 焊阻材料層 140 空腔 150 導電凸塊 160 第一晶粒 131561.doc 200913222 162 第二晶粒 170 模塑化合物 180 頂封裝 -19- 131561.doc

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  1. 200913222 十、申請專利範圍： 1. 一種半導體裝置，包括： -底積層基板，其具有由一阻障元件所分離的一底中 心部分及-周圍部分，該阻障元件形成一周圍壁以包圍 該底中心部分； -圖框形頂積層基板，其配置於該底積層基板之周圍 部分之上，該頂積層基板具有一開頂式中心部分，其相 配=由該周圍壁所包圍之該底中心部分以形成一空腔；及 ， I數個導電凸塊，該複數個導電凸塊之每一者係配置 於該頂積層基板之-頂觸片與該底積層基板之周圍部分 的-底觸片之間’以在其之間提供電性及機械耦合該 阻障元件在該空腔與該複數個導電凸塊之間形成一密 封。 2.如請求項丨之裝置，其進一步包括： 至少-附接於該底中心部分上的晶粒；及 -楔塑化合物，其用以封裝該至少一晶粒及填充該空 腔〇中配置於該頂積層基板、該底積層基板與該密封 1的區域係該模塑化合物之空隙。 3· Π，之裝置，其中該至少-晶粒包含-可作為- 曰曰:曰粒的第一晶粒及一可堆疊於該第一晶粒上的第二 曰曰:4 :該第二晶粒係可安裝為—線結合晶粒。 4·如5青求項9夕姑32 一 、，/、中該至少一晶粒包含一可安裝為 楚-曰 裝的第一晶粒及一可堆疊於該第一晶粒上的 弟一曰曰輪，兮楚-q · Μ第—日日粒可安裝為另一線結合封裝。 I3\561.doc 200913222 . 5.如請求項1 、1疋衮置，其中該阻障元件之高度係等於該 數個導雷 凸鬼之其中一者之高度加上該頂及底觸片之每 一者之高度。 如請求jf 1φ , 只K裝置’其中該阻障元件係由焊阻材料及黏 合劑材料之其中-者所形成。 如”月求項1之裝置’其中該阻障元件鄰接頂積層基板之 底表面以形成該密封。 8. 9. 如請求項1之裝置，其中除該等頂觸片外，該頂積層基 板之—底表面係塗有一焊阻材料層。 種製造具有一封裝層疊封裝結構的半導體裝置之方 法’該方法包括： 形成一配置於一底積層基板上的阻障元件，從而使該 底積層基板分離成一底中心部分及一周圍部分，其中該 阻障元件之形成包含形成一周圍壁以包圍可安裝至少一 晶粒的該底中心部分； 藉由結合該頂積層基板之一頂觸片及該周圍部分之一 底觸片至配置於其之間的複數個導電凸塊之其中一導電 凸塊，以將一圖框形頂積層基板附接至該底積層基板， 其中該頂積層基板包含一開頂式中心部分，其相配於該 底中心部分以形成一空腔； 安裝該至少一晶粒於該底中心部分上；及 藉由一模塑化合物填充該空腔以封裝該至少一晶粒， 其中配置於該頂積層基板、該底積層基板與該阻障元件 之間的區域係該模塑化合物之空隙。 131561.doc 200913222 10，如請求項^ 之方法，其進一步包括： 安 f 一丁5 4 ί裝於該頂積層基板以提供該封裝層疊封事 結構。 11. 如明求項9之方法，其中該頂及該底觸片與配置於其之 間的複數個導電凸塊之該結合係根據片上焊接方法執 行 ~、’、Q合在该底積層基板與該頂積層基板之間提供機 械及電性的耦合。 12. 如請求項9之方法’其中該至少一晶粒之安裝包含： 安裝—可安裝為覆晶晶粒的第一晶粒；及 安裝一第二晶粒於該第一晶粒上，該第二晶粒係可被 安裝為一線結合晶粒。 13. 如請求項9之方法’其中該阻障元件之該形成係包括由 一焊阻材料形成該阻障元件，及包含： 在該底積層基板之一區域上施加該焊阻材料，該底積 層基板具有該焊阻材料之一頂層，其中該經施加的區域 形成該周圍壁； 曝光及顯影該經施加的區域以移除該焊阻材料之不需 要的部分；及 完全地固化該經積層區域之焊阻材料以形成該阻障元 件0 131561.doc
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