TW200912880A - LCD driver IC and method for manufacturing the same - Google Patents
LCD driver IC and method for manufacturing the same Download PDFInfo
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- TW200912880A TW200912880A TW097133183A TW97133183A TW200912880A TW 200912880 A TW200912880 A TW 200912880A TW 097133183 A TW097133183 A TW 097133183A TW 97133183 A TW97133183 A TW 97133183A TW 200912880 A TW200912880 A TW 200912880A
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
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- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Description
200912880 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種液 B曰 顯 法。 裝置驅動積體電路及其製造方 【先前技術】 液晶顯示裝置驅動積體電路⑽)係為液晶顯示裝置〇iquld _Uisp丨ay ; LCD)驅動積體電路(integrated π)。液 晶顯示裝置之躲被劃分騎數個分區(_⑽),液晶顯示裝置 驅動積體祕㈣L林置之躲之每-分區。通常,若干 液晶顯示裝置轉積體電路帛 作業於紐之功率賴魏_轉_。液晶顯示裝 置驅動積體電路經常包含功率積體電路。 然而,用作需要高水準電流之功率積體電路之高壓積體電 路,包含大尺寸和高泄露水準。 降低高麗積體電路之尺寸和高泌露水準可以降低電流性能。 祕碰魏之電紐驗降低侧為,電流密度由於汲極 =之低劑置在沒極區域中變低,汲極區域係出於減少表面場 educe surface field ; Resurf)之目的被形成。 因此,本領域需要一種改善的功率積體電路。 【發明内容】 本發明實施例提供一種小尺寸液晶顯示裝置驅動積體電路及 200912880 其製造方法,可獲得高電流性能。 實施例之液晶顯示裝置驅動積體電路包含:第一導電類型 井’位於基板中;第二導電類型汲極區域,位於第—導電類型井 中,第隔_層$成於第二導電類型没極區域中;問極,开》成 於第-隔離層之第-側面處的基板之上;以及第二導電類型第— 離子植入區域’位於第—隔離層和·之_第二導電類型没極 區域中。 實施例之液晶顯示裝置驅動频電路之製造方法可包含:形 成第-導賴财於基板巾;形成第二導電類魏極區域於第二 導電井中’形絲-隔離層於第二導魏魏極區域·,形成閑極 於第一隔離層之第-側面處之基板上;以及形成第二導電類型第 -離子植人區域於第—隔離層和閘極之間的第二導電類型汲極區 域0 【實施方式】 驅動積體電路之製 以下,將結合圖式部份描述液晶顯示裝置 造方法之實施例。 、所述貫施例中,將要理解當—層(或膜)被稱為位於另 或基板,,之上〃時,它可直接地位於另—層或基板之上; 可以出現介入層。此外,將要理解當-層(或臈)被稱為位^ -層或縦m它可直接地位於另—層之下,並且還可 以出現-或多個介入層。另外,還要理解當一層被稱為位於兩層 200912880 之間’’時’它可為兩層之間的唯一層,或者還可以出現一或多個 介入層。 ,以了描述中,第-導電類型係指?型,第二導電類型係指N 型。但是,本發明之保護範圍並非限制於此。 #請參考「第i圖」,實施例之液晶顯示裝置驅動積體電路包含·· 第-導電類型井12G,形成祕板丨财;第二導電_祕區域 130,形成於第一導電類型井12〇中;第一隔離層i4〇a,形成於第 二導電類型汲極區域13〇中;.15〇,形成於第—隔離層勵 之-個側面處;以及第二導電_第—離子植人區域施,形成 於第一隔離層_和閘極15G之間的第二導電類型祕區域130 中。 再一實施例中,液晶顯示裝置驅動積體電路可包含:第二導 電類型第二離子植入區域170b,形成於第一隔離層14〇a之另一側 面處的第二導電類型汲極區域130中。因此,第二導電類型離子 植入區域170可被提供,包含第二導電類型第一離子植入區域i7〇a 和第二導電類型第二離子植入區域170b。 間隔物160可被形成於閘極15〇之橫向側面。 此外,第二隔離層14〇b可鄰接第一導電類型井12〇和第二導 電類型没極區域130而形成。第二隔離層14〇b可圍繞第一導電類 型井120之邊緣處的第二導電類型汲極區域13〇而形成。因此, 隔離層140可被提供,包含第一隔離層14〇a和第二隔離層14〇b。 200912880 依照實施例,第-隔離層H〇a可形成於第二導電類型没極區 域⑽之通道方向中,這樣基板中形成的電流路徑實質上可增加。 因此小的没極區域可用作大的汲極區域。 詳細地’透過形成第-隔離層140a於用作高壓源極或祕之 第二導電類魏麵域⑽之通道方向中,功率積體電路之尺寸 可被減少。 目此,汲極區域i3G可用作減少表面場。此時,小的汲極區 域可用作大的汲極區域。詳細地,電流流、_基板之表面,隔離 層形成於基板之上’這樣基板表面上的電流路徑可被增加,從而 使得小汲極區域用作大汲極區域。 此外,第一隔離層被提供於電場之形成區域中,從而分佈電 場。 依照貫施例,高濃度離子植入區域170a “A”形成於第一隔離 層140a和閘極150之間的沒極區域13〇中,這樣高壓積體電路之 電流密度可被增加。因此,可確保高壓積體電路之高電流性能。 詳細地,當形成高濃度離子植入區域170a時,用於功率積體 電路之裝置被形成。依照習知技術之高壓積體電路,高濃度離子 植入區域例如兩攙雜N型區域(Highly dopedN type region; HN+ ) 或回攙雜P型區域(Highly doped P type region ; HP+)被限制地 形成於預定區中。 然而,依照實施例’高壓裝置之N型或P型區域係開口狀, 200912880 銶高濃度離讀人區域可形成於射。就是說,不再需要赌 地疋義的用於植入之暴露區域。 “例如’使用開極150之橫向側面處形成的間隔物16〇作為緩 衝器,高濃度離子植入區域(㈣P+,携)可形成Μ型或p 型區域中。 就疋說,在「第丨圖」所示之接面輪廓巾,高濃度離子植入 區域可被形成於區域“A”中,這樣可確保功率積體電路之高電流密 度。依照f知技術,電流密度由於沒極區域之低劑量軒而變低: 但是,依照本發明實施例,高濃度離子植入區域被形成於區域“A” 中’這樣電流密度可增加。 — 下面參考「第2圖」和「第3圖」描述實施狀液晶顯示裝 置驅動積體電路之製造方法。 請參考「第2圖」,第一導電類型井12〇可形成於基板11〇中。 例如,p型離子可被植人基板no t,然後被驅動以形成高壓p 型井。 接下來’第二導電類型汲極區域13G可被形成於第一導電類 型井120中。例如’ N型離子可被植入P财,然後被驅動以形 成南壓N型沒極區域。 然後,隔離層140可被形成。隔離層14〇可包含第一隔離層 140a和第二隔離層140b,第一隔離層14〇a形成於第二導電類型 >及極區域130中,弟一隔離層140b形成於第二導電類型汲極區域 200912880 130之邊緣處。 例如,隔離層⑽可使用淺溝隔離(shaibwtrenehisdatiQn; STI)製程被形成。 依照實施例,第-隔離層140a可形成於波極區域130之通道 方向中,這樣基板中形成的電流路經實質上可增加。因此,小沒 極區域可用作大汲極區域。 ,請參考「第3圖」,閘極15〇可形雜第一隔離層顺 之側面處㈣’閘極15G可形成於第二導電類型汲極區域⑽ 之鄰接區域之第一導電類型井120之上。 接下來,間隔物160可形成於閘極15〇之橫向側面處。 第-V電類型南濃度離子植入區域17〇可使用間隔物】⑻作 為緩衝益透過植入離子至基板内而形成。 幻如透過植入第一導電類型離子至基板,第二導電類型第 ^ —離子植入區域17〇a可形成於第一隔離層馳和閘極15〇之間 的弟—導電類型沒極區域13〇中。 此外,第二導電類型第二離子植入區域170b可被形成於第一 離層l4〇a之另一側之第二導電類型汲極區域13〇中。 此時,第二導電類型第一離子植入區域170a和第二導電類型 第一離子植入區域17〇1)可同時或順序地形成。 依照實施例,高濃度離子植入區域170a “A”形成於第一隔離 層140a和閘極15〇之間的第二導電類型汲極區域13〇中,這樣高 10 200912880 壓積體電路之電流密度可被增加。因此,可確保高縫體電路之 高電流性能。 依照液晶顯示裝置驅動積體電路之製造方法之實施例,隔離 層更形成於汲麵域之通道方向巾,這樣基板中形成的電流路徑 實質上可增加,從而使得小的汲極區_作大的汲極區域。 此外,依照實施爿,高濃度離子植入區域形成於隔離層和閘 極之間躲_射,這樣紐積體電路之f絲度可被增加。 因此’可確保高壓積體電路之高電流性能 本說明書f -個實施例'匕實施例β、,,實施例實例,, 等表示聯繫本判至少—鱗關t包含的該倾倾描述特別 特徵、結構或特點。說明書中不同位置出現的這種術語並非必須 全=酬實_。此外,當特綱特徵、結構或特點係結合
任思貝把麻述日·^ ’在本領域技術人員的熟悉翻内結合其他實 施例會影響特徵、結構或義。 、 軸本發明以前述之實施例揭露如上’然其並非用以限定本 屬本發明和範,所為之更動與_,均 :發:爾、圖式以及申請專利範圍之内主題組合排 或排列。除了組件部和/或剩之更動與修正之外,本躺 技術人員_還可看出其他使財法。 【圖式簡單說明】 11 200912880 第1圖所示為本發明實施例之液 剖面圖;以及 晶顯示裝置驅動積體 電路之 第2圖和第3圖所示為本發明 體電路之製造程序之剖視圖。 實施例之液轉示裝置驅動積
【主要元件符號說明】 110 120 130 140 140a 140b 150 160 170 170a 170b 基板 第一導電類型井 第二導電類型汲極區域 隔離層 第一隔離層 第二隔離層 間隔物 第二導電類型離子植入區域 第一離子植入區域 第一離子植入區域 12
Claims (1)
- 200912880 十、申請專利範圍·· 1. 一種液晶顯示裝置驅動積體電路,包含有: —第一導電類型井,位於一基板中; —第二導電類型汲極區域,位於該第一導電類型井中; 一第一隔離層,位於該第二導電類型汲極區域中; 一閘極,位於該第一隔離層之一第一側面處的該基板之 上;以及 -第二導電類型第-離子植人區域,位於該第—隔離層和 該閘極之間的該第二導電類型汲極區域中。 2.如申請專利範圍第!項所述之液晶顯示裝置驅動積體電路,更 二第一導電類型第二離子植入區域,位於該第一隔離層之 一第二側面處之該第二導電類型汲極區域中。 V. 申。月專利補第1項所述之液晶顯示裝置轉積體電路 包含-間隔物,位於該閘極之—橫向側面處。 中::專利耗圍第1項所述之液晶顯示I置1_積體電路, 中該弟二料_第-料獻區域包含 雪 類型離子。 农又罘一導電 5. 一種液晶_示裝置驅動積體電路之製造方法,包含: 形成〜第-導電類型井於一基板中; 域=第二導電類魏極區域於該第—導電類型井中; 开滅〜第—隔離層於該第二導電類奴極區域; 形成1極於該第一隔離層之一第一側面處之該基板 13 200912880 上;以及 形成帛一導電類型第一離子植入區域於該第—隔離層 和該閘極之間的該第二導電類魏極區域。 6’ =申請專利_第5項所述之液晶顯稀置驅動積體電路之製 ^方法更包合在形成該閘極之後,形成—第二導電類型第二 離子植人區域於該第-隔離層之__第二侧面處之該第二導電 類型汲極區域。 / 7. 如申請專概圍第6項之液晶齡裝置鱗频電路之製 造方法,該第二導電類型第一離子植入區域和該第二導電類型 第一離子植入區域同時被形成。 8. 如申請專概圍第5項所述之液晶顯示裝置驅動積體電路之製 造方法,更包含形成一間隔物於該閘極之一橫向側面處。 9·如申轉利範圍第8項所述之液晶顯示裝置驅動積體電路之製 (; &方去,其中形成該第二導電類型第一離子植入區域包含使用 該間隔物作為一緩衝層完成一離子植入製程。 14
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KR1020070088245A KR100940625B1 (ko) | 2007-08-31 | 2007-08-31 | 엘씨디 구동 칩 및 그 제조방법 |
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JP (1) | JP2009060107A (zh) |
KR (1) | KR100940625B1 (zh) |
CN (1) | CN101378081A (zh) |
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US8222130B2 (en) | 2009-02-23 | 2012-07-17 | Globalfoundries Singapore Pte. Ltd. | High voltage device |
US8053319B2 (en) * | 2009-02-23 | 2011-11-08 | Globalfoundries Singapore Pte. Ltd. | Method of forming a high voltage device |
US8236640B2 (en) | 2009-12-18 | 2012-08-07 | Intel Corporation | Method of fabricating a semiconductor device having gate finger elements extended over a plurality of isolation regions formed in the source and drain regions |
JP6460349B2 (ja) | 2016-04-13 | 2019-01-30 | トヨタ自動車株式会社 | 車両走行制御装置 |
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KR100214855B1 (ko) * | 1995-12-30 | 1999-08-02 | 김영환 | 정전기 방지용 트랜지스터 및 그의 제조방법 |
JPH10107272A (ja) * | 1996-09-27 | 1998-04-24 | Rohm Co Ltd | 高耐圧半導体装置およびその製造方法 |
US6310380B1 (en) * | 2000-03-06 | 2001-10-30 | Chartered Semiconductor Manufacturing, Inc. | Electrostatic discharge protection transistor structure with a trench extending through the source or drain silicide layers |
DE10131705B4 (de) * | 2001-06-29 | 2010-03-18 | Atmel Automotive Gmbh | Verfahren zur Herstellung eines DMOS-Transistors |
KR20030052693A (ko) * | 2001-12-21 | 2003-06-27 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조방법 |
US20030134479A1 (en) * | 2002-01-16 | 2003-07-17 | Salling Craig T. | Eliminating substrate noise by an electrically isolated high-voltage I/O transistor |
US6930005B2 (en) * | 2003-12-02 | 2005-08-16 | Texas Instruments Incorporated | Low cost fabrication method for high voltage, high drain current MOS transistor |
KR20040010445A (ko) * | 2003-12-15 | 2004-01-31 | 실리콘허브주식회사 | 고전압 모오스 트랜지스터의 구조 및 그 제조방법 |
KR101068139B1 (ko) * | 2004-04-30 | 2011-09-27 | 매그나칩 반도체 유한회사 | Ldmosfet 제조방법 |
JP2007123729A (ja) * | 2005-10-31 | 2007-05-17 | Seiko Epson Corp | 半導体装置 |
KR100710194B1 (ko) * | 2005-12-28 | 2007-04-20 | 동부일렉트로닉스 주식회사 | 고전압 반도체소자의 제조방법 |
KR100734302B1 (ko) * | 2006-01-12 | 2007-07-02 | 삼성전자주식회사 | 집적도를 향상시킬 수 있는 반도체 집적 회로 소자 및 그제조방법 |
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- 2008-08-28 JP JP2008220394A patent/JP2009060107A/ja active Pending
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US20090059111A1 (en) | 2009-03-05 |
JP2009060107A (ja) | 2009-03-19 |
KR20090022686A (ko) | 2009-03-04 |
CN101378081A (zh) | 2009-03-04 |
DE102008039882A1 (de) | 2009-03-05 |
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