TW200903759A - Semiconductor package and semiconductor device using the same - Google Patents

Semiconductor package and semiconductor device using the same Download PDF

Info

Publication number
TW200903759A
TW200903759A TW097123884A TW97123884A TW200903759A TW 200903759 A TW200903759 A TW 200903759A TW 097123884 A TW097123884 A TW 097123884A TW 97123884 A TW97123884 A TW 97123884A TW 200903759 A TW200903759 A TW 200903759A
Authority
TW
Taiwan
Prior art keywords
pad
semiconductor package
frame
semiconductor
semiconductor device
Prior art date
Application number
TW097123884A
Other languages
English (en)
Other versions
TWI445146B (zh
Inventor
Yuka Tamadate
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200903759A publication Critical patent/TW200903759A/zh
Application granted granted Critical
Publication of TWI445146B publication Critical patent/TWI445146B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01009—Fluorine [F]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

200903759 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體封裝及一種使用該半導體封 裝之半導體裝置，及更特定言之，係關於一種包括使用於 BGA(球栅陣列（Ball Grid Array))或LGA(平面柵格陣列 (Land Grid Array))連接之覆晶（fiip_chip)連接墊及悍 盤（land pad)的半導體封裝，及一種使用該半導體封裝之 半導體裝置。 【先前技術】 在使用於行動電話或數位相機的半導體封裝及使用該 半導體封裝的半導體裝置中，希望增加密度及減小尺寸。 在具有肖加密度及減小尺寸之半導體封裝及半導體裝置 ^裝技術中’使用半導體晶片的覆晶連接結構為有^的 在覆晶連接結構中，晶片裝置區❹之 隔係相當小，即在高密度以 填充樹脂。…’使用具低黏度的樹脂作為底部 :使用具低黏度之底部填充樹脂的 ==地*覆_區域流出。習知”= 名化而可能被忽略。然而，當減小半 地 且半導體晶片及增加其他電子组二身之尺寸 部填充樹脂之流出可山 女裝毯、度時，會有底 的可能性。 了“利地影響周圍晶片及電子組件 97123884 200903759 近年來，有一種經由將另一车道 晶連接之半導體元件的半導體裝導 詈體破置安裝在具有經覆 置透過LGA連接彼此相連且使㈣半導體裝 此半導體裝置中，需要一種形 =㈣半導體裝置。在 由保護抗㈣層“之料充樹脂經 流至設置於半導體封 連接或LGA連接焊盤的方式包;^腸 7 a匕固日日片安裝區域。
[專利文件 1] JP-A-2006-351 559 圖14係顯示在包括覆 之半導體封裝之製造的中 曰曰連接塾及BGA或LGA連接焊盤 間之步驟的說明圖。 :形成於4*導體凡件10上之凸塊12(金凸塊)(見圖⑵ 接口至覆晶連接墊16’同時將焊球或連接插料接至偏 連接或LGA連接焊盤18。因此，焊料包覆至覆晶連接塾 16中之銅墊的表面。此外，於職連接或lga連接焊盤 18中亦可使用銅墊。然而，為使焊盤18更適當，應將電 鍍層36(例如’鎳電鍍層及金電鍍層)施加至銅墊之表面。 在將鎳電鍍層及金電鍍層施加至嬋盤18之情況中，在 形成基板14之步‘驟，將饰線圖案、覆晶連接塾16及烊盤 18形成於基板〗4之表面上，隨後先將電鐘層％施加至 作為焊盤18的塾部分，且如此將㈣他包覆至作為覆 晶連接藝16之藝部分。 a更明確s之，當要將電鍍層36施加至作為焊盤。的墊 4刀〗8a b•，將作為覆晶連接墊】6的墊部分丨塗佈抗 電鍍劑以施加電鍍層36,及當要將作為覆晶連接墊16之 97123884 200903759 墊部分168焊料塗佈焊料粉末52日寺，將遮蔽膠帶42黏著 至焊盤18且如此塗佈焊盤18。 焊盤18係設置在包圍其中形成覆晶連接塾16之區域的 外部區域中，且由保護抗钮劑層形成壤d以包圍並中形成 "々丨L /、形成焊盤18的區域，且提供壩D以自樹 1旨t板31或防焊劑38向上突出。如前所述，黏著遮蔽膠 帶4 2以屏蔽焊盤1 a。妙_ 册 ，由於形成壩D，因此遮蔽膠 π42痛法平坦地黏著於其中形成焊盤Μ的區域。因此， 會有如圖14所示於遮蔽膠帶42與其中形成焊盤18之區 域之間產生間隙S的問題。在將作為覆晶連接塾μ之整 部^ 16a焊料塗佈焊料粉末52的情況中，將—黏性溶液 黏者^墊部分16a。因此，當於此狀態供給黏性溶液時， 黏!·生岭液自其中形成焊盤j 8之區域與遮蔽膠帶仏之間的 V =至其中形成焊盤18之區域中’或者焊料粉末 者至知盤18 ’以致無法保護焊盤以表面上的電鍍層 36，而導致一瑕疵產品。 【發明内容】 一因此’本發明係要解決該等問題且具有一目的在於提供 :種具有透過包括覆晶連接及脱連接或—連接之不同 導ί =所獲得之連接塾的半導體封裂，及一種使用該半 裝的半導體裳置，其中能可靠地進行各連接塾中之 表面處理’且生產效率係高的。 根據本發明之第—態樣，提供一種半導體封裝，其包括： 97123884 200903759 形成有一焊盤之一區域， 連接塾之一區域’該形成有該焊盤之區域 係，又置在形成有該覆晶連接墊之區域的外側上，及 焊盤保牛’在形成以暴露該形成有該烊盤之區域中之 該保護構件包括： -框形結構部，設置成包圍該覆晶連接墊，及 一支«膜部’設置於該框形結構部之外側上。 裝㈣—態樣之半導體封 的=撐薄膜部係形成為類似自外侧包圍該框形結構部 裝根=發明之第三態樣，提供根據第一態樣之半導體封 的4膜部係形成為類似在該框形結構部之外側上 根據本發明之g m @ Μ mm3r , 4樣，提供根據第一至第三態樣中任 1樣之半導體封裝，其中， 任 側^支按謂部係形成於該焊盤之最外部周邊位置的外 用==可黏著-遮蔽膠帶，而不會對形成有 隙。因此，、妾或LGA連接之該焊盤的區域產生餘 封裝的製造成I進半導體封裝的良率，以致可降低半導體 97123884 200903759 此外’根據本發明之第五態樣，提供根據第一至第四態 樣中任一態樣之半導體封裝，其中， 、該框形結構部及該支撐薄膜部係以彼此相同的高度形 此可各易以平坦地黏著該遮蔽膠帶，而不會對形成 有用於進行該BGA連接或該LGA連接之該焊盤的區域產生 餘隙。因此’可進一步增進半導體封裝的良率。此外，可 進一步降低半導體封裝的製造成本。 此外，根據本發明之第六態樣，提供一種半導體聚置， 其中將半導體τό件裝置於根據第—至第五態樣中任一能 樣之半導體封裝上，其中， 〜 該安裝於半導體封裝上的半導體元件係透過一覆晶連 接而連接。 再者，根據本發明之第七態樣，提供一種半導體裝置， 其中， 、 將根據第六態樣之半導體裝置係以垂直方向層疊，及 將在上層側之該半導體裝置中的一外部連接端子連接 至在下層侧之該半導體裝置中的一焊盤。 此外，可將不同類型的半導體封裝層疊於根據本發明的 半導體封裝上。 根據本發明之半導體封裝及使用該半導體封裝之半導 體裝置’即使在具有透過一覆晶連接及-BGA連接或-LGA，連接之不同連接部之半導體封裝及使用該半導體封裝 之半導體裝置中用於防止底部填充樹脂流出的該框形結 97123884 200903759 構部亦可於各連接墊中可靠地進 撐薄膜部俦透奶 p F ^ 處理°此外，該支 存涛膜4係透過一防焊劑形成在形成有 中。因此，可減低各半導體封I及 Μ坏盤之區域 此，可與得且右+導體聚置的翹曲。因 ί ^具有小尺寸及W質时導體料及半導體裝 【實施方式】 將參照附圖根據本發明之一 下。圖系顯示用以例詳細說明於 … 很课具體例之製造本逡舻私驻 裝的平面圖W據具體例之半導體封 衣扪十面圖（圖11A)及沿平 ΠΒ)。圖i至1〇中之却⑽ 之A~A、線的剖面圖(圖 口 1至ίο中之剖面圖係沿圖UA中之 圖1係顯示將抗蝕劑圖案形成於具有單 樹脂基板上之狀態的剖面圖銅匕覆之 ikm ^ m ^ , 柷蝕幻圖案34係經由將抗 =膜33包覆至經黏著至樹脂基板3G之㈣31上， 及曝光及顯影抗蝕劑薄膜。浐益 淨欲土 - 、 抗钱为彳圖案34係經形成為 塗佈未:於圖中的預定佈線圖案，及用於進行⑽連= L=之覆晶連接墊16及焊盤18的圖案部分。 圖2係顯示將佈線圖幸 為覆晶連接塾及焊盤之執_；f於树月曰板上’且同時形成作 圖荤 之墊之狀態的剖面圖。於形成抗蝕劑 形成佈線圖宰、作為覆作為遮罩來姓刻銅羯，以致 為尸般从、為覆日日連接墊16的墊部分16a、及作 除y 、墊部分18a。於㈣後，將抗#劑圖案34移 圖3係顯不僅使防焊劑包覆自樹脂基板之表面暴露之 97123884 200903759 =曰連接塾及焊盤之塾部分之狀態的剖面圖。將樹脂 :=為=連接塾16的塾部分16a及作為谭盤18的 墊口 ί3刀18a自樹脂基板3〇之表面。 般：狀能的I「於作為烊盤之墊部分上進行電鍍以形成焊 盤之狀態的剖面圖。在并且骑 /、體例中，依序施加鎳電鍍層及 盤ι8Γ^1作為電料36。當要將㈣層施加至作為焊 之塾口P分18a日夺’以遮罩屏蔽形成有墊部分i6a之 此以使電鑛溶液不會黏著至作為覆晶連㈣ σ 〃 16a的方式電鍍’此未示於圖巾。關於遮罩， 可使用例如抗電錢劑。 圖5係顯示將框形結構部及支撐薄膜部形成於包圍盆 =覆晶連接塾設置於形成有烊盤之區域中之區域之配 中之狀態的剖面圖。將設置有蟬盤18之區域中之防焊 劑38的上表面塗佈作為保護構件之第二層的防焊劑⑽， 且同㈣成用於防止底部填充樹脂37流出的框形結構部 =及與框形結構部39A具有相等高度的支撐薄膜部 。框形結構部39A係沿其中形成有墊部分.之區域 的周圍而提供’且支撐薄膜部39β具有與框形結構部謝 相等之高度，並係形成類似於平面上所見之框架以包圍框 形結構部39A。 、如圖5所示’框形結構部39A係以足夠高度及寬度形 成以防止底#填充樹脂37流出。此外，支撐薄膜部39β 係在形成有連接塾18之區域中以與框形結構部心相等 97123884 200903759 :厂 成為類似框架。因此’可抑制半導體封 圖⑴及m)及使用半導體封u之半導體裝 圖⑵的趣曲。因此，可提供具有高度平坦度的' 裝60及半導體裝置7〇。 一、 更明確言之’當於覆晶連接後將半導體元件Μ翻轉至 上側之狀態中自前側觀看半導體裝置7〇時，已 叙置70會變形而呈向上外凸的 _加至半導體封裝60之::：:因此’經由將防焊 丁守脰玎衣ϋϋ之基板兩次，可提高使 而呈外凸形狀的應力。因此，可減低於半導 體裝置70上所產生的翹曲。 圖6係顯示以遮蔽膠帶遮蔽形成有焊盤之區域之狀能 的剖面圖。當將焊料包覆至墊部分心之表面時，使^ 蔽膠帶42於防止焊料粉末黏著至焊盤18的表面。如圖6 所示，框形結構部39A及支撐薄膜部39β之表面係位在焊 盤18之表面的上侧上。因此，將遮蔽膠帶42分別黏著至 框形結構部39A及支撐薄膜部39B之上表面，使其設置在 框形結構部39A與支撐薄膜部39B之間。 為了以遮蔽膠帶42可靠地覆蓋形成有焊盤18的區域， 較佳將至少一支撐薄膜部39β設置在距提供有最外部焊 盤18之位置更外側的位置上。 在使用於此具體例之遮蔽膠帶42中，基礎材料係由聚 氯乙烯基樹脂所形成，且黏著劑係由丙烯酸樹脂所形成。 即使黏著劑殘留於焊盤18中，遮蔽膠帶42之黏著層係由 既不會妨礙BGA連接亦不會妨礙LGA連接的材料所形成。 97123884 13 200903759 然而，由於遮蔽膠帶42係如圖6所示離開焊盤 而黏著，因此黏著劑並不會黏著至焊盤〗8之表面。 為使用之目的，將遮蔽膠帶42實際上從由樹脂: :成離，並黏著至目標物。經由將遮蔽膠帶 烊結構部㈣及支撐薄膜部之表面， ί
接下來，將焊料包覆至作為覆晶 先’將黏著層50形成於在圖6所示之加工件二表:J = 的表面上。經由將加工件^ ’於丙烯酸化合物所構成之黏著 = =：Τ6…_成黏二Si 面2监黏者至由銅所形成之塾部分16a的表 :件=而’料盤18塗佈遮蔽膠帶42。因此，即使將加 4二：t至黏著劑之溶液容器中，黏著劑之溶液亦不 ^者 8。圖7係顯示進行該處理之狀態的剖面 部：：來/將焊料粉末52黏著至作為覆晶連接墊16的墊 2=::在—Ϊ情況中將稱作塾部分_。圖8係 的刊面p/ T末黏者至作為覆晶連接塾之塾部分之狀態 粉末52係自加工件4〇之上方喷灑，並因 末分16a之表面。落於塾部们6a上之焊料粉 部分it :著層50黏著至墊部分16a之表面。落在除塾 除。此：二基板表面上的焊料粉末52於清潔步驟被移 ' ^4步驟’由於焊盤18經遮蔽膠帶42塗佈， 97123884 14 200903759 因而不會有妨礙。在此具體例巾 焊料粉末52。 體财’❹由㈣所形成的 =至塾部分16a之表面的焊料粉末52於回焊㈣㈣ =軌融，且因此黏著至墊部㈣a之表面。在此具體例 二先=粉末52係暫時黏著至墊部分16a作為回焊步驟 的先别4。暫時黏著步驟可輕度地炫融焊料粉末Μ及 粉末52,因此溶融至塾部分…。實際上 力:熱爐中在大約nrc下將基板加熱大 時地黏著焊料粉末52。在製程進行至暫時黏著步驟= :=::42剝離。於暫時黏著步驟後，即使焊盤以未 广“ 42塗佈’外來物質亦不會黏著至烊盤18之表 面0 义 s圖在9 基板之表面塗佈助炫劑之狀態的剖面 = 之:=示之將_板3°之上表 ，性及焊二: = = 得之焊輸的流動 ”至—刀1 6a的接合特性。為泠 54,較佳使用熟知方法。 4塗佈助熔劑 圖1〇係顯示於回焊步驟後將經 :::包覆至覆晶連接㈣面之狀態二二=: 融且:進行至回禪步驟’其中焊料粉末52炫 融且知科52a包覆至作為覆晶連接墊16 表面。於回焊步驟後，將祕劑54清潔並移/ a的 闕於透過黏著層5G將焊料粉末52㈣至谭墊部分… 97123884 15 200903759 之表面及透過回焊將焊料52a包覆至墊部分16a之表面的 方法，可利用例如JP-A-7-7244公開案中所述之方法。 經由如别所述开> 成包括覆晶連接塾1 6及焊盤18之基 板，然後再將外部連接端子15裝附至形成於樹脂基板3〇 之下表面上之墊P，可獲得圖11A及11β中所示之半導體 封裝60。在半導體封裝6〇中，框形結構部39Α及形成為 類似框架以於框形結構部39Α之外侧上包圍框形結構部 3 9 Α的支撐薄膜部3 9 Β係利用作為保護構件之第二層的防 焊劑39所形成，以暴露位在形成有覆晶連接墊16之區域 外侧上之形成有焊盤18之區域中的焊盤18。在圖nA及 11B所示之半導體封裝60中，框形構件係由位於兩位置 處的支撐薄膜部39B所形成。 此外，框形結構部39A及包圍框形結構部39A之支撐薄 膜部39B及39B係以彼此相等的高度形成。因此，當要將 黏著劑之溶液施加至覆晶連接墊16之墊部分16a時，能 以遮蔽膠帶42可靠地塗佈形成有焊盤丨8的區域。因此， 關於覆晶連接墊16，焊料52a可僅包覆至墊部分丨6a之 表面。再者，關於焊盤18，可僅將預定的電鍍層％施加 至墊部分18a之表面。因此，可透過覆晶連接及BGA連接 或LGA連接來安裝半導體元件或另一半導體封裝。 根據此具體例之製造半導體封裝60之方法的特徵在於 進行以下步驟：將遮蔽膠帶42如同橋般地黏著至框形結 構部39A及在包圍框形結構部39A之配置中以與框形結構 部39A之相等高度所形成的支撐薄膜部39B，因而平坦地 97123884 16 200903759 黏著遮蔽膠帶42，且當在樹脂基板30中形成覆晶連接墊 16及焊盤18時，在防止焊盤18有形成有焊盤18之部分 暴露至外侧的狀態下形成覆晶連接墊16。經由以遮蔽= 帶42完全塗佈焊盤18而不留下間隙，能可靠地進行^ 護，以致於防止焊料包覆至焊盤18。此外，可容易地進 行將遮蔽膠帶42黏著至框形結構部39A及支撐薄膜部39β 或自;t开ν、’’σ構39Α及支杈薄膜部3gB剝離遮蔽膠帶42 ί 在體封裝60之方法中’亦可提出一種塗佈液 態抗關以覆蓋焊盤18之方法作為另— 便將焊料包覆至覆晶連接塾16之方法。然而 二！=執需施加抗蝕劑，然後透過曝光及顯影使形成有 驟==:T16a之區域暴露。其會有生產力因複雜步 52之後將/飾題°此外’在此方法中’於黏著焊料粉末 之後將抗蝕劑層移除。基於此理由，會有當 劑層時’焊料粉末52亦可能被移除的問題。田一 使用遮蔽膠帶42來製造丰導體抖胜 當地被利用作為女曰Λ 〇之方法由於可適 利用作為大1生產半導體封裝 在不產生問題且有效方面係優異的。％際方法，而 在將半導體元件10安裝 較佳將半導體元件覆晶連接至# 60上的情況中’ 部填充樹脂37注入至半導接墊16 ’及將底 接合區域中。 ，、覆晶連接墊16的 會產生加熱生 在注入底部填充樹脂37的一些情況中 97123884 17 200903759 出的氣體。框形結構部39A及支撐薄膜部39B係突出至浐 形成有焊盤18之區域中之焊盤18之表面位置高的位置二 ，此’可防止加熱生出的氣體與焊盤18接觸，因而保護 焊盤^勺表面。因此，可適當地維持焊盤18的表面處理 之狀態(例如，鎳電鍍層及金電鍍層）。圖12係顯示使用 根據此具體例之半導體封裝之半導體裝置之一結構之 例的剖面圖。 1 本發明可構成為具有所謂之POP結構的半導體裝置 70,其中將如前所述所形成的半導體裝置7〇a及7⑽如圖 13所示垂直地層4。於下層側上之半導體裝χ 及於 上層側上之半導體裝置7〇A可透過於上層側上之半導體 裝置70A之外部連接端子的焊球15A而彼此電連接。防止 底部填充樹脂37流至焊盤18，及維持接合性質。因此， 亦月b可罪地進仃於上層側及下層側上之半導體裝置 及70B的電連接。 如前所述，於下層侧上之半導體裝置7〇β中的焊盤Μ 受到保護，㈣止在透過框形結構部及支撐薄膜部 39B注入底部填充樹腊37時來自底部填充樹脂π的加執 生出的氣體。因此’可以高品質狀態進行於上層侧上之半 導體裝置70A中的焊球15A及於下層侧上之半導體裝置 70B的知盤18之連接。因此，可增進連接的可靠度。 ，雖然本發明已基於具體例詳細說明於上，但本發明並不 受限於該具體例’而且當然有各種變化可屬於本發明的技 術範圍，而不脫離本發明的料。雖然已在具體例中就當 97123884 18 200903759 將遮蔽膠帶42黏著至形成有焊盤丨8之區域時形成具有與 框形結構部39A相等高度且自外側包圍框形結構部39A之 框形支撐薄膜部39β的組態作說明，但例如，支撐薄膜部 39Β並不需總是形成如同框架。此外，在產生本發明之優 點的範圍内’支撐薄膜部39Β之高度並不需總是與框形結 構部39Α的高度相等。 支撐薄膜部39Β可以遮蔽膠帶42連同框形結構部 一起平坦地屏蔽形成有焊盤18之區域的内部即足夠，且 其可形成如同格栅或分散點；再者’亦可採用將支撐薄膜 部39Β設置於形成有焊盤18之區域的整個内部而僅使焊 盤18部分暴露的組態。此外，亦可採用將複數個支撐薄 膜部39Β形成於框形結構部39Α之外側上的組態。 此外，當然，可採用能防止於製造中在半導體封裝6 〇 及半導體裝置70中翹曲的產生之支撐薄膜部39Β的佈線 圖案。 t： 雖然在此具體例中已就如圖4所示將樹脂基板3〇之整 個表面塗佈作為第一層之防焊劑38 ,及進行曝光及顯影 以僅使作為覆晶連接墊1 6之墊部分16a及作為焊盤丨8之 F刀18a暴路至樹脂基板30之表面，且將作為第二層 之防焊劑包覆至形成有焊盤18之區域，以致如圖5所示 形成框形結構部39A及支撐薄膜部39β的組態作說明，但 卜亦可經由使用不將作為第一層之防焊劑3 8包覆至 成有设晶連接墊16之區域’而係由作為第一層之防焊 背1 3 8形成框形結構部及支撐薄膜部的組態來獲得與此具 97123884 19 200903759 體例相同的功能及優點。 雖然在此具體例中已就將安裝於半導體封裝60之基板 之上#部中之半導體封裝60透過BGA連接而將半導體元件 政置於其上的組態作說明，但此外，安裝於半導體封 裝60之基板上部之半導體封裝60中的半導體元件10卷 /二係透過除BGA連接之外的打線接合而連接。 雖然於此具體例中已說明單—的基板部分或半導體封 :’/旦亦可製造#中將大量的半導體封裝60製造為-大 2基板的半‘體封裝作為加玉件，及於實際製程中於最 、;衣造階段將加工件分割成小件。 【圖式簡單說明】 圖i係、顯示將抗則^圖案形成於具有單側以銅包覆之 树月曰基板上之狀態的剖面圖。 ^係顯示將佈線圖案形成於樹脂基板上，且同時 作為覆晶連接塾及焊盤之塾之狀_剖面圖。 作L3曰係：示僅使防焊劑包覆暴露至樹脂基板之表面之 作為後曰曰連接墊及焊盤之塾部分之狀態的剖面圖。 圖4係顯示將電鍍層施加至作為焊般少勒加八、，v 焊盤之狀態的剖面圖。至作Μ盤之㈣分以形成 圖5係顯示將框形結構 中將覆晶連接塾設置二么支f薄臈部形成於包圍其 置中之狀態的剖面圖。區域中之區域的配 的=顯示以遮蔽膠帶遮蔽形成有焊盤之區域之狀態 97123884 20 200903759 圖7係顯示將黏著層形成於覆晶連 態的剖面圖。 衣囬上之狀 分示將㈣粉末黏著至作為覆晶連接墊之墊部 刀之狀悲的剖面圖。 =係顯示將基板之表面塗佈助溶劑之狀態的剖面圖。 的回焊步驟後將經由炼融焊料粉末所獲得 / 〇 復曰曰連接墊之表面之狀態的剖面圖。 剖顯示根據具體例之半導體封裝之結構的 置rirt使用根據具體例之半導體封裝之半導體裝 罝之 '、，《構之範例的剖面圖。 圖13係顯示其中垂直岸最柄 旦右pnp&碰 罝層且根據具體例之半導體裝置之 八有POP結構之半導體裝置之 少 衣κ結構的剖面圖。 圖14係顯示在包括覆晶連接 ^ ^ 墊及BGA或LGA連接焊盤 ,+V體封裝之製造的中間之步驟的說明圖。 【主要7G件符號說明】 10 半導體元件 12 凸塊 14 基板 15 外部連接端子 15A 焊球 16 覆晶連接墊 16a 墊部分 18 焊盤 97123884 21 200903759 f l 18a 墊部分 30 樹脂基板 31 銅猪 34 抗蝕劑圖案 36 電鍍層 37 底部填充樹脂 38 防焊劑 39 防焊劑；保護構件 39A 框形結構部 39B 支撐薄膜部 40 加工件 42 遮蔽膠帶 50 黏著層 52 焊料粉末 52a 焊料 54 助溶劑 60 半導體封裝 70 半導體裝置 70A 半導體裝置 70B 半導體裝置 D 壩 P 塾 S 間隙 97123884 22

Claims (1)

  1. 200903759 十、申請專利範圍： 1. 一種半導體封裝，其包括： 形成有一焊盤之一區域， ^形成有覆晶連接墊之一區域，該形成有一焊盤之區域 系又置在該幵/成有一覆晶連接塾之區域的外侧上，及 保護## ’形《為暴露該形成有該谭盤之區 • 盤，其中， δ亥保濩構件包括： :框形^構部，設置成包圍該覆晶連接墊，及 支撐薄膜部，設置於該框形結構部之外側上。 ^如申請專利範圍第1項之半導體封裝，其中， 3亥支撐薄膜部係形成為類似自外側包圍該框形結構i 的框架。 P如申請專利範圍第1項之半導體封裝，其中， 5亥支撐薄膜部係形成為類似在該框形結構部之外侧 的分散點。 _ 4.如申：專利範圍第1項之半導體封裝，其中， 側：支撐薄膜部係形成於該焊盤之最外部周邊位置的夕1 如申請專利範圍第之半導體封裝，其_， 成该框形結構部及該支㈣膜部似彼此相同的高度 ::-種半導體裝置，其中將一半導 利範圍第！項之半導體封裝上，其中，女裝、申-97123884 23 200903759 該安裝於半導體封裝上的半 接而連接。 導體元件係透過一 覆晶連 7. —種半導體裝置，其中， 將申請專利範圍第6項之該等半導體裝置以垂直方。 層疊，及 ^ 將在上層側之該半導體裝置中的一外部連接端子連接 至在下層側之該半導體裝置中的一焊盤。 97123884 24
TW097123884A 2007-06-27 2008-06-26 半導體封裝及使用其之半導體裝置 TWI445146B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007168495A JP4986738B2 (ja) 2007-06-27 2007-06-27 半導体パッケージおよびこれを用いた半導体装置

Publications (2)

Publication Number Publication Date
TW200903759A true TW200903759A (en) 2009-01-16
TWI445146B TWI445146B (zh) 2014-07-11

Family

ID=40159431

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097123884A TWI445146B (zh) 2007-06-27 2008-06-26 半導體封裝及使用其之半導體裝置

Country Status (4)

Country Link
US (1) US7825499B2 (zh)
JP (1) JP4986738B2 (zh)
CN (1) CN101335253B (zh)
TW (1) TWI445146B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI796336B (zh) * 2017-10-24 2023-03-21 台灣積體電路製造股份有限公司 半導體結構及其製造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8217514B2 (en) * 2008-04-07 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with warpage control system and method of manufacture thereof
JP5058929B2 (ja) * 2008-09-29 2012-10-24 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
TWI501352B (zh) * 2009-03-26 2015-09-21 Stats Chippac Ltd 具有翹曲控制系統之積體電路封裝系統及其製造方法
US8952552B2 (en) * 2009-11-19 2015-02-10 Qualcomm Incorporated Semiconductor package assembly systems and methods using DAM and trench structures
KR101067216B1 (ko) * 2010-05-24 2011-09-22 삼성전기주식회사 인쇄회로기판 및 이를 구비하는 반도체 패키지
JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5709309B2 (ja) * 2011-03-28 2015-04-30 京セラサーキットソリューションズ株式会社 配線基板
CN103165566B (zh) 2011-12-19 2016-02-24 先进封装技术私人有限公司 基板结构、半导体封装件及半导体封装件的制造方法
US8710681B2 (en) * 2012-05-31 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation rings for blocking the interface between package components and the respective molding compound
JP6125209B2 (ja) * 2012-11-19 2017-05-10 株式会社ジェイデバイス 半導体装置及びその製造方法
TWI492344B (zh) * 2013-04-09 2015-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP6586629B2 (ja) 2014-04-17 2019-10-09 パナソニックＩｐマネジメント株式会社 半導体パッケージ及び半導体装置
KR102412611B1 (ko) * 2015-08-03 2022-06-23 삼성전자주식회사 인쇄회로기판(pcb)과 그 제조방법, 및 그 pcb를 이용한 반도체 패키지 제조방법
US20180226271A1 (en) 2017-01-31 2018-08-09 Skyworks Solutions, Inc. Control of under-fill using a film during fabrication for a dual-sided ball grid array package

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5220200A (en) * 1990-12-10 1993-06-15 Delco Electronics Corporation Provision of substrate pillars to maintain chip standoff
JPH06268101A (ja) * 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
US5973393A (en) * 1996-12-20 1999-10-26 Lsi Logic Corporation Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits
JPH11297889A (ja) * 1998-04-16 1999-10-29 Sony Corp 半導体パッケージおよび実装基板、ならびにこれらを用いた実装方法
JP2000114918A (ja) * 1998-10-05 2000-04-21 Mitsubishi Electric Corp 表面弾性波装置及びその製造方法
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6600224B1 (en) * 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US20040012097A1 (en) * 2002-07-17 2004-01-22 Chien-Wei Chang Structure and method for fine pitch flip chip substrate
TW549592U (en) * 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
DE10239081B4 (de) * 2002-08-26 2007-12-20 Qimonda Ag Verfahren zur Herstellung einer Halbleitereinrichtung
TW561602B (en) * 2002-09-09 2003-11-11 Via Tech Inc High density integrated circuit packages and method for the same
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JP3929922B2 (ja) * 2003-03-18 2007-06-13 富士通株式会社 半導体装置とその製造方法、および半導体装置前駆体とその製造方法
US7057277B2 (en) * 2003-04-22 2006-06-06 Industrial Technology Research Institute Chip package structure
JP2006351559A (ja) 2003-06-23 2006-12-28 Shinko Electric Ind Co Ltd 配線基板および配線基板への半導体チップ実装構造
US7145226B2 (en) * 2003-06-30 2006-12-05 Intel Corporation Scalable microelectronic package using conductive risers
US7180165B2 (en) * 2003-09-05 2007-02-20 Sanmina, Sci Corporation Stackable electronic assembly
JP4843214B2 (ja) * 2004-11-16 2011-12-21 株式会社東芝 モジュール基板およびディスク装置
JP2006156544A (ja) * 2004-11-26 2006-06-15 Denso Corp 基板の実装構造およびその実装方法
JP4520355B2 (ja) * 2005-04-19 2010-08-04 パナソニック株式会社 半導体モジュール
US20070023904A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
CN1949487A (zh) * 2005-10-10 2007-04-18 南茂科技股份有限公司 可防止密封材料溢流的膜上倒装片封装结构
JP4703356B2 (ja) * 2005-10-19 2011-06-15 パナソニック株式会社 積層型半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI796336B (zh) * 2017-10-24 2023-03-21 台灣積體電路製造股份有限公司 半導體結構及其製造方法

Also Published As

Publication number Publication date
US20090001606A1 (en) 2009-01-01
JP4986738B2 (ja) 2012-07-25
CN101335253A (zh) 2008-12-31
TWI445146B (zh) 2014-07-11
US7825499B2 (en) 2010-11-02
CN101335253B (zh) 2012-06-13
JP2009010073A (ja) 2009-01-15

Similar Documents

Publication Publication Date Title
TW200903759A (en) Semiconductor package and semiconductor device using the same
TWI357645B (en) Structure of super thin chip scale package and met
TWI239056B (en) Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof
TWI600129B (zh) 玻璃覆晶接合結構
TWI323933B (en) Semiconductor package with plated connection
JP5764256B2 (ja) 支持端子パッドを有する半導体チップ
JP2009010073A5 (zh)
TW200525666A (en) Bump-on-lead flip chip interconnection
TW561602B (en) High density integrated circuit packages and method for the same
TW200828559A (en) Semiconductor device and manufacturing method of the same
TW200416787A (en) Semiconductor stacked multi-package module having inverted second package
TW200830500A (en) Wafer level package with die receiving through-hole and method of the same
TW200423318A (en) Multi-chip package substrate for flip-chip and wire bonding
TW550800B (en) Integrated circuit package without solder mask and method for the same
CN107785325A (zh) 半导体封装及其制造方法
TWI234209B (en) BGA semiconductor device with protection of component on ball-planting surface
CN108281397A (zh) 芯片封装结构及封装方法
WO2012171320A1 (zh) 一种新的接触式智能卡的封装方法
JPWO2015198837A1 (ja) 半導体装置およびその製造方法
TW200808143A (en) PCB electrical connection terminal structure and manufacturing method thereof
TWI336516B (en) Surface structure of package substrate and method for manufacturing the same
TW200529388A (en) Chip package
TW200408095A (en) Chip size semiconductor package structure
TW200915458A (en) Test socket and test board for wafer level semiconductor testing
TWI375307B (en) Flip chip package structure and method for manufacturing the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees