TW200735312A - Wafer level package including a device wafer integrated with a passive component - Google Patents

Wafer level package including a device wafer integrated with a passive component

Info

Publication number
TW200735312A
TW200735312A TW095109200A TW95109200A TW200735312A TW 200735312 A TW200735312 A TW 200735312A TW 095109200 A TW095109200 A TW 095109200A TW 95109200 A TW95109200 A TW 95109200A TW 200735312 A TW200735312 A TW 200735312A
Authority
TW
Taiwan
Prior art keywords
level package
wafer
passive component
wafer level
polymer layer
Prior art date
Application number
TW095109200A
Other languages
English (en)
Other versions
TWI315569B (en
Inventor
Qing Gan
Robert W Warren
Anthony J Lobianco
Steve X Liang
Original Assignee
Skyworks Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Skyworks Solutions Inc filed Critical Skyworks Solutions Inc
Publication of TW200735312A publication Critical patent/TW200735312A/zh
Application granted granted Critical
Publication of TWI315569B publication Critical patent/TWI315569B/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
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TW095109200A 2005-04-01 2006-03-17 Wafer level package including a device wafer integrated with a passive component TWI315569B (en)

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Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10203397B4 (de) * 2002-01-29 2007-04-19 Siemens Ag Chip-Size-Package mit integriertem passiven Bauelement
GB0330010D0 (en) * 2003-12-24 2004-01-28 Cavendish Kinetics Ltd Method for containing a device and a corresponding device
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
US7576426B2 (en) * 2005-04-01 2009-08-18 Skyworks Solutions, Inc. Wafer level package including a device wafer integrated with a passive component
JP4891994B2 (ja) * 2005-06-30 2012-03-07 シーメンス アクチエンゲゼルシヤフト 外部からの不正操作に対するセンシティブな電子装置データモジュールを保護する回路担体およびそれを用いた電子装置データモジュールへの不正アクセスの検出方法
EP1976004B1 (en) * 2005-12-28 2017-02-15 A.L.M.T. Corp. Semiconductor element mounting substrate, semiconductor device using the same, and process for producing semiconductor element mounting substrate
US7635606B2 (en) * 2006-08-02 2009-12-22 Skyworks Solutions, Inc. Wafer level package with cavities for active devices
US20080217708A1 (en) * 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
US20080308922A1 (en) * 2007-06-14 2008-12-18 Yiwen Zhang Method for packaging semiconductors at a wafer level
US7968978B2 (en) * 2007-06-14 2011-06-28 Raytheon Company Microwave integrated circuit package and method for forming such package
KR100927418B1 (ko) * 2007-09-28 2009-11-19 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
CN101878527B (zh) 2007-11-30 2012-09-26 斯盖沃克斯瑟路申斯公司 使用倒装芯片安装的晶片级封装
DE102007060632A1 (de) * 2007-12-17 2009-06-18 Robert Bosch Gmbh Verfahren zum Herstellen eines Kappenwafers für einen Sensor
US8900931B2 (en) 2007-12-26 2014-12-02 Skyworks Solutions, Inc. In-situ cavity integrated circuit package
US7989262B2 (en) 2008-02-22 2011-08-02 Cavendish Kinetics, Ltd. Method of sealing a cavity
KR100980810B1 (ko) 2008-03-26 2010-09-10 주식회사 제이엠엘 웨이퍼 레벨-칩 스케일 패키지가 가능한 이미지 센서 모듈 및 그 제조방법
US7993950B2 (en) * 2008-04-30 2011-08-09 Cavendish Kinetics, Ltd. System and method of encapsulation
US7863699B2 (en) * 2008-05-21 2011-01-04 Triquint Semiconductor, Inc. Bonded wafer package module
DE102008025202B4 (de) * 2008-05-27 2014-11-06 Epcos Ag Hermetisch geschlossenes Gehäuse für elektronische Bauelemente und Herstellungsverfahren
US8035219B2 (en) * 2008-07-18 2011-10-11 Raytheon Company Packaging semiconductors at wafer level
US8018821B2 (en) * 2008-09-30 2011-09-13 Intel Corporation Protection layers for media protection during fabrication of probe memory device
JP4972633B2 (ja) * 2008-12-11 2012-07-11 日東電工株式会社 半導体装置の製造方法
US7955885B1 (en) 2009-01-09 2011-06-07 Integrated Device Technology, Inc. Methods of forming packaged micro-electromechanical devices
JP5300558B2 (ja) * 2009-03-27 2013-09-25 日東電工株式会社 半導体装置の製造方法
KR101067133B1 (ko) * 2009-08-17 2011-09-22 삼성전기주식회사 원통형 캐패시터를 구비한 웨이퍼 레벨 패키지 및 그 제조방법
WO2011037534A1 (en) * 2009-09-25 2011-03-31 Agency For Science, Technology And Research A wafer level package and a method of forming a wafer level package
TWI420988B (zh) * 2009-10-14 2013-12-21 Wintec Ind Inc 垂直結構被動元件的裝置和方法
US8987830B2 (en) * 2010-01-12 2015-03-24 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
US8574960B2 (en) 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
KR100976813B1 (ko) 2010-04-23 2010-08-20 옵토팩 주식회사 전자 소자 패키지 및 그 제조 방법
US8969176B2 (en) 2010-12-03 2015-03-03 Raytheon Company Laminated transferable interconnect for microelectronic package
US8535983B2 (en) * 2011-06-02 2013-09-17 Infineon Technologies Ag Method of manufacturing a semiconductor device
US8987898B2 (en) * 2011-06-06 2015-03-24 International Rectifier Corporation Semiconductor wafer with reduced thickness variation and method for fabricating same
TWI447889B (zh) * 2011-08-05 2014-08-01 Chipmos Technologies Inc 晶片封裝結構
US8624359B2 (en) * 2011-10-05 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package and method of manufacturing the same
DE102012206732A1 (de) * 2012-04-24 2013-10-24 Robert Bosch Gmbh Verfahren zum Herstellen eines hybrid integrierten Bauteils
DE102012112058B4 (de) 2012-12-11 2020-02-27 Snaptrack, Inc. MEMS-Bauelement und Verfahren zur Verkapselung von MEMS-Bauelementen
US9470710B2 (en) * 2013-02-27 2016-10-18 Texas Instruments Incorporated Capacitive MEMS sensor devices
US9556017B2 (en) * 2013-06-25 2017-01-31 Analog Devices, Inc. Apparatus and method for preventing stiction of MEMS devices encapsulated by active circuitry
TWI527166B (zh) * 2013-07-25 2016-03-21 The package structure of the optical module
US9208938B2 (en) * 2013-10-02 2015-12-08 Globalfoundries Inc. Inductor structure having embedded airgap
US9123626B1 (en) * 2014-02-27 2015-09-01 Texas Instruments Incorporated Integrated passive flip chip package
JP6339229B2 (ja) 2014-12-03 2018-06-06 インテル・コーポレーション 電子パッケージを作製する方法
CN105347289A (zh) * 2015-10-09 2016-02-24 锐迪科微电子（上海）有限公司 适用于芯片级封装的密闭结构及其制造方法
US10629468B2 (en) * 2016-02-11 2020-04-21 Skyworks Solutions, Inc. Device packaging using a recyclable carrier substrate
CN105762085B (zh) * 2016-04-01 2019-01-01 江苏长电科技股份有限公司 金属圆片埋孔型表面声滤波芯片封装结构及制造方法
CN105870077A (zh) * 2016-04-01 2016-08-17 江苏长电科技股份有限公司 埋孔型表面声滤波芯片封装结构及其制造方法
CN105810597B (zh) * 2016-04-01 2018-10-09 江苏长电科技股份有限公司 金属圆片级埋孔型表面声滤波芯片封装结构的制造方法
CN105742255B (zh) * 2016-04-01 2018-10-09 江苏长电科技股份有限公司 金属圆片级凹槽埋孔型表面声滤波芯片封装结构及方法
CN105742195A (zh) * 2016-04-01 2016-07-06 江苏长电科技股份有限公司 一种蚀刻埋孔型表面声滤波芯片封装结构的制造方法
US10453763B2 (en) 2016-08-10 2019-10-22 Skyworks Solutions, Inc. Packaging structures with improved adhesion and strength
KR20180134237A (ko) * 2017-06-08 2018-12-18 (주)와이솔 웨이퍼레벨패키지 및 제조방법
DE102017212796A1 (de) * 2017-07-26 2019-01-31 Robert Bosch Gmbh Elektrische Baugruppe
US10472228B2 (en) * 2017-08-17 2019-11-12 Advanced Semiconductor Engineering, Inc. MEMS device package and method for manufacturing the same
US10854533B2 (en) * 2018-03-26 2020-12-01 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
US11075173B2 (en) * 2018-10-31 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming same
US11316550B2 (en) 2020-01-15 2022-04-26 Skyworks Solutions, Inc. Biasing of cascode power amplifiers for multiple power supply domains
US11450630B2 (en) 2020-10-27 2022-09-20 Cirrus Logic, Inc. Coupling of integrated circuits (ICS) through a passivation-defined contact pad

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323051A (en) 1991-12-16 1994-06-21 Motorola, Inc. Semiconductor wafer level package
US5448014A (en) * 1993-01-27 1995-09-05 Trw Inc. Mass simultaneous sealing and electrical connection of electronic devices
US5561085A (en) * 1994-12-19 1996-10-01 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
US5798557A (en) 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
US5893726A (en) 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication
DE19801312A1 (de) 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
EP0951068A1 (en) 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
JP2000114413A (ja) 1998-09-29 2000-04-21 Sony Corp 半導体装置、その製造方法および部品の実装方法
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6566745B1 (en) * 1999-03-29 2003-05-20 Imec Vzw Image sensor ball grid array package and the fabrication thereof
US6498114B1 (en) 1999-04-09 2002-12-24 E Ink Corporation Method for forming a patterned semiconductor film
US6265246B1 (en) 1999-07-23 2001-07-24 Agilent Technologies, Inc. Microcap wafer-level package
KR20020066321A (ko) 1999-09-03 2002-08-14 듀폰 디스플레이즈, 인크. 유기 전자 장치의 캡슐 밀봉
US6297551B1 (en) 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
US6452238B1 (en) 1999-10-04 2002-09-17 Texas Instruments Incorporated MEMS wafer level package
US6750521B1 (en) 1999-10-22 2004-06-15 Delphi Technologies, Inc. Surface mount package for a micromachined device
JP3597754B2 (ja) * 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2002016181A (ja) 2000-04-25 2002-01-18 Torex Semiconductor Ltd 半導体装置、その製造方法、及び電着フレーム
US6214644B1 (en) 2000-06-30 2001-04-10 Amkor Technology, Inc. Flip-chip micromachine package fabrication method
TW457657B (en) 2000-07-14 2001-10-01 Jou Jeng San Wafer-level packaging of micro electromechanical elements and fabrication method thereof
US6402970B1 (en) 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6530515B1 (en) 2000-09-26 2003-03-11 Amkor Technology, Inc. Micromachine stacked flip chip package fabrication method
US6630725B1 (en) 2000-10-06 2003-10-07 Motorola, Inc. Electronic component and method of manufacture
US6358773B1 (en) 2000-12-27 2002-03-19 Vincent Lin Method of making substrate for use in forming image sensor package
WO2002058233A1 (en) * 2001-01-18 2002-07-25 Infineon Technologies Ag Filter devices and method for fabricating filter devices
US6525420B2 (en) 2001-01-30 2003-02-25 Thermal Corp. Semiconductor package with lid heat spreader
JP4055368B2 (ja) 2001-02-27 2008-03-05 日本電気株式会社 二次電池
JP2002261190A (ja) 2001-02-28 2002-09-13 Sony Corp 半導体装置、その製造方法及び電子機器
US6773962B2 (en) * 2001-03-15 2004-08-10 General Electric Company Microelectromechanical system device packaging method
US6926057B2 (en) * 2001-09-25 2005-08-09 Dainippon Screen Mfg. Co., Ltd. Thin film forming apparatus and thin film forming method
TWI312166B (en) * 2001-09-28 2009-07-11 Toppan Printing Co Ltd Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board
TW560018B (en) * 2001-10-30 2003-11-01 Asia Pacific Microsystems Inc A wafer level packaged structure and method for manufacturing the same
US6787897B2 (en) 2001-12-20 2004-09-07 Agilent Technologies, Inc. Wafer-level package with silicon gasket
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
JP2003218256A (ja) 2002-01-21 2003-07-31 Kyocera Corp 電子部品収納用パッケージ
US6660564B2 (en) 2002-01-25 2003-12-09 Sony Corporation Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US7045459B2 (en) 2002-02-19 2006-05-16 Northrop Grumman Corporation Thin film encapsulation of MEMS devices
US6838309B1 (en) 2002-03-13 2005-01-04 Amkor Technology, Inc. Flip-chip micromachine package using seal layer
CN100446243C (zh) * 2002-03-19 2008-12-24 Nxp股份有限公司 堆叠有绝缘腔的芯片
KR100850879B1 (ko) 2002-05-15 2008-08-07 엘지이노텍 주식회사 저온 소성 세라믹을 이용한 안테나 스위치
US7059048B2 (en) 2002-06-07 2006-06-13 Intel Corporation Wafer-level underfill process making use of sacrificial contact pad protective material
JP4892171B2 (ja) 2002-06-13 2012-03-07 日立化成工業株式会社 多層配線板の製造方法および多層配線板
DE10228593A1 (de) * 2002-06-26 2004-01-15 Infineon Technologies Ag Elektronisches Bauteil mit einer Gehäusepackung
SE0202681D0 (sv) * 2002-09-10 2002-09-10 Frank Niklaus Hermetic sealing with combined adhesive bonding and sealing rings
SG111972A1 (en) 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
JP4342174B2 (ja) * 2002-12-27 2009-10-14 新光電気工業株式会社 電子デバイス及びその製造方法
US6872589B2 (en) 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same
DE10310617B4 (de) 2003-03-10 2006-09-21 Infineon Technologies Ag Elektronisches Bauteil mit Hohlraum und ein Verfahren zur Herstellung desselben
US6812558B2 (en) 2003-03-26 2004-11-02 Northrop Grumman Corporation Wafer scale package and method of assembly
US6743991B1 (en) * 2003-04-14 2004-06-01 Agilent Technologies, Inc. Polymeric liquid metal switch
US20040259325A1 (en) 2003-06-19 2004-12-23 Qing Gan Wafer level chip scale hermetic package
JP4269806B2 (ja) 2003-06-30 2009-05-27 カシオ計算機株式会社 半導体装置およびその製造方法
US7368808B2 (en) * 2003-06-30 2008-05-06 Intel Corporation MEMS packaging using a non-silicon substrate for encapsulation and interconnection
US7203394B2 (en) 2003-07-15 2007-04-10 Rosemount Aerospace Inc. Micro mirror arrays and microstructures with solderable connection sites
US7045868B2 (en) 2003-07-31 2006-05-16 Motorola, Inc. Wafer-level sealed microdevice having trench isolation and methods for making the same
US6777263B1 (en) 2003-08-21 2004-08-17 Agilent Technologies, Inc. Film deposition to enhance sealing yield of microcap wafer-level package with vias
US20050054133A1 (en) 2003-09-08 2005-03-10 Felton Lawrence E. Wafer level capped sensor
US7275424B2 (en) 2003-09-08 2007-10-02 Analog Devices, Inc. Wafer level capped sensor
US20050085016A1 (en) 2003-09-26 2005-04-21 Tessera, Inc. Structure and method of making capped chips using sacrificial layer
KR20050040589A (ko) * 2003-10-29 2005-05-03 삼성전기주식회사 광도파로가 형성된 인쇄회로 기판 및 그 제조 방법
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
KR100604334B1 (ko) 2003-11-25 2006-08-08 (주)케이나인 플립칩 패키징 공정에서 접합력이 향상된 플립칩 접합 방법
US20050139984A1 (en) 2003-12-19 2005-06-30 Tessera, Inc. Package element and packaged chip having severable electrically conductive ties
US7961478B2 (en) 2004-04-16 2011-06-14 Nxp B.V. Integrated circuit, and a mobile phone having the integrated circuit
US7061099B2 (en) 2004-09-30 2006-06-13 Intel Corporation Microelectronic package having chamber sealed by material including one or more intermetallic compounds
US7198725B2 (en) * 2004-11-05 2007-04-03 Chi-Yen Shen Method for making a surface acoustic wave device package
US7202560B2 (en) * 2004-12-15 2007-04-10 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Wafer bonding of micro-electro mechanical systems to active circuitry
US7169649B2 (en) * 2004-12-16 2007-01-30 Palo Alto Research Center, Inc. Wafer scale integration of electroplated 3D structures using successive lithography, electroplated sacrificial layers, and flip-chip bonding
JP2006237406A (ja) 2005-02-25 2006-09-07 Toshiba Corp 樹脂封止型電子部品装置
US20060211233A1 (en) 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
US7576426B2 (en) 2005-04-01 2009-08-18 Skyworks Solutions, Inc. Wafer level package including a device wafer integrated with a passive component
US7323675B2 (en) 2005-09-21 2008-01-29 Sigurd Microelectronics Corp. Packaging structure of a light-sensing device with a spacer wall
US7635606B2 (en) 2006-08-02 2009-12-22 Skyworks Solutions, Inc. Wafer level package with cavities for active devices
US20080217708A1 (en) 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package

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