KR100976813B1 - 전자 소자 패키지 및 그 제조 방법 - Google Patents
전자 소자 패키지 및 그 제조 방법 Download PDFInfo
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- KR100976813B1 KR100976813B1 KR1020100037978A KR20100037978A KR100976813B1 KR 100976813 B1 KR100976813 B1 KR 100976813B1 KR 1020100037978 A KR1020100037978 A KR 1020100037978A KR 20100037978 A KR20100037978 A KR 20100037978A KR 100976813 B1 KR100976813 B1 KR 100976813B1
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Abstract
본 발명의 실시 예들은 소자층을 보호하기 위한 패시베이션층과 폴리머층이 형성된 전자 소자와, 전자 소자와 대향하여 배치된 기판 어셈블리와, 전자 소자와 기판 어셈블리 사이에 형성되며, 실링 영역을 둘러싸는 폐루프 형상으로 형성된 실링 링을 포함하며, 실링 링은 적어도 일측면이 폴리머층과 접하여 패시베이션층 상에 형성되는 전자 소자 패키지 및 그 제조 방법을 제공한다.
본 발명의 실시 예들에 의하면, 실링 링이 형성되는 영역에 형성된 마이크로렌즈 및 컬러 필터 등의 폴리머층을 제거하고 패시베이션층 상에 실링 링을 형성함으로써 실링 링과 조인트의 높이를 균일하게 형성할 수 있어 전기적인 결함을 방지할 수 있다.
Description
도 2는 도 1의 A-A' 라인을 따라 절취한 상태의 단면도.
도 3은 본 발명의 일 실시 예에 따른 포토 센서 패키지의 제조 방법을 설명하기 위한 공정 순서도.
도 4(a) 내지 도 4(f)는 도 3의 공정 순서에 따른 공정 단면도.
도 5(a) 및 도 5(b)는 종래의 SnAg를 이용한 실링 링 및 터짐이 발생된 상태의 단면 사진.
도 6은 본 발명의 일 실시 예에 따른 구리와 SnAg를 이용한 실링 링의 단면 사진.
도 7은 본 발명의 다른 실시 예들에 따른 포토 센서 패키지의 단면도.
300 : 연결부 400 : 실링 링
410 : 실링층 420 : 접합층
430 : 실링 링 패드
Claims (20)
- 소자층을 보호하기 위한 패시베이션층과 폴리머층이 형성된 전자 소자;
상기 전자 소자와 대향하여 배치된 기판 어셈블리; 및
상기 전자 소자와 기판 어셈블리 사이에 형성되며, 실링 영역을 둘러싸는 폐루프 형상으로 형성된 실링 링을 포함하며,
상기 실링 링은 적어도 일 측면이 상기 폴리머층과 접하여 상기 패시베이션층 상에 형성되는 전자 소자 패키지.
- 제 1 항에 있어서, 상기 전자 소자는 포토 센서, MEMS 소자, 실리콘 베이스 소자, GaAs 베이스 소자, InP 베이스 소자를 포함하는 전자 소자 패키지.
- 제 2 항에 있어서, 상기 기판 어셈블리는 광에 대하여 투명, 반투명 또는 불투명 기판을 이용할 수 있고, 전기적으로 도전성, 반도체성 또는 절연성 기판을 포함하는 전자 소자 패키지.
- 제 1 항에 있어서, 상기 패시베이션층은 상기 전자 소자의 전체 영역에 형성되며, 상기 폴리머층은 상기 실링 영역의 상기 패시베이션층 상에 형성되는 전자 소자 패키지.
- 제 4 항에 있어서, 상기 패시베이션층은 실리콘 옥사이드(SiO2), TEOS, 실리콘 나이트라이드(SiN), 실리콘 카바이드(SiC), 실리콘 옥시나이트라이드(SiON), 다이아몬드 혼합물을 포함하는 어느 하나 또는 이들의 혼합물을 단일층 또는 적어도 둘 이상을 적층하여 형성되는 전자 소자 패키지.
- 제 4 항에 있어서, 상기 폴리머층은 컬러 필터 및 마이크로렌즈를 포함하는 전자 소자 패키지.
- 제 1 항에 있어서, 상기 실링 링은 실링층 및 접합층이 적층되어 형성된 전자 소자 패키지.
- 제 7 항에 있어서, 상기 접합층은 상기 실링층보다 융점이 낮은 저융점 물질층이 상기 실링층과 반응하여 형성되며, 금속간 화합물인 전자 소자 패키지.
- 제 8 항에 있어서, 상기 실링층은 구리, Au, Sn, SnAg, SnAgCu, Ag, Ni중 적어도 어느 하나를 이용하는 전자 소자 패키지.
- 제 8 항에 있어서, 상기 저융점 물질층은 Sn, SnAg, Ti/In/Au, Bi, In중 적어도 어느 하나를 이용하는 전자 소자 패키지.
- 제 8 항에 있어서, 상기 실링층 및 저융점 물질층은 각각 구리와 Sn, 구리와 SnAg, Au와 Ti/In/Au의 적층 구조, Sn과 Bi, SnAg와 Bi, SnAgCu와 Bi, Ag와 In, Ni와 Sn의 어느 하나를 이용하는 전자 소자 패키지.
- 제 11 항에 있어서, 상기 접합층은 CuSn, CuSnAg, AuIn, SnBi, Sn,AgBi, SnAgCuBi, AgIn, NiSn의 어느 하나로 형성되는 전자 소자 패키지.
- 제 1 항에 있어서, 상기 실링 링 외측에 형성되며, 상기 패시베이션층과 접촉하여 형성된 조인트를 더 포함하는 전자 소자 패키지.
- 제 1 항에 있어서, 상기 실링 링 내측에 형성되며, 상기 폴리머층과 양 측면이 접촉하고 밑면이 상기 패시베이션층과 접촉하여 형성된 조인트를 더 포함하는 전자 소자 패키지.
- 제 1 항에 있어서, 상기 실링 링 외측에 형성된 수지 실링을 더 포함하는 전자 소자 패키지.
- 기판 상에 패시베이션층 및 폴리머층이 적층된 전자 소자가 제공되는 단계;
상기 폴리머층의 일부를 제거하는 단계;
상기 폴리머층이 제거된 전자 소자 또는 상기 폴리머층이 제거된 영역에 대응되는 영역의 기판 어셈블리의 어느 하나 상에 실링층 및 저융점 물질층을 적층 형성하는 단계;
상기 실링층 및 저융점 물질층이 형성되지 않은 상기 전자 소자 또는 기판 어셈블리의 어느 하나 상에 실링 링 패드를 형성하는 단계;
상기 저융점 물질층과 상기 실링 링 패드가 대응되도록 상기 전자 소자 및 기판 어셈블리를 접촉시키는 단계; 및
상기 저융점 물질층을 용융시켜 상기 실링층 및 실링 링 패드와 반응시켜 접합층을 형성하는 단계를 포함하는 전자 소자 패키지 제조 방법.
- 제 16 항에 있어서, 상기 폴리머층은 폐루프 형상으로 제거하는 전자 소자 패키지 제조 방법.
- 제 16 항에 있어서, 상기 실링층 및 저융점 물질층은 상기 전자 소자 상에 형성되며, 상기 실링층 및 저융점 물질층과 이격되어 상기 패시베이션층 상에 조인트를 형성하는 전자 소자 패키지 제조 방법.
- 제 18 항에 있어서, 상기 조인트는 상기 실링층 및 저융점 물질층과 동일 물질로 동시에 형성되는 전자 소자 패키지 제조 방법.
- 제 16 항에 있어서, 상기 접합층은 상기 저융점 물질층과 다른 금속간 화합물을 형성하도록 열처리하여 형성하는 전자 소자 패키지 제조 방법.
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