TW200717772A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
TW200717772A
TW200717772A TW095125328A TW95125328A TW200717772A TW 200717772 A TW200717772 A TW 200717772A TW 095125328 A TW095125328 A TW 095125328A TW 95125328 A TW95125328 A TW 95125328A TW 200717772 A TW200717772 A TW 200717772A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
hole
insulating
insulating material
wire
Prior art date
Application number
TW095125328A
Other languages
English (en)
Inventor
Tomonaga Kobayashi
Yuzo Takita
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW200717772A publication Critical patent/TW200717772A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76Apparatus for connecting with build-up interconnects
    • H01L2224/7615Means for depositing
    • H01L2224/76151Means for direct writing
    • H01L2224/76155Jetting means, e.g. ink jet
    • HELECTRICITY
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821Forming a build-up interconnect
    • H01L2224/82101Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/01005Boron [B]
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    • H01L2924/01006Carbon [C]
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01018Argon [Ar]
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    • H01L2924/01023Vanadium [V]
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    • H01L2924/01074Tungsten [W]
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    • H01ELECTRIC ELEMENTS
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/01079Gold [Au]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
TW095125328A 2005-07-13 2006-07-11 Semiconductor device TW200717772A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005204231 2005-07-13
JP2006065482A JP2007049115A (ja) 2005-07-13 2006-03-10 半導体装置

Publications (1)

Publication Number Publication Date
TW200717772A true TW200717772A (en) 2007-05-01

Family

ID=37660942

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125328A TW200717772A (en) 2005-07-13 2006-07-11 Semiconductor device

Country Status (5)

Country Link
US (1) US7573119B2 (zh)
JP (1) JP2007049115A (zh)
KR (2) KR100847488B1 (zh)
CN (1) CN100583435C (zh)
TW (1) TW200717772A (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8749054B2 (en) * 2010-06-24 2014-06-10 L. Pierre de Rochemont Semiconductor carrier with vertical power FET module
JP4544181B2 (ja) * 2006-03-03 2010-09-15 セイコーエプソン株式会社 電子基板、半導体装置および電子機器
KR100753415B1 (ko) * 2006-03-17 2007-08-30 주식회사 하이닉스반도체 스택 패키지
KR100854927B1 (ko) * 2006-08-29 2008-08-27 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
JP2008210933A (ja) * 2007-02-26 2008-09-11 Casio Comput Co Ltd 半導体装置
JP4305678B2 (ja) * 2007-05-11 2009-07-29 セイコーエプソン株式会社 半導体装置
US8212155B1 (en) * 2007-06-26 2012-07-03 Wright Peter V Integrated passive device
JP4950012B2 (ja) * 2007-11-29 2012-06-13 力成科技股▲分▼有限公司 シリコンスルーホールを有する半導体チップ装置及びその製造方法
JP5592053B2 (ja) * 2007-12-27 2014-09-17 新光電気工業株式会社 半導体装置及びその製造方法
JP2009277879A (ja) * 2008-05-14 2009-11-26 Fujikura Ltd 半導体装置
JP5543084B2 (ja) * 2008-06-24 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置の製造方法
JP2010040782A (ja) * 2008-08-05 2010-02-18 Toshiba Corp 半導体装置及びその製造方法
KR101009103B1 (ko) * 2008-10-27 2011-01-18 삼성전기주식회사 양면 전극 패키지 및 그 제조방법
US8680843B2 (en) * 2010-06-10 2014-03-25 Infineon Technologies Ag Magnetic field current sensors
US8716859B2 (en) * 2012-01-10 2014-05-06 Intel Mobile Communications GmbH Enhanced flip chip package
JP5956944B2 (ja) * 2013-02-28 2016-07-27 日本電産サンキョー株式会社 非接触式情報処理装置
US10251280B2 (en) 2013-12-31 2019-04-02 Texas Instruments Incorporated Integrated circuit with micro inductor and micro transformer with magnetic core
JP2016174101A (ja) 2015-03-17 2016-09-29 株式会社東芝 半導体装置およびその製造方法
US10130302B2 (en) * 2016-06-29 2018-11-20 International Business Machines Corporation Via and trench filling using injection molded soldering
KR102213561B1 (ko) 2019-05-09 2021-02-08 베렉스주식회사 반도체 장치

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JPH03227046A (ja) * 1990-01-31 1991-10-08 Mitsubishi Electric Corp 高周波集積回路
JPH0786507A (ja) * 1993-09-20 1995-03-31 Fujitsu Ltd 半導体装置及びその製造方法
US5508234A (en) * 1994-10-31 1996-04-16 International Business Machines Corporation Microcavity structures, fabrication processes, and applications thereof
JPH08147351A (ja) 1994-11-25 1996-06-07 Misawa Homes Co Ltd 建物用cadシステムの設計情報処理方法
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JP3509362B2 (ja) 1996-01-26 2004-03-22 シャープ株式会社 半導体装置及びその製造方法
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JP2001185685A (ja) * 1999-12-24 2001-07-06 Toshiba Corp 半導体装置
JP4969715B2 (ja) * 2000-06-06 2012-07-04 ルネサスエレクトロニクス株式会社 半導体装置
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JP2005093867A (ja) * 2003-09-19 2005-04-07 Seiko Epson Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US7573119B2 (en) 2009-08-11
KR20070008397A (ko) 2007-01-17
CN100583435C (zh) 2010-01-20
KR20080036568A (ko) 2008-04-28
KR100847488B1 (ko) 2008-07-22
JP2007049115A (ja) 2007-02-22
US20070013062A1 (en) 2007-01-18
CN1897274A (zh) 2007-01-17
KR100890974B1 (ko) 2009-03-27

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