TW200623235A - A method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions - Google Patents
A method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensionsInfo
- Publication number
- TW200623235A TW200623235A TW094141232A TW94141232A TW200623235A TW 200623235 A TW200623235 A TW 200623235A TW 094141232 A TW094141232 A TW 094141232A TW 94141232 A TW94141232 A TW 94141232A TW 200623235 A TW200623235 A TW 200623235A
- Authority
- TW
- Taiwan
- Prior art keywords
- specific dimensions
- forming
- gate electrode
- polysilicon gate
- sidewall spacers
- Prior art date
Links
- 125000006850 spacer group Chemical group 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 229920005591 polysilicon Polymers 0.000 abstract 3
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/002,586 US7279386B2 (en) | 2004-12-03 | 2004-12-03 | Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200623235A true TW200623235A (en) | 2006-07-01 |
TWI397107B TWI397107B (zh) | 2013-05-21 |
Family
ID=36218711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094141232A TWI397107B (zh) | 2004-12-03 | 2005-11-24 | 形成具有特定尺寸之閘極側壁間隔件之半導體配置之方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7279386B2 (zh) |
EP (1) | EP1829092B1 (zh) |
JP (1) | JP2008522441A (zh) |
KR (1) | KR101142992B1 (zh) |
CN (1) | CN100459052C (zh) |
DE (1) | DE602005011483D1 (zh) |
TW (1) | TWI397107B (zh) |
WO (1) | WO2006060528A2 (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7279386B2 (en) * | 2004-12-03 | 2007-10-09 | Advanced Micro Devices, Inc. | Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions |
US7585735B2 (en) * | 2005-02-01 | 2009-09-08 | Freescale Semiconductor, Inc. | Asymmetric spacers and asymmetric source/drain extension layers |
US20110049582A1 (en) * | 2009-09-03 | 2011-03-03 | International Business Machines Corporation | Asymmetric source and drain stressor regions |
CN103928315B (zh) * | 2014-04-28 | 2017-06-23 | 上海华力微电子有限公司 | 一种栅极侧墙减薄工艺 |
CN103943462A (zh) * | 2014-04-28 | 2014-07-23 | 上海华力微电子有限公司 | 针对薄膜沉积产生负载效应的消除方法 |
US9941388B2 (en) | 2014-06-19 | 2018-04-10 | Globalfoundries Inc. | Method and structure for protecting gates during epitaxial growth |
US10566194B2 (en) * | 2018-05-07 | 2020-02-18 | Lam Research Corporation | Selective deposition of etch-stop layer for enhanced patterning |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4033026A (en) | 1975-12-16 | 1977-07-05 | Intel Corporation | High density/high speed MOS process and device |
JP2685149B2 (ja) * | 1988-04-11 | 1997-12-03 | 住友電気工業株式会社 | 電界効果トランジスタの製造方法 |
JPH08335554A (ja) * | 1995-06-07 | 1996-12-17 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
US5656518A (en) * | 1996-09-13 | 1997-08-12 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
JP3530692B2 (ja) * | 1996-11-06 | 2004-05-24 | キヤノン株式会社 | 走査型露光装置及びそれを用いたデバイスの製造方法 |
JP3598693B2 (ja) * | 1996-12-03 | 2004-12-08 | ソニー株式会社 | 半導体装置およびその製造方法 |
JPH10242460A (ja) * | 1997-02-25 | 1998-09-11 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US5930634A (en) | 1997-04-21 | 1999-07-27 | Advanced Micro Devices, Inc. | Method of making an IGFET with a multilevel gate |
JP2000012844A (ja) * | 1998-06-19 | 2000-01-14 | Sony Corp | 高耐圧半導体装置及びその製造方法 |
KR100284905B1 (ko) * | 1998-10-16 | 2001-04-02 | 윤종용 | 반도체 장치의 콘택 형성 방법 |
JP2000260701A (ja) * | 1999-03-10 | 2000-09-22 | Toshiba Corp | パターン形成方法及びそれを用いた半導体装置の製造方法 |
JP3381147B2 (ja) * | 1999-04-16 | 2003-02-24 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6300208B1 (en) | 2000-02-16 | 2001-10-09 | Ultratech Stepper, Inc. | Methods for annealing an integrated device using a radiant energy absorber layer |
JP2001250756A (ja) * | 2000-03-03 | 2001-09-14 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP4776813B2 (ja) * | 2001-06-12 | 2011-09-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
TW540102B (en) * | 2001-12-31 | 2003-07-01 | Silicon Integrated Sys Corp | Formation method of oxide film |
JP3725841B2 (ja) * | 2002-06-27 | 2005-12-14 | 株式会社東芝 | 電子ビーム露光の近接効果補正方法、露光方法、半導体装置の製造方法及び近接効果補正モジュール |
JP2004165218A (ja) * | 2002-11-08 | 2004-06-10 | Canon Inc | 露光装置 |
TWI222227B (en) * | 2003-05-15 | 2004-10-11 | Au Optronics Corp | Method for forming LDD of semiconductor devices |
JP2005012038A (ja) * | 2003-06-20 | 2005-01-13 | Renesas Technology Corp | 半導体装置の製造方法 |
US6893967B1 (en) | 2004-01-13 | 2005-05-17 | Advanced Micro Devices, Inc. | L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials |
US7279386B2 (en) | 2004-12-03 | 2007-10-09 | Advanced Micro Devices, Inc. | Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions |
-
2004
- 2004-12-03 US US11/002,586 patent/US7279386B2/en not_active Expired - Fee Related
-
2005
- 2005-11-24 TW TW094141232A patent/TWI397107B/zh not_active IP Right Cessation
- 2005-11-29 KR KR1020077012157A patent/KR101142992B1/ko not_active IP Right Cessation
- 2005-11-29 EP EP05852586A patent/EP1829092B1/en not_active Expired - Fee Related
- 2005-11-29 WO PCT/US2005/043397 patent/WO2006060528A2/en active Application Filing
- 2005-11-29 CN CNB2005800392172A patent/CN100459052C/zh not_active Expired - Fee Related
- 2005-11-29 JP JP2007544490A patent/JP2008522441A/ja active Pending
- 2005-11-29 DE DE602005011483T patent/DE602005011483D1/de active Active
Also Published As
Publication number | Publication date |
---|---|
US7279386B2 (en) | 2007-10-09 |
JP2008522441A (ja) | 2008-06-26 |
CN101073143A (zh) | 2007-11-14 |
TWI397107B (zh) | 2013-05-21 |
EP1829092B1 (en) | 2008-12-03 |
KR20070085551A (ko) | 2007-08-27 |
DE602005011483D1 (de) | 2009-01-15 |
KR101142992B1 (ko) | 2012-05-15 |
WO2006060528A3 (en) | 2006-10-26 |
WO2006060528A2 (en) | 2006-06-08 |
CN100459052C (zh) | 2009-02-04 |
US20060121711A1 (en) | 2006-06-08 |
EP1829092A2 (en) | 2007-09-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |