WO2003015182A3 - Steg-feldeffekttransistor und verfahren zum herstellen eines steg-feldeffekttransistors - Google Patents

Steg-feldeffekttransistor und verfahren zum herstellen eines steg-feldeffekttransistors Download PDF

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Publication number
WO2003015182A3
WO2003015182A3 PCT/DE2002/002760 DE0202760W WO03015182A3 WO 2003015182 A3 WO2003015182 A3 WO 2003015182A3 DE 0202760 W DE0202760 W DE 0202760W WO 03015182 A3 WO03015182 A3 WO 03015182A3
Authority
WO
WIPO (PCT)
Prior art keywords
field effect
effect transistor
fin field
producing
substrate
Prior art date
Application number
PCT/DE2002/002760
Other languages
English (en)
French (fr)
Other versions
WO2003015182A2 (de
Inventor
Franz Hofmann
Johannes Kretz
Wolfgang Roesner
Thomas Schulz
Original Assignee
Infineon Technologies Ag
Franz Hofmann
Johannes Kretz
Wolfgang Roesner
Thomas Schulz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Franz Hofmann, Johannes Kretz, Wolfgang Roesner, Thomas Schulz filed Critical Infineon Technologies Ag
Priority to EP02794490A priority Critical patent/EP1412986A2/de
Publication of WO2003015182A2 publication Critical patent/WO2003015182A2/de
Publication of WO2003015182A3 publication Critical patent/WO2003015182A3/de
Priority to US10/768,971 priority patent/US7265424B2/en
Priority to US11/833,080 priority patent/US20080035997A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Der Steg-Feldeffekttransistor weist ein Substrat, einen Steg über dem Substrat, sowie einen Drain-Bereich und einen Source-Bereich ausserhalb des Steges über dem Substrat auf. Der Steg dient als Kanal zwischen Source-Bereich und Drain-Bereich. Source- und Drain-Bereich werden erst nach dem Erzeugen des Gates gebildet.
PCT/DE2002/002760 2001-07-30 2002-07-26 Steg-feldeffekttransistor und verfahren zum herstellen eines steg-feldeffekttransistors WO2003015182A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP02794490A EP1412986A2 (de) 2001-07-30 2002-07-26 Steg-feldeffekttransistor und verfahren zur herstellung eines steg-feldeffekttransistors
US10/768,971 US7265424B2 (en) 2001-07-30 2004-01-30 Fin Field-effect transistor and method for producing a fin field effect-transistor
US11/833,080 US20080035997A1 (en) 2001-07-30 2007-08-02 Fin Field-Effect Transistor and Method for Fabricating a Fin Field-Effect Transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10137217A DE10137217A1 (de) 2001-07-30 2001-07-30 Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
DE10137217.5 2001-07-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/768,971 Continuation US7265424B2 (en) 2001-07-30 2004-01-30 Fin Field-effect transistor and method for producing a fin field effect-transistor

Publications (2)

Publication Number Publication Date
WO2003015182A2 WO2003015182A2 (de) 2003-02-20
WO2003015182A3 true WO2003015182A3 (de) 2003-08-07

Family

ID=7693676

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/002760 WO2003015182A2 (de) 2001-07-30 2002-07-26 Steg-feldeffekttransistor und verfahren zum herstellen eines steg-feldeffekttransistors

Country Status (5)

Country Link
US (2) US7265424B2 (de)
EP (1) EP1412986A2 (de)
DE (1) DE10137217A1 (de)
TW (1) TW554537B (de)
WO (1) WO2003015182A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10137217A1 (de) * 2001-07-30 2003-02-27 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US6864164B1 (en) 2002-12-17 2005-03-08 Advanced Micro Devices, Inc. Finfet gate formation using reverse trim of dummy gate
US6855582B1 (en) 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US7041542B2 (en) 2004-01-12 2006-05-09 Advanced Micro Devices, Inc. Damascene tri-gate FinFET
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
TWI277210B (en) * 2004-10-26 2007-03-21 Nanya Technology Corp FinFET transistor process
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
KR100649874B1 (ko) * 2005-12-29 2006-11-27 동부일렉트로닉스 주식회사 에스오아이 웨이퍼를 이용한 트랜지스터 제조 방법
TWI283482B (en) * 2006-06-05 2007-07-01 Promos Technologies Inc Multi-fin field effect transistor and fabricating method thereof
US7646046B2 (en) * 2006-11-14 2010-01-12 Infineon Technologies Ag Field effect transistor with a fin structure
US7838948B2 (en) * 2007-01-30 2010-11-23 Infineon Technologies Ag Fin interconnects for multigate FET circuit blocks
US8682116B2 (en) * 2007-08-08 2014-03-25 Infineon Technologies Ag Integrated circuit including non-planar structure and waveguide
DE102008059500B4 (de) * 2008-11-28 2010-08-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Mehr-Gatetransistors mit homogen silizidierten Stegendbereichen
US20110001169A1 (en) * 2009-07-01 2011-01-06 International Business Machines Corporation Forming uniform silicide on 3d structures
JP2011066362A (ja) * 2009-09-18 2011-03-31 Toshiba Corp 半導体装置
US8232627B2 (en) * 2009-09-21 2012-07-31 International Business Machines Corporation Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device
US9634000B2 (en) 2013-03-14 2017-04-25 International Business Machines Corporation Partially isolated fin-shaped field effect transistors
US9219114B2 (en) * 2013-07-12 2015-12-22 Globalfoundries Inc. Partial FIN on oxide for improved electrical isolation of raised active regions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996574A (en) * 1988-07-01 1991-02-26 Fujitsu Limited MIS transistor structure for increasing conductance between source and drain regions
US5623155A (en) * 1994-11-24 1997-04-22 Seimens Aktiengesellschaft MOSFET on SOI substrate
US5915183A (en) * 1998-06-26 1999-06-22 International Business Machines Corporation Raised source/drain using recess etch of polysilicon
US6091076A (en) * 1996-06-14 2000-07-18 Commissariat A L'energie Atomique Quantum WELL MOS transistor and methods for making same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2670605B1 (fr) * 1990-12-13 1993-04-09 France Etat Procede de realisation d'une barriere de diffusion electriquement conductrice a l'interface metal/silicium d'un transistor mos et transistor correspondant.
US6118161A (en) * 1997-04-30 2000-09-12 Texas Instruments Incorporated Self-aligned trenched-channel lateral-current-flow transistor
US6274913B1 (en) * 1998-10-05 2001-08-14 Intel Corporation Shielded channel transistor structure with embedded source/drain junctions
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6303479B1 (en) * 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
DE10137217A1 (de) * 2001-07-30 2003-02-27 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996574A (en) * 1988-07-01 1991-02-26 Fujitsu Limited MIS transistor structure for increasing conductance between source and drain regions
US5623155A (en) * 1994-11-24 1997-04-22 Seimens Aktiengesellschaft MOSFET on SOI substrate
US6091076A (en) * 1996-06-14 2000-07-18 Commissariat A L'energie Atomique Quantum WELL MOS transistor and methods for making same
US5915183A (en) * 1998-06-26 1999-06-22 International Business Machines Corporation Raised source/drain using recess etch of polysilicon

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FUJIWARA A ET AL: "SUPPRESSION OF UNINTENTIONAL FORMATION OF PARASITIC SI ISLANDS ON ASI SINGLE-ELECTRON TRANSISTOR BY THE USE OF SIN MASKED OXIDATION", EXTENDED ABSTRACTS OF THE INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, JAPAN SOCIETY OF APPLIED PHYSICS. TOKYO, JA, 1 September 1997 (1997-09-01), pages 482 - 483, XP000728204 *
ISHII T ET AL: "CHARACTERIZATION OF ONE-DIMENSIONAL CONDUCTION IN AN ULTRA-THIN POLY-SI WIRE", EXTENDED ABSTRACTS OF THE INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, JAPAN SOCIETY OF APPLIED PHYSICS. TOKYO, JA, 21 August 1995 (1995-08-21), pages 201 - 203, XP000544601 *

Also Published As

Publication number Publication date
US7265424B2 (en) 2007-09-04
US20080035997A1 (en) 2008-02-14
WO2003015182A2 (de) 2003-02-20
TW554537B (en) 2003-09-21
US20040217408A1 (en) 2004-11-04
DE10137217A1 (de) 2003-02-27
EP1412986A2 (de) 2004-04-28

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