WO2000021118A3 - Verfahren zur herstellung eines vertikalen mosfets - Google Patents

Verfahren zur herstellung eines vertikalen mosfets Download PDF

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Publication number
WO2000021118A3
WO2000021118A3 PCT/DE1999/003208 DE9903208W WO0021118A3 WO 2000021118 A3 WO2000021118 A3 WO 2000021118A3 DE 9903208 W DE9903208 W DE 9903208W WO 0021118 A3 WO0021118 A3 WO 0021118A3
Authority
WO
WIPO (PCT)
Prior art keywords
producing
double gate
vertical mosfet
structuring
sub
Prior art date
Application number
PCT/DE1999/003208
Other languages
English (en)
French (fr)
Other versions
WO2000021118A2 (de
Inventor
Michel Marso
Juergen Moers
Dirk Klaes
Peter Kordos
Hans Lueth
Original Assignee
Forschungszentrum Juelich Gmbh
Michel Marso
Juergen Moers
Dirk Klaes
Peter Kordos
Hans Lueth
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich Gmbh, Michel Marso, Juergen Moers, Dirk Klaes, Peter Kordos, Hans Lueth filed Critical Forschungszentrum Juelich Gmbh
Publication of WO2000021118A2 publication Critical patent/WO2000021118A2/de
Publication of WO2000021118A3 publication Critical patent/WO2000021118A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung eines Bauelements mit sub-100 nm-Strukturierung. Dabei ist zu Anfang der geometrischen Ausbildung des Bauelements eine einzige sub-100 nm-Strukturierung vorgesehen. Als Bauelement kann ein MOSFET gewählt werden, dessen Gatter den Kanal umschließt.
PCT/DE1999/003208 1998-10-07 1999-10-05 Verfahren zur herstellung eines vertikalen mosfets WO2000021118A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1998146063 DE19846063A1 (de) 1998-10-07 1998-10-07 Verfahren zur Herstellung eines Double-Gate MOSFETs
DE19846063.5 1998-10-07

Publications (2)

Publication Number Publication Date
WO2000021118A2 WO2000021118A2 (de) 2000-04-13
WO2000021118A3 true WO2000021118A3 (de) 2001-01-11

Family

ID=7883611

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/003208 WO2000021118A2 (de) 1998-10-07 1999-10-05 Verfahren zur herstellung eines vertikalen mosfets

Country Status (2)

Country Link
DE (1) DE19846063A1 (de)
WO (1) WO2000021118A2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10030391C2 (de) * 2000-06-21 2003-10-02 Infineon Technologies Ag Verfahren zur Herstellung einer Anschlussfläche für vertikale sublithographische Halbleiterstrukturen
AT409489B (de) * 2000-10-20 2002-08-26 Agrolinz Melamin Gmbh Verfahren zur herstellung von melamin
US6455377B1 (en) * 2001-01-19 2002-09-24 Chartered Semiconductor Manufacturing Ltd. Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
US6798017B2 (en) * 2001-08-31 2004-09-28 International Business Machines Corporation Vertical dual gate field effect transistor
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
DE10250984A1 (de) 2002-10-29 2004-05-19 Hahn-Meitner-Institut Berlin Gmbh Feldeffekttransistor sowie Verfahren zu seiner Herstellung
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6967143B2 (en) 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
US7192876B2 (en) 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US6903967B2 (en) 2003-05-22 2005-06-07 Freescale Semiconductor, Inc. Memory with charge storage locations and adjacent gate structures
DE10333669A1 (de) * 2003-07-24 2005-03-03 Forschungszentrum Jülich GmbH Photodetektor und Verfahren zu seiner Herstellung
US6921700B2 (en) 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels
DE10350751B4 (de) 2003-10-30 2008-04-24 Infineon Technologies Ag Verfahren zum Herstellen eines vertikalen Feldeffekttransistors und Feldeffekt-Speichertransistor, insbesondere FLASH-Speichertransistor
US6831310B1 (en) 2003-11-10 2004-12-14 Freescale Semiconductor, Inc. Integrated circuit having multiple memory types and method of formation
US7098502B2 (en) 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation
US7018876B2 (en) 2004-06-18 2006-03-28 Freescale Semiconductor, Inc. Transistor with vertical dielectric structure
US7354831B2 (en) 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
WO2007054844A2 (en) * 2005-11-14 2007-05-18 Nxp B.V. Vertical insulated gate field-effect transistor and method of manufacturing the same
US7432122B2 (en) 2006-01-06 2008-10-07 Freescale Semiconductor, Inc. Electronic device and a process for forming the electronic device
US8476132B2 (en) 2008-01-29 2013-07-02 Unisantis Electronics Singapore Pte Ltd. Production method for semiconductor device
WO2009096002A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体装置の製造方法
US9005548B2 (en) 2009-02-25 2015-04-14 California Institute Of Technology Methods for fabricating high aspect ratio probes and deforming high aspect ratio nanopillars and micropillars
JP5763629B2 (ja) 2009-06-26 2015-08-12 カリフォルニア インスティチュート オブ テクノロジー パッシベートされたシリコンナノワイヤーの製造方法およびこれにより得られるデバイス
US8809093B2 (en) 2009-11-19 2014-08-19 California Institute Of Technology Methods for fabricating self-aligning semicondutor heterostructures using silicon nanowires
US9018684B2 (en) 2009-11-23 2015-04-28 California Institute Of Technology Chemical sensing and/or measuring devices and methods
DE102016220749B4 (de) * 2016-10-21 2019-07-11 Infineon Technologies Ag Verfahren zur Herstellung von Ätzstoppbereichen zum Kontaktieren von Halbleitervorrichtungen

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2103879A (en) * 1981-08-19 1983-02-23 Secr Defence <Method for producing a vertical channel transistor
GB2222306A (en) * 1988-08-23 1990-02-28 Plessey Co Plc Field effect transistor
DE4235152A1 (de) * 1992-10-19 1994-04-21 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung einer Halbleiterfeinstruktur und damit hergestellte Halbleiterbauelemente, beispielsweise Vertikaltransistoren
DE4238749A1 (de) * 1992-11-17 1994-05-19 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung einer Halbleiterfeinstruktur und damit hergestellte Halbleiterbauelemente
DE19621244A1 (de) * 1996-05-25 1996-11-14 Ignaz Prof Dr Eisele Vertikale Transistoren, bei denen das Gate durch Planarisierung und Rückätzen quasi selbstjustierend strukturiert wird
US5612255A (en) * 1993-12-21 1997-03-18 International Business Machines Corporation One dimensional silicon quantum wire devices and the method of manufacture thereof
DE19711482A1 (de) * 1997-03-19 1998-09-24 Siemens Ag Verfahren zur Herstellung eines vertikalen MOS-Transistors

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2103879A (en) * 1981-08-19 1983-02-23 Secr Defence <Method for producing a vertical channel transistor
GB2222306A (en) * 1988-08-23 1990-02-28 Plessey Co Plc Field effect transistor
DE4235152A1 (de) * 1992-10-19 1994-04-21 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung einer Halbleiterfeinstruktur und damit hergestellte Halbleiterbauelemente, beispielsweise Vertikaltransistoren
DE4238749A1 (de) * 1992-11-17 1994-05-19 Inst Halbleiterphysik Gmbh Verfahren zur Herstellung einer Halbleiterfeinstruktur und damit hergestellte Halbleiterbauelemente
US5612255A (en) * 1993-12-21 1997-03-18 International Business Machines Corporation One dimensional silicon quantum wire devices and the method of manufacture thereof
DE19621244A1 (de) * 1996-05-25 1996-11-14 Ignaz Prof Dr Eisele Vertikale Transistoren, bei denen das Gate durch Planarisierung und Rückätzen quasi selbstjustierend strukturiert wird
DE19711482A1 (de) * 1997-03-19 1998-09-24 Siemens Ag Verfahren zur Herstellung eines vertikalen MOS-Transistors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AEUGLE TH ET AL: "ADVANCED SELF ALIGNED SOI CONCEPTS FOR VERTICAL MOS TRANSISTORS WITH ULTRASHORT CHANNEL LENGHTS", PROCEEDINGS OF THE EUROPEAN SOLID STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 22 September 1997 (1997-09-22), XP000764862 *
BEHAMMER D ET AL: "Comparison of lateral and vertical Si-MOSFETs with ultra short channels", 1998 E-MRS SPRING CONFERENCE, SYMPOSIUM D: THIN FILMS EPITAXIAL GROWTH AND NANOSTRUCTURES, STRASBOURG, FRANCE, 16-19 JUNE 1998, vol. 336, no. 1-2, Thin Solid Films, 30 Dec. 1998, Elsevier, Switzerland, pages 313 - 318, XP004154112, ISSN: 0040-6090 *

Also Published As

Publication number Publication date
DE19846063A1 (de) 2000-04-20
WO2000021118A2 (de) 2000-04-13

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