TW200606939A - Adaptive algorithm for MRAM manufacturing - Google Patents

Adaptive algorithm for MRAM manufacturing

Info

Publication number
TW200606939A
TW200606939A TW094123589A TW94123589A TW200606939A TW 200606939 A TW200606939 A TW 200606939A TW 094123589 A TW094123589 A TW 094123589A TW 94123589 A TW94123589 A TW 94123589A TW 200606939 A TW200606939 A TW 200606939A
Authority
TW
Taiwan
Prior art keywords
mram
eeprom
random access
otp
eprom
Prior art date
Application number
TW094123589A
Other languages
English (en)
Other versions
TWI300562B (en
Inventor
Hsu Kai Yang
Xi Zeng Shi
Po Kang Wang
Bruce Yang
Original Assignee
Headway Technologies Inc
Applied Spintronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Headway Technologies Inc, Applied Spintronics Inc filed Critical Headway Technologies Inc
Publication of TW200606939A publication Critical patent/TW200606939A/zh
Application granted granted Critical
Publication of TWI300562B publication Critical patent/TWI300562B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
TW094123589A 2004-07-13 2005-07-12 Adaptive algorithm for mram manufacturing TWI300562B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/889,911 US7085183B2 (en) 2004-07-13 2004-07-13 Adaptive algorithm for MRAM manufacturing

Publications (2)

Publication Number Publication Date
TW200606939A true TW200606939A (en) 2006-02-16
TWI300562B TWI300562B (en) 2008-09-01

Family

ID=35431905

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094123589A TWI300562B (en) 2004-07-13 2005-07-12 Adaptive algorithm for mram manufacturing

Country Status (5)

Country Link
US (4) US7085183B2 (zh)
EP (1) EP1624458B1 (zh)
JP (3) JP4732817B2 (zh)
KR (3) KR101143337B1 (zh)
TW (1) TWI300562B (zh)

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WO2007040189A1 (ja) 2005-10-03 2007-04-12 Nec Corporation 磁気ランダムアクセスメモリ及びその動作方法
US7345912B2 (en) * 2006-06-01 2008-03-18 Grandis, Inc. Method and system for providing a magnetic memory structure utilizing spin transfer
JP2008047214A (ja) * 2006-08-15 2008-02-28 Nec Corp 半導体記憶装置及びそのテスト方法
US7505348B2 (en) * 2006-10-06 2009-03-17 International Business Machines Corporation Balanced and bi-directional bit line paths for memory arrays with programmable memory cells
JP2010033620A (ja) * 2006-10-30 2010-02-12 Renesas Technology Corp 磁性体メモリ
CN100576356C (zh) * 2006-12-21 2009-12-30 中芯国际集成电路制造(上海)有限公司 减小存储单元写入扰乱的方法
KR100850283B1 (ko) * 2007-01-25 2008-08-04 삼성전자주식회사 3차원 적층구조를 가지는 저항성 반도체 메모리 장치 및그의 워드라인 디코딩 방법
US20080198674A1 (en) * 2007-02-21 2008-08-21 Jan Keller Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit
US7890892B2 (en) * 2007-11-15 2011-02-15 International Business Machines Corporation Balanced and bi-directional bit line paths for memory arrays with programmable memory cells
US7808819B2 (en) * 2008-04-29 2010-10-05 Sandisk Il Ltd. Method for adaptive setting of state voltage levels in non-volatile memory
US7808836B2 (en) * 2008-04-29 2010-10-05 Sandisk Il Ltd. Non-volatile memory with adaptive setting of state voltage levels
US7821839B2 (en) * 2008-06-27 2010-10-26 Sandisk Il Ltd. Gain control for read operations in flash memory
US8218349B2 (en) * 2009-05-26 2012-07-10 Crocus Technology Sa Non-volatile logic devices using magnetic tunnel junctions
US8547736B2 (en) * 2010-08-03 2013-10-01 Qualcomm Incorporated Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction
KR101884203B1 (ko) * 2011-06-27 2018-08-02 삼성전자주식회사 자기 메모리 소자 및 자기 메모리 소자의 데이터 기록 방법
US8659954B1 (en) * 2011-09-14 2014-02-25 Adesto Technologies Corporation CBRAM/ReRAM with improved program and erase algorithms
US9431083B2 (en) 2014-03-25 2016-08-30 Samsung Electronics Co., Ltd. Nonvolatile memory device and storage device having the same
US9813049B2 (en) * 2015-08-12 2017-11-07 Qualcomm Incorporated Comparator including a magnetic tunnel junction (MTJ) device and a transistor
US9793003B2 (en) 2015-09-15 2017-10-17 Avalanche Technology, Inc. Programming of non-volatile memory subjected to high temperature exposure
US9997564B2 (en) 2015-10-09 2018-06-12 Western Digital Technologies, Inc. MTJ memory array subgrouping method and related drive circuitry
US9899082B2 (en) 2016-03-03 2018-02-20 Toshiba Memory Corporation Semiconductor memory device
KR102388615B1 (ko) * 2017-11-13 2022-04-21 에스케이하이닉스 주식회사 메모리 시스템
US10872662B2 (en) 2019-02-19 2020-12-22 Samsung Electronics Co., Ltd 2T2R binary weight cell with high on/off ratio background
CN112309481B (zh) * 2019-08-02 2024-07-16 神讯电脑(昆山)有限公司 Eeprom读写检测系统及其方法

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JP3866701B2 (ja) * 2003-08-25 2007-01-10 株式会社東芝 磁気ランダムアクセスメモリ及びそのテスト方法
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JP2005349800A (ja) * 2004-06-14 2005-12-22 Bando Chem Ind Ltd 印刷用ブランケット及びその製造方法

Also Published As

Publication number Publication date
KR101143337B1 (ko) 2012-05-09
KR20060050140A (ko) 2006-05-19
KR101204659B1 (ko) 2012-11-27
JP5178787B2 (ja) 2013-04-10
KR20120016605A (ko) 2012-02-24
KR101365478B1 (ko) 2014-02-21
US20060250865A1 (en) 2006-11-09
US7085183B2 (en) 2006-08-01
JP4732817B2 (ja) 2011-07-27
US7224628B2 (en) 2007-05-29
TWI300562B (en) 2008-09-01
US20060013038A1 (en) 2006-01-19
US7321519B2 (en) 2008-01-22
JP5178788B2 (ja) 2013-04-10
EP1624458B1 (en) 2013-04-24
JP2006031923A (ja) 2006-02-02
EP1624458A1 (en) 2006-02-08
US20060250867A1 (en) 2006-11-09
US20060250866A1 (en) 2006-11-09
JP2010282719A (ja) 2010-12-16
KR20120016604A (ko) 2012-02-24
US7369430B2 (en) 2008-05-06
JP2010238362A (ja) 2010-10-21

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