TWI300562B - Adaptive algorithm for mram manufacturing - Google Patents

Adaptive algorithm for mram manufacturing Download PDF

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Publication number
TWI300562B
TWI300562B TW094123589A TW94123589A TWI300562B TW I300562 B TWI300562 B TW I300562B TW 094123589 A TW094123589 A TW 094123589A TW 94123589 A TW94123589 A TW 94123589A TW I300562 B TWI300562 B TW I300562B
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Taiwan
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current
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column
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TW094123589A
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TW200606939A (en
Inventor
Kai Yang Hsu
Shi Xi-Zeng
Wang Po-Kang
yang Bruce
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Headway Technologies Inc
Applied Spintronics Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)

Description

1300562 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種磁性隨機存取記憶體，特別是關於利用磁性隨 機存取記憶體的特性去適應每個獨立記憶胞的列與行編程電流，而使 磁性隨機存取記憶體可以當作靜態隨機存取記憶體、一次編程隨機存 取記憶體（one-time-programmableRAM)、和電子式可變或快閃隨機存 取記憶體（electrically alterable or flash RAM)使用，進而使磁性隨機存 取記憶體的總產量達到最大化的演算法。 【先前技術】 n 一典型包含一個獨立電晶體之磁性隨機存取記憶胞如第一圖所 示，一位元線110、位元線110之電流120及其所形成的磁場13〇如第 一圖所示。另外，一字元線140、字元線140之電流170及其所形成之 磁場160如第一圖所示。組成記憶胞的三層如第一圖所示，自由層（free layer) 180與固定層（pinned layer) 195這兩層為磁性材料，分別設置 於絕緣層（insulationlayer)之上下兩側，絕緣層可為氧化物19〇。一獨 立之電晶體亦如第一圖所示，而磁性穿遂接面（Magnetic Tunnel 隹 Junction，MTJ)所表現出磁滯現象的特性如第二圖。記憶胞之兩個明 顯狀態係基於其阻抗率，無論自由層與固定層的磁場是平行或反平行 (anti-parallel) ’當磁場為反平行時，阻抗的增加比例最高可達5〇%。 記憶胞需要兩個電流元件的交會點以將兩種不同的狀態寫入記憶胞 中。在第二圖中，字元線的電流相當於列電流（IR)而位元線的電流 相當於行電流（1C)。第二圖展示了單一磁性穿遂接面之兩個磁滯迴 圈，當字元線的電流為〇毫安培，位元線的電流必須為±75毫安培以 1300562 切換自由層的磁場方向，而當字元線的電流為4毫安培時，切換自由 層磁場方向所需的位元線紐在±25毫安培左右，磁性料接面的阻 抗由7.6千歐姆増加了 38%，變為ι〇·5千歐姆。第二圖也顯示了磁滞 見象的t微不對稱，將磁性穿遂接面由低阻抗轉成高阻抗需要比反向 的操作更多的位元線電流。改變單—磁性穿遂接面自由層磁場方向所 的最低子元線電與位元線電流如第三圖所示，任何在星狀區域 31〇内的偏壓點（bias p()int)(字元線/列電流IR與位元線/行電流ic之 組合）都不會改變自由層的磁場方向。任何在星狀區域3ig外的偏壓 點都會改變磁場方向，或是無意地對共賴—條字元線錄元線之磁 性穿遂接面造賴動。當—個記麵_係由大量_性穿遂接面組 成時每個磁性穿遂接面的特性可能會因為隨機程序的變化而有明顯 的文化。第二圖的星狀輪廓將會是陣列巾所有磁性穿遂接面的混合 物。要找出-個固定的偏迦（IRmc)使所有的磁性穿遂接面可以 在兩個方向上切換，且不干擾同一列或同一行上之磁性穿遂接面，是 一件困難的工作。 組成記憶齡_雖_存取記㈣（囊⑷記憶胞被排列 成列與行，透過職频行電絲進行編程，其中铜錢與行電流 交叉點上的記憶胞會被編程；分享同—列和同—行的記憶胞會發現到 其各自之舰錢行電流，這些電流射之—Μ無意地對記憶胞編 程或是干擾。由於製作過程科_，因此欲對目標元件進行編程且 不干擾同歹或同仃上的凡件，其所需要的電流標準在整個記憶體 1300562 不θ相同’非常大的時候，關題賴變得更加嚴重。 將陣列切割祕域字元線’如第四騎示，只有在記憶胞與將被 編程的位元組制相同位元_，可能發生干擾狀況，而透過調整每1300562 IX. Description of the Invention: [Technical Field] The present invention relates to a magnetic random access memory, and more particularly to utilizing the characteristics of a magnetic random access memory to adapt the column and row programming current of each individual memory cell The magnetic random access memory can be used as a static random access memory, a one-time-programmable RAM, and an electronically variable or flash random access memory (electrically alterable memory). Or flash RAM) algorithm that is used to maximize the total output of the magnetic random access memory. [Prior Art] n A magnetic random access memory cell typically including an independent transistor, as shown in the first figure, a bit line 110, a current 120 of the bit line 110, and a magnetic field 13 formed by it, such as the first The figure shows. In addition, the current 170 of the word line 140, the word line 140, and the magnetic field 160 formed therein are as shown in the first figure. The three layers constituting the memory cell are as shown in the first figure. The free layer 180 and the pinned layer 195 are magnetic materials respectively disposed on the upper and lower sides of the insulating layer, and the insulating layer. It can be an oxide of 19 〇. A separate transistor is also shown in the first figure, and the characteristics of the hysteresis phenomenon exhibited by the Magnetic Tunnel 隹 Junction (MTJ) are shown in the second figure. The two apparent states of the memory cell are based on their impedance ratio, whether the magnetic field of the free layer and the fixed layer is parallel or anti-parallel. When the magnetic field is anti-parallel, the impedance increases by up to 5〇%. The memory cell requires the intersection of two current elements to write two different states into the memory cell. In the second figure, the current of the word line corresponds to the column current (IR) and the current of the bit line corresponds to the line current (1C). The second figure shows the two hysteresis loops of a single magnetic through-junction. When the current of the word line is 〇 milliamperes, the current of the bit line must be ±75 milliamps to 1300562 to switch the magnetic field direction of the free layer. When the current of the word line is 4 mA, the bit line required to switch the direction of the free layer magnetic field is about ±25 mA, and the impedance of the magnetic material junction is increased by 38% from 7.6 k ohms to ι. 〇·5 thousand ohms. The second figure also shows the t-micro-symmetry of the hysteresis image. Converting the magnetic through-junction from low impedance to high impedance requires more bit line current than the reverse operation. Change the minimum sub-line power and bit line current of the magnetic field in the direction of the free-layer magnetic field. As shown in the third figure, any bias point (bias p() int) in the star-shaped region 31〇 (The combination of the word line/column current IR and the bit line/row current ic) does not change the direction of the magnetic field of the free layer. Any bias point outside the 3ig of the star-shaped region will change the direction of the magnetic field, or unintentionally oscillate the magnetic cross-section of the shared line of the word line. When a face _ is composed of a large number of _ straits, the characteristics of each magnetic piercing interface may be clearly cultured due to changes in random procedures. The star-shaped profile of the second image will be a mixture of all magnetic piercing faces of the array towel. It is difficult to find a fixed bias (IRmc) so that all magnetic piercing joints can be switched in both directions without interfering with the magnetic piercing joints in the same column or on the same row. . Composition memory age _ Although _ access record (four) (sac (4) memory cells are arranged in columns and rows, programmed through the frequency line, in which the memory cells at the intersection of copper and current will be programmed; share the same - Columns and the same-line memory cells will find their own ship money currents, which are unintentionally programmed or interfered with the memory cells. Because of the production process, it is necessary to program the target components and not Interfering with the same thing on the same or the same, the current standard required is not the same when the whole memory 1300562 is not the same ‘very large, the problem becomes more serious. The array cuts the secret word line as the first Four rides show that only in the memory cell and the same bit that will be programmed _, the interference situation may occur, and by adjusting each

'的、扁㈣w ’可使編程每—個記憶叙不干擾記憶體陣列中 其他記憶胞的機率大幅提升。第四圖顯示出第則個區段與第N', flat (four) w ' can greatly increase the probability that each memory will not interfere with other memory cells in the memory array. The fourth picture shows the first segment and the Nth

品奴8〇 N由1開始遞增，第則個區段中之記憶胞與分段字 το線選擇電晶體491 一同顯示於圖中，分段字元線選擇電晶體例上 有-返回線接附在-全域字元線回報（Globalwordlin㈣㈣彻上， 沿者全域字70線42G的分段字元線選擇電晶體係用以包入或排除受到 記憶胞編程影響的-個區段、—條元組或—組位元組。如第四圖中 全域字元線420與區域字元線49〇皆為第一圖中所提及的列，而第四 圖中之位元線460則是第一圖中所提及的行。 第六圖所不為一以磁性穿遂接面實現之非揮發性閂（n〇n %iatiie latch)，而第五圖所顯示者為一能透過此非揮發性閂來編程進而調整電 流層級之可調適電流源，此二圖顯示了一種改變編程電流的方法，任 何熟悉此技術的人能以許多不同之方法實作可調適電流源。第五圖中 使用閂單元510，其係詳述於第六圖中，三個電流源52〇透過電晶體 530的選擇性活化而被選擇性地結合在一起；一組合電流可產生可調適 電流，此組合電流即為總電流ItQtal 550 ; — Vdd電源供應器540係用以 供應電力給電流源II、12與13。 第六圖中之非揮發性閃疋利用兩p通道金氧半場效電晶體（PM〇s 1300562 FET) 610、630、兩η通道金氧半場效電晶體（NpM〇s FET) 62〇、64〇、 兩可變電阻（較適合的MJT) 670、680，以及兩反向器65〇、_實作 而成；Vdd電源供應器69〇與接地端695如圖所示。另外，閂之輸出 端為655及665，輸入端為675及685。 根據以上描述，由於製造過程的不可測性，編程特定記憶胞並且 不干擾到同一列線或位元線上其他記憶胞所需要的電流層級在整個記 憶體陣列巾都不同。當今技術能賊立絲愈大的記憶體陣列，使得 瞻上關題愈來愈嚴重。即使透過前述的方法對_作分段，因為無法 找到符合第二®巾星狀區域31〇的列電流和行電流組合，還是有許多 磁性晶片必須被捨棄。 因此’本發明即針對上述先前技術之數項缺失，提出—種用於磁 性隨機存取記憶體架構的可適性演算法，以有效克服上述之 【發明内容】 本發明之主要目的在提供一種演算法與測試流程，能夠把無法符 合快速寫人需求的雜隨機存取記憶體晶片，分成_符合—次編程 • (〇ne-time-programmable > OTP) (electrically programmable read only memory，EPR〇M )應用類型的晶片。 本毛月之另-目的在提供—種用於磁性隨機存取記憶體架構的可 適性演算法，其係提出—個於晶片上之演算法控制騎描述的磁性隨 機存取記憶體晶粒（die)區塊圖。 上述本發明之目的，係藉由—個對磁性隨機存取記憶體進行可適 性編程與測試的方法所達成，該方法包含以下步驟：設定一候選列電 1300562 流；設定一候選行電流， ·寫入輸入資料到一完整陣列中；從完整陣列 中讀出資料；比較讀取出的資料以及寫入的輸入資料；若讀取出的資 料以及寫入的輸入資料比較結果為負面的即發出一不匹配錯誤訊號。 額外的步驟係包括··當不匹配錯誤訊號發生時，則改變列電流或行電 流以嘗試一有限清單中列電流與行電流之組合；判斷是否已經試過所 有列電流與行電流之組合；若有不匹配錯誤訊號發生且所有列電流與 行電流之組合尚未全部試驗過時，重複前述之寫、讀、比較的步驟； 若發生不匹配錯誤訊號，且已經試驗過全部的電流組合，則發出一不 良晶粒訊號；若沒有發生不匹配錯誤訊號，卿定候騎電流與候選 列電流；若沒有不匹配錯誤訊號發生，則發出一良好晶粒訊號。 底下藉由具體實施例詳加說明，t更容腾解本發明之 術内容、特點及其所達成之功效。 又 【實施方式】 、在先別技射說明了，如第三圖所示透過將_以區域字元線的 ▲方式分割，可能的干擾只會發生在與職編程之位元組共用位元線的 思胞（memory cell)上，透過調整每個位元組的編程電流，對每個 敕隐胞進仃杨而不干制其他靖朗機率被大幅地提升。用於調 整一陣列中任意位元組之編程電流的演算法可增加寫入的時間，然 而’對於-次編程電子式可編程唯讀記憶體（〇TpEpR〇⑷類型的應 用而言，當編㈣透過程式設計㈣科部難單元制試器由外部 =制時’花費長時間的寫入是可以接受的。同樣地，對於電子式可抹 示可編程唯軌« (EEPRGM) _錢对可猶可編程唯讀 1300562 記憶體（FLASHEEPROM)這類可以容許數百微秒（百萬分之一秒） 至數十毫秒編程時間的應用而言，其可由晶片上之電路控制編程行 為。本發明提供-套方法、設計、測試演算法與製造流程，使磁性隨 機存取記賴在靜_齡取記賴、電子式可抹除可編程唯讀記憶 體、快閃式電子式可抹除可編㈣讀記紐及—次編程電子式可編程 唯讀記憶體的應用上，總產能可達到最大化。 第七圖所示為本發明之第—實施例，其為適合的列與行編程 • t流對磁性隨機存取記憶體陣列進行編程與測試之方法。第一步驟71〇 係設定-初始的候選（nGminal)列編程電流IR，以及-初始的候選行 編程電流1C ;在步驟72G中，糊這些初始的編程電流寫人全部的磁 性記憶體陣列單元；接著如步驟73〇，讀取全部的磁性記憶體陣列單 元，並與先前寫入的值做比較；步驟765如果從記憶胞讀出的資料與 先前寫入的資料之比較全部通過，則如步驟74〇所述鎖定或固定汛與 1C ;然後在步驟75〇中發出一良好晶粒訊號以作為結束。若有任何從 • 記憶胞中讀出之資料與先前寫入之資料比較失敗，如步驟760，則跳到 改變適合的行編程電流或列編程電流之步驟Μ，若尚未嘗試過所有可 能的IR+IC組合，則改變行或列編程電流，並跳回步驟no中對所有 記憶胞的寫人動作，接著，重複讀取全部的記親並與寫人的資料做 比較之動作，·若有任何比較失敗了如步驟’則再次進行步驟別改 變行編程電流或列編程電流，直到嘗試過所有可能的IR+Ic之組合。 若所有的IR+IC、组合皆已嘗試過，仍然如步驟76〇比較失敗，則進行 11 1300562 步驟780，發出-不良晶粒（die)訊號並終止。磁性隨機存取記憶體 陣列所進行之編程與測試到此結束，其使用上就如同一靜態隨機存取 記憶體（Static Random Access Memory，SRAM)。 第八圖所示為本發日狀第二實_，其為適合的列與行編程 電流之任何組合對記憶體P車列中任意位元組進行編程與測試的方法。 第-個步驟⑽，係設定-初始之候選（麵inal)列編程電流IR及一 初始之候選行編程電流1C，再如步驟82〇齡將被編程之位驗；接 φ 著如步驟830所述，讀取並儲存所有與將被編程之位元組（byte being programmed，BBP)位在同一行上之已編程位元組；接著如步驟84〇 所述，對將被編程之位元組進行編程；然後，將在步驟_中將被編 程之位元組讀回，並與原本儲存的將編程位元組（BBp)資料做比較， 如步驟850;若比較成功如步驟866，則讀取所有之將編程位元組(BBp) 在同-行上之已編程位it組，如步驟_所述，並與先前儲存之已編 程位元組資料作比較。若如步驟895所述比較成功，則如步驟奶所 • 述，#成功地縣被編綠元組進行編程，且沒有干翻其他位在同 一列上之位元組（BBP)時，發出一個訊號並結束。 如果讀取紐編程位元組（BBP)，且其與之_存的將被編程位 元組（BBP)資料比較失敗，如步驟_，則接下來之步驟轉為改變適 合的行電流或列電流，如步驟87〇，在嘗試過所有可能的IR+IC組合之 刖，持續改變行編程電流或列編程電流；如果嘗試過所有ir+ic組合 且發生失敗如步驟854，則如步驟865所述，發出一不良晶粒（die) 12 1300562 的訊號以停止流程。 若是讀取同一行上已被編程的位元組，且此位元組與先前儲存之 已編程位元組資料味失敗，如步_，顺下來之步轉為改變適 。之灯電肌或適合之列電流。先如步驟875所述改變行編程電流或列 編程電流，除非已經嘗試過所有可能的則c組合；若在嘗試過所有 IR+IC組合後發生失敗訊號如步驟m，則如步驟祕所述，發出一不 良曰曰粒（die)魏以分止流权，若還有未嘗試的組合而通過如步驟845， •貝變對將編程位元組⑽P)進行編程之步驟840，流程繼續進行。 上述方法亦可用於回復或更正因先前嘗試對陣列進行編程與測試 時所干擾到之位元組；同樣地，上述方法亦可用於同一列或同一字元 線上之位元組。在此延伸的應財，前述所提及行之處均要改成列。 第九騎7F為本發明之第二實補，其為彻適合之列與行編程 電流的任意組合對整個記憶體陣列進行編程之方法。第一步驟910係 將陣列的起始紐奴㈣觀程德元組（BBP);接魏此將編程 籲之位元、，且（BBP)進行先如於第八圖中所定義之方法或流程。第八圖中 是對記憶體陣列中任意單-位元組進行編程與測試之方法，當成功完 成將編程位元組（BBP)的寫入後，接著進行第九圖之步驟930，檢查 將編程位元組（BBP)是否為記憶體陣列中要被編成的最後位址，若步 驟930之判斷結果為「是」，則如步驟94〇所述，發出一個良好記憶 體陣列或子陣列之訊號’並結束流程；若步驟93〇之判斷結果為「否」， 則遞增將編程位元組（BBP) ’並回到步驟92〇，以新的將編程位元組 13 1300562 (BBP)重複弟八圖所不之弟》一測试流程。在這個方法中，整個記惊體 陣列都會使用第八圖所示之第二測試流程來進行編程與測試，若有晶 粒發生失敗，其與第八圖所示之第二測試流程所描述的失敗有關。 第十圖為一使用晶片上之適當列與行編程電流產生器與演算法控 制器的磁性隨機存取記憶體電路之方塊圖，磁性隨機存取記憶體的主 要輸入端包括：一位址匯流排1060、一雙向資料匯流排1〇7〇與複數控 制線，而這些控制線包括：一晶片致能1071、一輸出致能1〇72及一寫 入（編程）訊號1073 ;位址匯流排1060驅動位址緩衝區1〇8〇，這些 位址緩衝區輸出至-位址多。位址多；在外部位址匯流排 與内部位址暫存器輸出之間做選擇，其中内部位址暫存器係由演算法 控制器1075驅動，此演算法控制器實作出如第七圖、第八圖與第九圖 所述之方核程，這些方法要能預先將位址暫存器設定成必須的值。 雙向資料匯流排麵與輸入輸出緩衝區聰相接，此輸入輸出緩衝 區依次與資料暫存器和感應放大器娜相接，且與演算法控制器簡 中之貝料暫存器1〇55相接。記憶體子單元丨麵是由一記憶體子陣列 ^列驅^觸、—行轉11 1G4G或雙向位元線電流之複數驅 動器及-適當電流產生器卿組成，其中記憶體子單元圆可透過 " 式寫入一個位元組的資料，例如將位元組的值‘10110011，放入 驅動器中，並透過字元驅動器來選擇要將被編程之位元组 (BBP)〇 # ®所不為本發明之第四實施例，其為一不使用晶片上適當 rs、 14 1300562 列與行編㈣流與演算法控繼，㈣對雜_存取記憶體進行編 程、測試及排細產生-:欠編料子切祕唯讀純體（〇τρ EPROM)之方法。這意味著在第十圖所描述之以巾，演算法控制器 浙5是在位於晶片外部之-外部測試器巾。而第十—圖所描述之方法 係由在心體_上完整的第—測試流程開始，該第—職流程如第 七圖所述’其係嘗試對整個磁性隨機存取記憶體編程及測試，包括了 寫入與讀出整個陣列，並找出可接受之適合行編程電流與列編程電 _ 流；若如步驟1160所述，如果對整個陣列的讀取或測試成功，則此方 法完成，並發出訊號表示此記憶體陣列適合當作標準靜態隨機存取記 憶體（staticRAM，SRAM)使用，亦即可多次讀寫；若對整個陣列的 讀取或測試失敗如步驟1140，則進行第九圖所示之第三測試流程 112〇。第三測試流程係嘗試一次對整個磁性記憶體中之一位元組進行編 程之方式，如果第三測試流程如步驟117〇所述成功，則此方法完成， 並發出訊號表示此記憶體陣列適合作為一次編程電子式可編程唯讀記 Φ 憶體（0TPEPR0M)使用；若第三測試流程失敗如步驟1150，則如步 驟1130所述發出一必須被捨棄之不良晶粒（die)訊號。 第十二圖所示為本發明之第五實施例，其為一種使用晶片上適當 列、行編程電流與演算法控制器，對磁性隨機存取記憶體進行編程、 測試與排序，以產生電子式可抹除可編程唯讀記憶體（electrically erasable pn)gmmmable read only memory，EEPROM)或快閃式電子式 可抹除可編程唯讀記憶體（FlashEEPROM)之方法。這意味著在如第 15 ⑧ 1300562 十圖所描述之晶>i巾，演算法是在第十騎示之晶片内部。 第十二_描述之方法，其—開雜在記《_上完整實施第 七圖所述之第-測試流程’其係嘗試對整個磁性隨機存取記憶體進行 編程及測試，這包括了寫入與讀出整個陣列，並找出可接受之適合的 行與列編程電流；若對整個陣列之讀取_試成功，如步驟丨細則 此方法完成，並發出訊號表示此記憶體陣列適合當作標準靜態隨機存 取記憶體（staticRAM，SRAM)使用，亦即可多次讀寫；如果對整個 # 陣列之讀取或測試失敗’如步驟測，則進行第九圖所示之第三測試 流程122G。此第三測試流程係嘗試以—次—個位元組的方式對整個磁 性記憶體跡’如果第三測試流程成功，航方法完成，並發出訊號 表示此記憶體陣列適合當作電子式可抹除可編程唯讀記憶體晶粒 (EEPROM die)(如步驟1270)錄閃式電子式可抹除可編程唯讀記 憶體晶粒（FLASHEEPROMdie)(如步驟1280)使用；若第三測試流 程失敗如步驟125G，則如步驟123G所述，發出必須被捨棄之一不良晶 • 粒訊號。 本發明之優點係透過調整每個位元組之編程電流，大幅提升對每 一個記憶胞進行編程又不干擾記憶體陣列中其他記憶胞之機率。本發 明提供一套方法、設計、測試演算法與製造流程，使磁性隨機存取記 憶體在靜態隨機存取記憶體、電子式可抹除可編程唯讀記憶體 (EEPROM)、快閃式電子式可抹除可編程唯讀記憶體（Flash eeprom)及一次編程可抹除記憶體（0TPEPR0M)應用上的總產能 16 1300562 達到最大化。 唯以上所述者，僅為本發明之較佳實施例而已，並非用 發明實施之範圍。故即凡依本發明巾請範_述之特徵 =本 均等變化或修飾，均應包括於本發明之申請專利範圍内。 _之 【圖式簡單說明】 第一圖為先前技術中包含磁性通道接合、隔離電晶體、字元線及位一 線之一磁性隨機存取記憶胞之示意圖。 第二圖為一磁性穿遂接面（MTJ)之磁滯迴圈示意圖。 •第二圖為單一磁性穿遂接面磁性隨機存取記憶胞之可程式化能力之星 狀不意圖。 第四圖為先前技術中將字元線分段之磁性隨機存取記憶胞陣列示意 圖。 第五圖為一典型之可程式化之可調適電流源示意圖。 第六圖為一典型之用於設定可調適電流源之非揮發性閂示意圖。 第七圖為本發明巾第-實酬之示意圖，其係為—種適合的列與 • 行編程電流對磁性隨機存取記憶體陣列進行編程與測試之方法。 第八圖為本發Θ种第二實施例之示意圖，其係為_種利用適合的列與 行編程電流之任意組合對記憶體_巾任—位元組進行編程與測試之 方法。 第九圖為本《巾第三實補之示細，其係為—種_適合的列與 行編知電流之任意組合對整個記憶體陣列進行編程之方法。 第十圖為-使用晶上適當電流產生II與演算法控制器之磁性隨機存 取記憶體電路之方塊圖。 17 ⑧ 1300562 弟十一圖為本發明中第四實施例之示意圖，其係為—種不使用晶片上 之適田列與仃編程電流及演算法控㈣’即可對磁性隨機存取記憶體 進灯、’綠、剛試與解，以姓—次編程電？式可編程唯讀記憶體(OTP EPROM)之方法。 第！1 一圖為本發明中第五實施例之示意圖，其係為一種使用晶片上之 ，田列^與行編程電流與演算法控制器，對磁性隨機存取記憶體進行編 耘測试與排序’以產生電子式可抹除可編程唯讀記憶體（EEPROM)、 快閃式電子式可抹除可編程唯讀記憶體（FLASHEEPROM)之方法。 【主要元件符號說明】 110位元線 120位元線電流 130位元線磁場 140字元線 150絕緣電晶體 160子元線磁場 170字元線電流 180自由層 190絕緣層 195固定層 310星狀區域 410磁性隨機存取記憶胞 420全域字元線 430選擇線N-1 1300562The product slave 8〇N is incremented by 1, the memory cell in the first segment is shown together with the segmentation word το line selection transistor 491, and the segmented word line selection transistor has a return-return line. Attached to the - global word line return (Globalwordlin (four) (four) thoroughly, along the global word 70 line 42G segmentation word line selection of the crystal system used to enclose or exclude the segment affected by memory cell programming, - strip Group or group of bytes. As shown in the fourth figure, the global character line 420 and the area word line 49 are both the columns mentioned in the first figure, and the bit line 460 in the fourth figure is the first The line mentioned in the figure. The sixth figure is not a non-volatile latch (n〇n %iatiie latch) realized by magnetic piercing joints, and the fifth figure shows that one can pass this non- The volatile latch is programmed to adjust the current level of the adjustable current source. The two figures show a way to change the programming current. Anyone familiar with this technology can implement an adjustable current source in many different ways. A latch unit 510 is used, which is detailed in the sixth figure, and three current sources 52 are transmitted through the transistor 53. The selective activation of 0 is selectively combined; a combined current produces an adjustable current, which is the total current ItQtal 550; - Vdd power supply 540 is used to supply power to current sources II, 12 And 13. The non-volatile flash in the sixth figure utilizes two p-channel MOS field-effect transistors (PM〇s 1300562 FET) 610, 630, two n-channel MOSFETs (NpM〇s FET) 62 〇, 64〇, two variable resistors (suitable MJT) 670, 680, and two inverters 65〇, _ are made; Vdd power supply 69〇 and ground 695 are shown in the figure. The outputs of the latches are 655 and 665, and the inputs are 675 and 685. According to the above description, due to the unmeasurability of the manufacturing process, the specific memory cells are programmed and do not interfere with the current required by other memory cells on the same column line or bit line. The level is different in the entire memory array towel. Today's technology can thieves the larger the memory array, making the problem more and more serious. Even if the above method is used to segment the _ because it can not find the second ® towel star-shaped area 31 〇 column current In the combination of row currents, there are still many magnetic wafers that must be discarded. Therefore, the present invention proposes an adaptability algorithm for a magnetic random access memory architecture for the above-mentioned prior art missing, to effectively overcome the above-mentioned problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide an algorithm and a test flow, which can divide a random random access memory chip that cannot meet the needs of fast writing into _ compliant-time programming. (〇ne-time-programmable &gt ; OTP) (electrically programmable read only memory, EPR 〇 M ) application type of wafer. Another purpose of this month is to provide an adaptive algorithm for magnetic random access memory architecture, which proposes a on-wafer algorithm to control the magnetic random access memory die of the ride description ( Die) block diagram. The above object of the present invention is achieved by a method for adaptive programming and testing a magnetic random access memory, the method comprising the steps of: setting a candidate column 1300562 stream; setting a candidate row current, Write input data to a complete array; read data from the complete array; compare the read data with the written input data; if the read data and the written input data are negative, the result is sent One does not match the error signal. The additional steps include: when the mismatch error signal occurs, the column current or the row current is changed to try a combination of column current and row current in a limited list; to determine whether all combinations of column current and row current have been tried; If there is a mismatch error signal and all combinations of column current and line current have not been tested, repeat the steps of writing, reading and comparing; if a mismatch error signal occurs and all current combinations have been tested, then A bad grain signal; if no mismatch error signal occurs, the current is waiting for the current and the candidate column current; if no mismatch error signal occurs, a good grain signal is sent. The details of the invention, the features and the effects achieved by the present invention will be further explained by the detailed description of the specific embodiments. [Embodiment], in the first shot, as shown in the third figure, by dividing _ by the ▲ way of the area word line, the possible interference will only occur in the bit of the job programming. On the line of the memory cell, by adjusting the programming current of each byte, the probability of entering each of the sinister cells without causing other Jinglang is greatly improved. The algorithm used to adjust the programming current of any byte in an array can increase the write time, whereas 'for-time programming electronically programmable read-only memory (〇TpEpR〇(4) type of application, when (4) Through programming (4) Department of the difficult unit tester from the external = system time 'will take a long time to write is acceptable. Similarly, for the electronic can be programmed programmable tracked « (EEPRGM) _ money pair In the case of applications such as FLASHEEPROM, which can tolerate hundreds of microseconds (millionths of a second) to tens of milliseconds of programming time, it can be controlled by circuitry on the wafer. Provides a set of methods, designs, test algorithms and manufacturing processes to enable magnetic random access to be recorded in static aging, electronically erasable programmable read-only memory, and flash electronically erasable The total capacity can be maximized in the application of (4) reading and reading-time electronic programmable read-only memory. The seventh figure shows the first embodiment of the invention, which is suitable for column and row programming. • t stream is magnetically stored The memory array is programmed and tested. The first step 71 sets the initial candidate (nGminal) column programming current IR, and - the initial candidate row programming current 1C; in step 72G, the initial programming current is pasted. Write all of the magnetic memory array cells; then, as in step 73, read all of the magnetic memory array cells and compare them with previously written values; step 765 if the data read from the memory cells is previously written If the comparison of the data is all passed, then lock or fix 汛 and 1C as described in step 74; then send a good grain signal in step 75 to end. If there is any data read from the memory cell and The previously written data fails to compare. If step 760, skip to the step of changing the appropriate row programming current or column programming current. If all possible IR+IC combinations have not been tried, change the row or column programming current, and Jump back to the write action of all the memory cells in step no, and then repeat the action of reading all the recorded relatives and comparing with the data of the writer. If any comparison fails, such as step 'Steps again to change the line programming current or column programming current until all possible combinations of IR+Ic have been tried. If all IR+ICs, combinations have been tried, still fail as in step 76, then proceed 11 1300562 Step 780, issuing a bad die signal and terminating. The programming and testing of the magnetic random access memory array ends here, and the use is like the same static random access memory (Static Random Access) Memory, SRAM) The eighth figure shows the method of programming and testing any byte in the memory P train in any combination of suitable column and row programming currents. The first step (10) is to set the initial candidate (plane inal) column programming current IR and an initial candidate row programming current 1C, and then, as in step 82, the program will be programmed; Read, store and store all programmed bytes on the same line as the byte being programmed (BBP); then, as described in step 84, the pair of bytes to be programmed Programming; then The byte to be programmed will be read back in step_ and compared with the originally stored programming byte (BBp) data, as in step 850; if the comparison is successful as step 866, then all will be programmed. The byte (BBp) is programmed bit group on the same-line as described in step_ and compared to the previously stored programmed byte data. If the comparison is successful as described in step 895, then, as described in the step milk, the successful county is programmed by the green group, and when the other bits (BBP) in the same column are not turned over, a The signal ends. If the new programming byte (BBP) is read and it fails to compare with the programmed byte (BBP) data, as in step _, the next step is to change the appropriate row current or column. The current, as in step 87, continues to change the row programming current or column programming current after all possible IR+IC combinations have been attempted; if all ir+ic combinations have been tried and a failure occurs as in step 854, then as in step 865 Said, send a bad die 12 1300562 signal to stop the process. If the byte that has been programmed on the same line is read, and the byte and the previously stored programmed byte data fail, such as step _, the step is changed to change. The light of the electric muscle or the suitable current. First change the row programming current or column programming current as described in step 875, unless all possible combinations of c have been tried; if a failure signal such as step m occurs after all IR+IC combinations have been tried, as described in the step, A bad die is issued to terminate the flow, and if there are still untried combinations, the process proceeds to step 840 by programming the programming byte (10) P) as in step 845, and the flow continues. The above method can also be used to reply or correct the byte that was disturbed by the previous attempt to program and test the array; as such, the above method can also be used for the same column or a byte on the same word line. In this case, the extensions mentioned above must be changed to columns. The ninth rider 7F is the second complement of the present invention, which is a method of programming the entire memory array in any combination of suitable column and row programming currents. The first step 910 is to start the array of the new Nunu (four) Guancheng Deyuan group (BBP); the Wei will program the bit, and (BBP) the method or process as defined in the eighth figure. The eighth figure is a method for programming and testing any single-byte group in the memory array. After successfully writing the programming byte (BBP), step 930 of the ninth figure is performed, and the check will be performed. Whether the programming byte (BBP) is the last address to be programmed in the memory array. If the result of the determination in step 930 is "YES", then a good memory array or sub-array is issued as described in step 94. The signal 'ends the process; if the result of the determination in step 93 is "No", then the programming byte (BBP) is incremented and returns to step 92, to repeat the new programming byte 13 1300562 (BBP) A test procedure for the younger brother of the Eight Diagrams. In this method, the entire array of shots will be programmed and tested using the second test flow shown in Figure 8. If a die fails, it is described in the second test flow shown in Figure 8. Related to failure. Figure 10 is a block diagram of a magnetic random access memory circuit using an appropriate column and row programming current generator and algorithm controller on the wafer. The main input of the magnetic random access memory includes: an address convergence. Row 1060, a bidirectional data bus 1 〇 7 〇 and a plurality of control lines, and these control lines include: a wafer enable 1071, an output enable 1 〇 72 and a write (program) signal 1073; address bus The 1060 drives the address buffer 1〇8〇, and these address buffers output to - many addresses. There are many addresses; a choice is made between the external address bus and the internal address register output, wherein the internal address register is driven by the algorithm controller 1075, and the algorithm controller is implemented as shown in the seventh figure. For the square nucleus described in the eighth and ninth diagrams, these methods are capable of setting the address register to a necessary value in advance. The two-way data bus surface is connected with the input and output buffers. The input and output buffers are connected to the data register and the sense amplifier, and are connected with the data processor of the algorithm controller. Pick up. The memory subunit is composed of a memory sub-array, a turn-to-turn 11 1G4G or a bidirectional bit line current multi-function driver and a suitable current generator, wherein the memory sub-unit is permeable. " write data of a byte, for example, put the value of the byte '10110011 into the drive, and select the byte to be programmed (BBP) 〇# ® through the character driver For the fourth embodiment of the present invention, it is to use a suitable rs, 14 1300562 column and row (four) stream and algorithm control on the wafer, and (4) to program, test and fine-produce the impurity_access memory. : The method of arranging the secrets to read the pure body (〇τρ EPROM). This means that in the tenth figure, the algorithm controller Zhejiang 5 is an external tester wiper located outside the wafer. The method described in the tenth-graph is started by the complete first test flow on the mind body, and the first job process is as described in the seventh figure, and the system attempts to program and test the entire magnetic random access memory. Include writing and reading the entire array and finding acceptable line programming current and column programming power_flow; if, as described in step 1160, if the reading or testing of the entire array is successful, then the method is completed, And the signal indicates that the memory array is suitable for use as a standard static random access memory (SRAM), and can be read and written multiple times; if the reading or testing of the entire array fails as in step 1140, then the first The third test flow 112 shown in Figure IX. The third test procedure is a method of programming one byte in the entire magnetic memory. If the third test flow is successful as described in step 117, the method is completed, and a signal indicates that the memory array is suitable. As a one-time programming electronic programmable read-only Φ memory (0TPEPR0M); if the third test flow fails as step 1150, then a bad die signal that must be discarded is issued as described in step 1130. Figure 12 is a fifth embodiment of the present invention, which is a method for programming, testing and sorting magnetic random access memory using an appropriate column, row programming current and algorithm controller on a wafer to generate electrons. A method of erasable programmable read only memory (EEPROM) or flash electronically erasable programmable read only memory (FlashEEPROM). This means that in the crystal >i towel as described in Fig. 15 8 1300562, the algorithm is inside the wafer of the tenth riding. The twelfth-description method, which is described in the "Completely implementing the first-test flow described in the seventh figure", attempts to program and test the entire magnetic random access memory, which includes writing Enter and read the entire array and find acceptable row and column programming currents; if the entire array is read, the test is successful, as in the step, the method is completed, and a signal indicates that the memory array is suitable for Used as standard static random access memory (SRAM), it can be read and written multiple times; if the entire # array is read or tested failed 'step test, then the third test shown in the ninth figure Flow 122G. This third test procedure attempts to treat the entire magnetic memory trace in a time-by-byte manner. If the third test process is successful, the navigation method is completed, and a signal is sent indicating that the memory array is suitable for electronic wiping. In addition to the programmable read-only memory die (EEPROM die) (step 1270), flash-type electronic erasable programmable read-only memory die (FLASHEEPROM die) (as in step 1280); if the third test process fails In step 125G, as described in step 123G, a bad crystal grain signal must be discarded. The advantage of the present invention is that by programming the programming current for each byte, the probability of programming each memory cell without interfering with other memory cells in the memory array is greatly increased. The present invention provides a method, design, test algorithm and manufacturing flow for magnetic random access memory in static random access memory, electronic erasable programmable read only memory (EEPROM), flash electronic Maximize the total capacity of the programmable eraser memory (Flash eeprom) and the one-time programmable erasable memory (0TPEPR0M) application of 16 1300562. The above is only the preferred embodiment of the present invention and is not intended to be in the scope of the invention. Therefore, the features of the present invention are all included in the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic diagram of a magnetic random access memory cell including a magnetic channel junction, an isolation transistor, a word line, and a bit line in the prior art. The second figure is a schematic diagram of the hysteresis loop of a magnetic piercing joint (MTJ). • The second figure is a star-shaped intent of the stylized ability of a single magnetic piercing interface magnetic random access memory cell. The fourth figure is a schematic diagram of a magnetic random access memory cell array in which the word lines are segmented in the prior art. The fifth picture shows a typical programmable current source. The sixth figure is a typical non-volatile latch diagram for setting an adjustable current source. The seventh figure is a schematic diagram of the first embodiment of the invention, which is a method for programming and testing a magnetic random access memory array by a suitable column and row programming current. The eighth figure is a schematic diagram of a second embodiment of the present invention, which is a method for programming and testing a memory_cloth any-bit group using any combination of suitable column and row programming currents. The ninth figure is the third embodiment of the towel, which is a method for programming the entire memory array by any combination of suitable column and row programming currents. The tenth figure is a block diagram of a magnetic random access memory circuit using an appropriate current generation II on the crystal and an algorithm controller. 17 8 1300562 The eleventh figure is a schematic diagram of the fourth embodiment of the present invention, which is a kind of magnetic random access memory which can be used without using the field array and the 仃 programming current on the wafer and the algorithm control (4) Into the light, 'green, just try and solve, with the last name - programming power? A method of programmable read only memory (OTP EPROM). The first! 1 is a schematic view of a fifth embodiment of the present invention, which is a method for compiling and sorting magnetic random access memory using a matrix and row programming current and algorithm controller on a wafer. 'To create an electronically erasable programmable read only memory (EEPROM), flash electronically erasable programmable read only memory (FLASHEEPROM) method. [Main component symbol description] 110 bit line 120 bit line current 130 bit line magnetic field 140 word line 150 insulated transistor 160 sub-line magnetic field 170 word line current 180 free layer 190 insulation layer 195 fixed layer 310 star shape Region 410 magnetic random access memory cell 420 global word line 430 select line N-1 1300562

440選擇線N 450 全域字元線回報（Global Word line return) 460位元線 470第N_1個區段 480第N個區段 490區域字元線 491分段字元線選擇電晶體 510閃單元 520電流源 530電晶體 540電源供應器 550總電流 610、630P通道金氧半場效電晶體 620、640 N通道金氧半場效電晶體440 select line N 450 Global Word line return 460 bit line 470 N_1th section 480 Nth section 490 area word line 491 Segment word line select transistor 510 flash unit 520 Current source 530 transistor 540 power supply 550 total current 610, 630P channel gold oxygen half field effect transistor 620, 640 N channel gold oxygen half field effect transistor

650、660反向器 655、665閂之輸出端 670、680可變電阻 675、685閃之輸入端 690電源供應器 695接地端 1010記憶體子單元 19 1300562 1020記憶體子陣列 1030適當電流產生器 1040行驅動器 1050列驅動器 1055資料暫存器 1060位址匯流排 1065位址暫存器 1070雙向資料匯流排 1071晶片致能 1072輸出致能 1073寫入（編程）訊號 1075演算法控制器 1080位址緩衝區 1085資料暫存器和感應放大器 1090位址多工器 1095輸入輸出緩衝區650, 660 inverter 655, 665 latch output 670, 680 variable resistor 675, 685 flash input 690 power supply 695 ground terminal 1010 memory subunit 19 1300562 1020 memory sub-array 1030 appropriate current generator 1040 row driver 1050 column driver 1055 data register 1060 address bus row 1065 address register 1070 bidirectional data bus row 1071 chip enable 1072 output enable 1073 write (program) signal 1075 algorithm controller 1080 address Buffer 1085 data register and sense amplifier 1090 address multiplexer 1095 input and output buffer

Claims (1)

1300562 修正本 年月日修正替換w η 、申請專利範圍： 一種對磁性隨機存取記憶體進行編程與測試的可適性方法，其係包含 下列步驟：1300562 Revised this year's monthly correction replacement w η , the scope of patent application: An adaptability method for programming and testing magnetic random access memory, which includes the following steps: a·设定一候選列電流（nominal row current); b·没定一候選行電流（nominal column current); c.寫入輸入資料到一完整陣列； d·由該完整陣列中讀取資料； e·比較該讀取之資料與該寫入之輸入資料； f·若該讀取之資料與該寫入之輸入資料之比較結果為負面的，則發出 一不匹配錯誤訊號（mismatch failure signal); g·若發生該不匹配錯誤訊號，則改變列電流或行電流以嘗試一有限清 單中之列電流與行電流組合； h·檢查是否所有該列電流與該行電流之組合都已嘗試過；a·setting a candidate column current; b·nominal column current; c. writing input data to a complete array; d· reading data from the complete array; e. comparing the read data with the written input data; f. if the comparison between the read data and the written input data is negative, then a mismatch failure signal is issued. g. If the mismatch error signal occurs, change the column current or row current to try a combination of the column current and the row current in a limited list; h· check if all combinations of the column current and the row current have been tried ; j. 若發生该不匹配錯誤訊號，且還未嘗試過所有該列電流與該行電流之 組合，則重複步驟c、d和e; k. 右發生該不匹配錯誤訊號’且已嘗試過所有前述之電流、组合，則發 出一不良晶粒（die)訊號； m·若該不匹配錯誤織沒有發生，靡定贿選行電赫雜選列電 流；以及 η·若該不匹配錯誤訊號沒有發生，則發出一良好晶粒訊赛。 2.如申請專繼_丨_狀對雜隨機存取記憶體進行齡與測試的 可適性方法’其中該改變職流與行電流之步_透過程式化可調適電 21 1300562 流源來達成。 3·如申請專利範圍第1j. If the mismatch error signal occurs and no combination of all of the column currents and the row current has been tried, repeat steps c, d, and e; k. The mismatch error signal occurs right 'and has tried all The current current and combination send a bad die signal; m. If the mismatch does not occur, the bridging line is selected; and η· if the mismatch error signal is not present Occurs, a good grain game is issued. 2. If the application is successful _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3. If the patent application scope is 1 修正本 項所述之對雜_躲記㈣進行姉與測試的 可適性方法，其中該改變列電流與行電流之步驟，_巧試該有限清 單中之列電流與行電流組合，其侧在於產生不纽㈣場方向、也不 會無意地影響到共賴-字s線或同—位元線上磁性記憶胞的列電流與 行電流組合。Correct the adaptability method for the 姊 and test of the miscellaneous _ hide (4) described in this section, wherein the step of changing the column current and the row current, _ the combination of the current and the row current in the limited list, The direction of the column current and the line current of the magnetic memory cells on the common-bit line or the same-bit line is not inadvertently affected. 種在磁性隨機存取記憶體帽於隨意位元組進行編程與測試之可適性 方法，包括下列步驟： a.設定一候選列電流； b·設定一候選行電流； c.儲存將被編程之位元組； d·讀取位在同-行上所有已被編程之位元組，並齡到—記錄暫存 3S · ，An adaptive method for programming and testing a magnetic random access memory cap in a random byte comprises the steps of: a. setting a candidate column current; b setting a candidate row current; c. storing will be programmed Bytes; d·read bits in the same-line all the programmed bytes, and age-to-record temporary 3S · , e •對將被編程的位元組或被干擾的位元組進行編程； f.讀取將被編程之該位元組； g·比較該讀出的資料與一寫入之輸入資料； h·若該讀取之資料與該寫入之輸入資料之比較結果為負面的，則發出 一不匹配錯誤訊號； k.若該不匹配錯誤訊號發生，則調整列電流或行電流以嘗試一有限清 單中之列電流與行電流組合； m·檢查是否所有該列電流與行電流之組合都已嘗試過； 22 1300562 I--j 修正本 • 9». i i9rf«! 、 n.若發生該不匹配錯誤訊號，且還未嘗試過所有該列電流與該行電流 之組合，則重複步驟e、f和g ; 〇·若發生該不匹配錯誤訊號，且已嘗試過所有該列電流與該行電流之 組合，則發出一不良晶粒訊號； P·讀取所有位在同行上之該已編程位元組； q·比較所有位在同行上的該已編程位元組與存在該記錄暫存器中位元 組，若所有位在同一行上之該已編程位元組與該記錄暫存器中的值相 9) 同，則發出一無干擾狀況（non-disturb condition)的訊號，並跳到步 驟z ; r·若沒有發生該無干擾狀況，則改變列電流或行電流以嘗試一有限清單 中之列電流與行電流組合； s·檢查是否所有該列電流與行電流之組合都已嘗試過； t. 若無干擾狀況沒有發生，而且還未嘗試過所有該列電流與行電流之組 合，則重複步驟e、f和g ;e • programming the byte or the disturbed byte to be programmed; f. reading the byte to be programmed; g· comparing the read data with a written input; h · If the comparison between the read data and the written input data is negative, a mismatch error signal is issued; k. if the mismatch error signal occurs, adjust the column current or the line current to try a limited The current in the list is combined with the line current; m·Check if all combinations of current and line current have been tried; 22 1300562 I--j Amendment • 9». i i9rf«!, n. If this happens If the error signal is not matched and all combinations of currents and currents have not been tried, steps e, f, and g are repeated; 〇·If the mismatch error signal occurs, and all of the column currents have been tried a combination of row currents, a bad grain signal is sent; P· reads all programmed bits in the peer; q· compares all programmed bits in the peer with the presence of the record a byte in the memory, if all bits are on the same line The programmed byte is the same as the value in the record register, and a non-disturb condition signal is sent and jumps to step z; r. if the interference-free condition does not occur , then change the column current or row current to try a combination of the current and row current in a limited list; s · check if all combinations of current and row current have been tried; t. if no interference occurs, and If all combinations of current and row current have not been tried, repeat steps e, f and g; u. 如果無干擾狀況沒有發生，且已嘗試過所有該列電流與行電流之組 合’則發出一個不良晶粒訊號；以及 ζ·訊號程序（signalingprocess)結束。 5· 如申請專利範圍第4項所述之對磁性隨機存取記憶體進行編程與測試 的可適性方法，其中該改變列電流與行電流之步驟，係透過程式化可調 適電流源來達成。 6_如申請專利範圍第4項所述之對磁性隨機存取記憶體進行編程與測試 23 修正本u. If the interference-free condition does not occur and all combinations of current and line currents have been tried, a bad grain signal is issued; and the signalling process ends. 5. An adaptability method for programming and testing a magnetic random access memory as described in claim 4, wherein the step of changing the column current and the row current is achieved by stylizing an adjustable current source. 6_Programming and testing the magnetic random access memory as described in item 4 of the patent application. 1300562 的可適性方法’其巾該改賴錢與行電叙步驟，侧財試該有限 清單中之職流與行電流組合，其伽在於產生不纽變磁場方向、也 不會無意地影響職關-字元線或同_位元線上磁性記憶胞的列電流 與行電流組合。 -種在磁性隨機存取記憶體帽於隨意位元組進行編程與測試之可 適性方法，其係包括下列步驟·· a·設定一候選列電流； b·設定一候選行電流； e•儲存將被編程的位元組； d·項取位在同-列上之所冑已編程位元組，並將其儲存到-記錄暫存 3S · II， e.對將被編程的該位元組或是被干擾的位元組進行編程； f·讀取該已編程位元組； g·比較該讀取之資料與一寫入之輸入資料； h.若該讀取之資料與該寫入之輸入資料的比較結果為負面的，則發出 一不匹配錯誤訊號； k·若發生該不匹配錯誤訊號，則改變列電流或行電流以嘗試一有限清 單中之列電流與行電流組合； 瓜檢查是否所有該列電流與該行電流之組合都已嘗試過； η·若有不匹配錯誤訊號發生，而且還未嘗試過所有該列電流與行電漭 之組合，則重複步驟e、f和g; 24 1300562 i曰r替換頁 修正本 〇_若有不匹配錯誤訊號發生，且已嘗試過所有該列電流與該行電流之 組合’則發出一不良晶粒（die)訊號； ρ·讀取所有位在同一列上之該已編程位元組； q·比較所有位在同一列上之該已編程位元組與存在該記錄暫存器中之 該位元組的值，若所有位在同一行上之該已編程位元組與該記錄暫存 器中之該位元組的值相同，則發出一無干擾狀況（non-disturb condition)訊號，並跳到步驟z ;1300562's adaptability method 'the towel should change the money and the power-study step, the side financial test the combination of the job flow and the line current in the limited list, the gamma is to produce the direction of the magnetic field, and it will not affect the job unintentionally. The column current of the magnetic memory cell on the off-character line or the same-bit line is combined with the line current. An adaptive method for programming and testing a magnetic random access memory cap in a random byte, comprising the steps of: a setting a candidate column current; b setting a candidate row current; e• storing The byte to be programmed; the d. item is taken from the programmed byte on the same-column and stored in the -record temporary 3S · II, e. for the bit to be programmed The group or the disturbed byte is programmed; f·read the programmed byte; g· compare the read data with a written input data; h. if the read data and the write If the comparison result of the input data is negative, a mismatch error signal is issued; k. If the mismatch error signal occurs, the column current or the row current is changed to try a combination of the current and the row current in a limited list; The melon checks whether all combinations of the current and the current of the row have been tried; η· If there is a mismatch error signal and has not tried all combinations of current and row current, repeat steps e, f And g; 24 1300562 i曰r replacement page revision 〇_If there is a mismatch error signal, and all combinations of currents and currents have been tried, then a bad die signal is sent; ρ·read all bits in the same column that have been programmed a byte; q. compares the programmed byte of all bits on the same column with the value of the byte in the record register, if all bits are on the same line of the programmed byte Same as the value of the byte in the record register, then issue a non-disturb condition signal and jump to step z; r·若沒有發生該無干擾狀況，則改變列電流或行電流以嘗試一有限清單 中之列電流與行電流組合； s·檢查是否所有該列電流與行電流之組合都已嘗試過； t·若無干擾狀況沒有發生，且還未嘗試過所有該列電流與行電流之組 合，則重複步驟e、f和g; u·若無干擾狀況沒有發生，且已嘗試過所有該列電流與行電流之組 合’則發出一不良晶粒（die)訊號；以及 ζ·訊號程序（signalingprocess)結束。 8·如巾請專利誠第7項所狀對雖賴存取記憶舰行編程與測試 的可適性方法，其中該改變列電流與行電流之步驟，乃是透過程式化可 調適電流源來達成。 9.如申請專利範圍第7項所述之對磁性隨機存取記憶體進行編程與測試 的可適性方法，其中該改變列電流與行電流之步驟，係用以嘗試該有限 清單中之列電流與行電流組合，其作用在於列出不會改變磁場方向、也 25 修正本 70線上複數磁性記憶胞之列 1300562 i & !日，正替換頁丨 不會無意地影響到共用同_字元線或 電流與行電流組合 程與測試之可 H). 一種在磁性隨機存取記憶體中對於個別位元組進行編 適性方法，包含下列步驟： a.將要被編程的位元組之陣列位址設定成記憶體陣列之起始位址； b·編程並測試該要被編程的位元組，·r. If the interference-free condition does not occur, change the column current or row current to try a combination of the current and the row current in a limited list; s·Check if all combinations of current and row current have been tried; • If no interference has occurred and no combination of current and line currents has been tried, repeat steps e, f, and g; u. If no interference has occurred, and all of the currents have been tried The combination of line currents 'issues a bad die signal; and the signal processing process ends. 8·If you want to apply the method of programming and testing the access memory ship, the step of changing the column current and the line current is achieved by stylizing the adjustable current source. . 9. An adaptability method for programming and testing a magnetic random access memory as described in claim 7 wherein the step of changing the column current and the row current is used to attempt a current in the limited list. In combination with the line current, the function is to list the direction of the magnetic field without changing the direction of the magnetic field, and to correct the 1300562 i & ! day of the magnetic memory cell on the 70th line, the replacement page does not inadvertently affect the shared same _ character Line or current and line current combination and test H). A method for compiling individual bytes in magnetic random access memory, comprising the following steps: a. Array bits of the byte to be programmed The address is set to the start address of the memory array; b·program and test the byte to be programmed, c.若該編程與測試之步騾指出不良晶粒 列的訊號，並跳至步驟h ; (dle)’則發財良記憶體陣 d. 比較該陣顺址與觀憶轉狀最後位址； e. 若該_位域該記__之該紐位址相等， 憶體陣列訊號，並跳至步驟h ; f·若該陣列位址與該記憶體陣列之該最後位址不相等 位址；c. If the step of programming and testing indicates the signal of the bad die column, and jump to step h; (dle) 'is the good memory matrix d. Compare the array address and the last address of the image recall; e. If the address of the _ bit field is equal to the address of the __, remember the body array signal and jump to step h; f. if the array address is not equal to the last address of the memory array ; 則發出一良好記 ’則增加該陣列 g·重複步驟b、c、d與e ;以及 h· 號程序（signalingprocess)結束。 α如申請專利範圍第10項所述之對磁性隨機存取記鋪中個別位元組 進行編程與職之可雜方法，其巾該難麵試係包括下列步驟： a·設定一候選列電流； b.設定一候選行電流； c·儲存將被編程之位元組； d讀取位铜-行上之射6難侃組，麵翻—記錄暫存器 26 (S ) 1300562 e. f. 年月日修正替換頁 97. R· 1 β_— 對將被編程之該位元組或已被干擾的位元組進行編程； 讀取該將被編程之位元組； g.比較該讀取之資料與一寫入之輸入資料； h_若該讀取之資料與該寫入之輸入資料之比較結果為負面的，則發出 一個不匹配錯誤訊號； k·若發生該不匹配錯誤訊號，則改變列電流或行電流以嘗試一有限清單 中之列電流與行電流組合；Then a good note is issued to increase the array g. Repeat steps b, c, d and e; and the end of the h· signing process. α is as described in claim 10 of the patent application, and the programming of the individual bytes in the magnetic random access memory is performed. The difficult interview includes the following steps: a·setting a candidate column current; b. Set a candidate row current; c· store the byte to be programmed; d read the bit copper - row on the 6 difficult group, face flip - record register 26 (S) 1300562 ef Correction replacement page 97. R·1 β_—programs the byte or the disturbed byte to be programmed; reads the byte to be programmed; g. compares the read data with a written input data; h_ if the comparison between the read data and the written input data is negative, then a mismatch error signal is issued; k. if the mismatch error signal occurs, the column is changed Current or line current to try to combine the current and row current in a limited list; m·檢查是否所有該列電流與行電流之組合皆已嘗試過； η.若有不匹配錯誤訊號發生，而且還未嘗試過所有該列電流與行電流之 組合，則重複步驟e、f和g ; 〇_若有不匹配錯誤訊號發生，且已嘗試過所有該列電流與行電流之組 合，則發出一不良晶粒（die)訊號； ρ·讀取所有在同一行上之該已編程位元組；m·Check if all combinations of current and row current have been tried; η. If there is a mismatch error signal and you have not tried all combinations of current and row current, repeat steps e, f and g ; 〇 _ If there is a mismatch error signal, and all combinations of current and line currents have been tried, a bad die signal is sent; ρ·Read all programmed on the same line Byte group 修正本 q·比杈所有在同-行上之該已編餘元組與存在該記錄暫存器中之該 位兀組的值，若所有位在同-行上之該已編程位元組與該記錄暫存器 中之該位元組的值相同，則發出一無干擾狀況（n〇n_disturb c〇nditi〇n) 訊號’並跳到步驟z ; r. 若沒有產生前述之無干擾狀況，狀_電流或行電颇f試一個有 限清單中之列電流與行電流組合； s. 檢查是輯有前述舰流與行糕德切已經嘗試過； t. 若無干擾狀I又有發生，且還未嘗試過所有該列電流與行電流之組 27 1300562Correcting the value of the group of all the remaining tuples on the same-line and the group of bits in the record register, if all the bits are on the same-row of the programmed byte If the value of the byte in the record register is the same, a non-interference condition (n〇n_disturb c〇nditi〇n) signal is issued and jumps to step z; r. if the aforementioned interference-free condition is not generated , the current or the line is quite a test of a combination of the current and the line current in a limited list; s. The inspection is a combination of the aforementioned ship and the line has been tried; t. If there is no interference, I have occurred And have not tried all of the column current and line current groups 27 1300562 修正本 合’則重複步驟e、f和g ; U.若無干擾狀況沒有發生，且已嘗試過所有前述之電流組合，則發出該 不良晶粒訊號；以及 Λ ζ•訊號程序（signalingprocess)結束。 12. -種不使用單晶片演算法產生器而使用外部測試裝置對磁性隨機存 取記憶體陣列進行編程、職與排序之可適性方法，其係包括下列步驟： a·編程並測試一記憶體陣列；The correction of the combination 'repeated steps e, f and g; U. If the interference-free condition does not occur, and all the aforementioned current combinations have been tried, the bad grain signal is issued; and the Λ 讯 signal process (signaling process) ends . 12. An adaptive method for programming, job and ordering magnetic random access memory arrays using an external test device without using a single-wafer algorithm generator, comprising the steps of: a. programming and testing a memory Array b.如果對該記憶體陣列之該編程與測試指出__良好晶粒，則發出—良 好之靜態隨機存取記憶體（SRAM)晶粒之訊號，並跳至步驟g; C·若對該記憶體_之該編程與測試指[不良晶粒，.出一失敗 訊號； d·對该記憶體陣列進行一次寫入之編程與測試； e·絲記鐘_之該—次寫人之雌與戦齡可通過，則發出一 良好之-次編程電子式可編程唯讀記憶體（〇TpEpR〇⑷晶粒訊號 並跳至步驟g; f·若對該記憶體陣列針對一次寫入的編程與測試失敗，則發出不良晶 粒訊號；以及 g·訊號程序（signalingpr〇cess)結束。 13·如申請專利範圍帛12項所述之不使用於晶片上之演算法產生器而使 用外部測試裝置對磁性隨機存取記憶體陣列進行編程、測試與排序之可 ^ 会其中δ亥對s己憶體陣列的編成與測試係包含下列步驟： 28 修正本 1300562 —9Z 5“ 〇….....一 a·設定一候選列電流； b·設定一候選行電流； c•寫入一輸入資料到一完整陣列中； d·從該完整陣列中讀取資料； e·對該讀取資料與該寫入之輸入資料進行比較； f.若該讀取資料與該寫入之輸入資料之比較結果為負面的，則發出一 不匹配錯誤訊號；b. If the programming and testing of the memory array indicates __good dies, issue a good SRAM grain signal and jump to step g; C. Memory_The programming and testing means [bad dies, a failure signal; d. programming and testing of a write to the memory array; e. silk clock _ the one-time female And the age can pass, then send a good-time programming electronic programmable read-only memory (〇TpEpR〇(4) die signal and jump to step g; f· if the memory array is programmed for one write If the test fails, a bad grain signal is issued; and the g·signal program (signalingpr〇cess) ends. 13. Use an external test device as described in claim 12, not using the algorithm generator on the wafer. Programming, testing, and sorting magnetic random access memory arrays can include the following steps: 28 Revision 1300562 - 9Z 5" 〇....... a. Set a candidate column current; b Setting a candidate row current; c• writing an input data to a complete array; d· reading data from the complete array; e· comparing the read data with the written input data; f. If the comparison result between the read data and the written input data is negative, a mismatch error signal is sent; §·若發生該不匹配錯誤訊號，則改變列電流或行電流以舊试一有限清 單中之列電流與行電流組合； h·檢查是否所有該列電流與行電流之組合皆已嘗試過； j·若有不匹配錯誤訊號發生，且還未嘗試過所有該列電流與行電流之組 合，則重複步驟c、d和e; k·若有不匹配錯誤訊號發生，且已嘗試過所有該列電流與行電流之組 合，則發出一不良晶粒訊號； 若沒有不匹配錯誤訊號，則固定該候選行電流與該候選列電流；以及 η.如果沒有不匹配錯誤的訊號，發出一個良好晶粒的訊號。 K 如申請專利範圍第12項所述之不使用於晶片上之演算法產生器而使 用外部測試裝置對磁性隨機存取記憶體陣列進行編程、測試與排序之可 適性方法，其中對該一次寫入對記憶體陣列進行的編成與測試係包含下 列步驟： a·將要被編程之位元組之陣列位址設定成一記憶體陣列之起始位址； 29 1300562 I——^» 修正本 b·編程並測試要被編程之該位元組； 則發出〜不良陣列訊 c•如果該編程與測試步驟中指出一不良晶粒 號，並跳至步驟h; d·比較該陣列位址與該記憶體陣列之最後位址； e·若該陣列位址與該記憶體陣列之該最後位址相等， .^ 、j發出一良好晶 粒訊號，並跳至步驟h; f·若該陣列位址與該記憶體陣列之該最後位址§·If the mismatch error signal occurs, change the column current or row current to test the current and row current combinations in the limited list; h• check if all combinations of current and row current have been tried; j. If there is a mismatch error signal, and have not tried all combinations of current and line currents, repeat steps c, d, and e; k. If there is a mismatch error signal, and all attempts have been made a combination of column current and row current sends a bad grain signal; if there is no mismatch error signal, the candidate row current is fixed to the candidate column current; and η. If there is no mismatched error signal, a good crystal is emitted. The signal of the grain. K is an applicability method for programming, testing, and ordering a magnetic random access memory array using an external test device as described in claim 12, which is not used on an on-wafer algorithm generator, wherein the write once The programming and testing of the memory array includes the following steps: a. Setting the array address of the byte to be programmed into the starting address of a memory array; 29 1300562 I——^» Amendment b· Program and test the byte to be programmed; then issue ~ Bad Array C. • If the programming and test steps indicate a bad die number, and jump to step h; d· Compare the array address with the memory The last address of the body array; e. If the array address is equal to the last address of the memory array, .^, j emit a good grain signal and jump to step h; f. if the array address The last address with the memory array 卜々曰寺，則將該陣列位 址增加； g·重複步驟b、c、d及e ;以及 h.訊號程序（signaiingprocess)結束。 15. -種使用於晶片上之演算法產生器對磁性隨機存取記憶體陣列進行 編程、測試與排序之可適性方法，其係包含下列步驟： a·編程並測試一記憶體陣列； b·若對該記憶體陣列之編程與測試指出一良好晶粒，則發出一良好靜 態隨機存取記憶體（SRAM)晶粒訊號，並跳至步驟g ; c·若對該記憶體陣列之編程與測試指出一不良晶粒，則發出一失敗訊 d. 對該記憶體陣列進行一次寫入之編程與測試； e. 若該記憶體陣列一次寫入的編程與測試顯示可通過，則發出一良好 一次編程電子式可編程唯讀記憶體（OTPEPROM)晶粒訊號，並跳 至步驟g ; 1300562Buh temple, the array address is increased; g· repeat steps b, c, d and e; and h. signaling (signaiing process) ends. 15. An adaptive method for programming, testing, and ordering a magnetic random access memory array using an algorithm generator on a wafer, comprising the steps of: a) programming and testing a memory array; b· If the memory array is programmed and tested to indicate a good die, a good static random access memory (SRAM) die signal is issued and jumps to step g; c. if the memory array is programmed The test indicates a bad die, then a failure message is sent. d. Write and test the memory array once; e. If the memory array writes once the programming and test display can pass, then a good Program the electronically programmable read-only memory (OTPEPROM) die signal once and jump to step g; 1300562 修正本 f·若該記憶體陣列一次寫入的編程與測試失敗， 則發出一不良晶粒訊 號；以及 g·訊號程序（signalingprocess)結束。 &如帽專利細第15項所述之使驗晶片上之演算法產生器對磁性 隨機存取記憶體陣列進行編程、測試與排序之可適性方法，其中對該圮 憶體陣列之編成與測試係包含下列步驟：Correction f. If the programming and test of the memory array one-time write fails, a bad grain signal is issued; and the g·signaling process ends. & an applicability method for programming, testing, and ordering a magnetic random access memory array by an algorithm generator on a wafer as described in the cap patent specification, wherein the editing of the memory array is performed The test system consists of the following steps: a.設定一候選列電流； b·設定一候選行電流； c.寫入一輸入資料到一完整陣列中； d·從該完整陣列中讀取資料； e.比較該讀取資料與寫入之該輸入資料； f·若該讀取資料與寫入之該資料之比較結果為負面的，則發出一不匹 配錯誤訊號； g·若發生該不匹配錯誤訊號，則改變列電流或行電流以嘗試一有限清 單中之列電流與行電流組合； h·檢查是否所有該列電流與行電流之組合都已經嘗試過； j·若有不匹配錯誤訊號發生，而且還未嘗試過所有該列電流與行電流之 組合，則重複步驟c、d和e; k·若有不匹配錯誤訊號發生，且已嘗試過所有該列電流與行電流之組 合，則發出一不良晶粒訊號； m•如果沒有不匹配錯誤訊號發生，則固定該候選行電流與該候選列電 31 1300562 流；以及 U n mmm 修正本 η·如果沒有不匹配錯誤訊號發生，則發出一良好晶粒訊號。 17.如申請專利範圍帛I5項所述之使用於晶片上之演算法產生器對磁性 隨機存取記憶體陣列進行編程、測試與排序之可適性方法，其中一次寫 入對该兄憶體陣列進行之編成與測試係包含下列步驟·· a.將要被編程之位元組之陣列位址設定成—記憶體陣列之起始位址； b_編程並測試該要被編程之位元組； C·如果該編程與測試指出-不良晶粒，則發出一不良陣列訊號，並跳 至步驟h ; d·比較該陣列位址與該記憶體陣列之最後位址； e·若該陣列位址與該記憶體陣列之該最後位址相等，則發出一良好晶 粒訊號，並跳至步驟h; f. 若該_健無記麵_之該最触科鱗，職該陣列位 址增加；a. setting a candidate column current; b) setting a candidate row current; c. writing an input data to a complete array; d) reading data from the complete array; e. comparing the read data with the write The input data; f. If the comparison result of the read data and the written data is negative, a mismatch error signal is issued; g. if the mismatch error signal occurs, the column current or the row current is changed. Try to combine the current and row current in a limited list; h· check if all combinations of current and line current have been tried; j. If there is a mismatch error signal, and have not tried all of the column The combination of current and line current repeats steps c, d and e; k. If a mismatch error signal occurs and all combinations of current and line current have been tried, a bad grain signal is emitted; m• If no mismatch error signal occurs, the candidate row current is fixed to the candidate column power 31 1300562; and the U n mmm correction table η is sent out if there is no mismatch error signal. number. 17. An adaptability method for programming, testing, and ordering a magnetic random access memory array using an algorithm generator on a wafer as described in the scope of claim 帛I5, wherein the write-once to the buddy array The programming and testing process includes the following steps: a. setting the array address of the byte to be programmed into the starting address of the memory array; b_ programming and testing the byte to be programmed; C. If the programming and testing indicate a bad die, issue a bad array signal and jump to step h; d· compare the array address with the last address of the memory array; e. if the array address And if the last address of the memory array is equal, a good grain signal is sent, and jumps to step h; f. if the most touched scale of the _jian no-face _, the array address is increased; g. 重複步驟b、c、d與e;以及 h·訊號程序（signaiingprocess)結束。 18· 一種磁性隨機存取記憶體（MRAM)電路，包含： 至少-記憶體子陣列，其係與複數位址暫存器與複數感應放大器相接； 至少一適當電流產生器； 至少一列驅動器（driver)，與該記憶體子陣列相接； 至少一行驅動器（driver)，與該記憶體子陣列相接； 32 修正本 以及 !300562 複數位址暫存器，其係與該記憶體子陣列相接 複數資料暫存器，其係與該記韻子陣列相接 複數位址多工器，其係與該記憶體子陣列相接 複數位址緩衝區，其係與複數位址多工器相接 複數感應放大器，其係與該記憶體子陣列相接 複數輸人輸丨緩舰⑽buffei>)，其倾觀子陣列相接g. Repeat steps b, c, d, and e; and end the h·signaling process. 18. A magnetic random access memory (MRAM) circuit comprising: at least a memory sub-array coupled to a complex address register and a complex sense amplifier; at least one suitable current generator; at least one column of drivers ( Driver), connected to the memory sub-array; at least one row of drivers connected to the memory sub-array; 32 revision and !300562 complex address register, which is associated with the memory sub-array a plurality of data registers are connected to the plurality of address multiplexers, and the plurality of address multiplexers are connected to the memory sub-array, and the plurality of address multiplexers are connected to the complex address multiplexer Connected to the plurality of sense amplifiers, which are connected to the memory sub-array and connected to the input and output sub-array (10) buffei>, and the sub-array is connected •如申请專利範圍帛I8項所述之磁性隨機存取記憶體電路，更包含一 演算法控制器。 20·如申請專利範圍第18項所述之磁性隨機存取記憶體電路，更包含： 複數位址輸入端，其係與該位址多工器相接； 複數雙向資料輸入端，其係與該記憶體子陣列相接； 曰曰片致能（chip enable)輸入端，其係與該演算法控制器相接； 一輸出致能（outputenable)輸入端，其係與該演算法控制器相接；以及 一控制輸入端，其係與該演算法控制器相接。 21·如申請專利範圍第18項所述之磁性隨機存取記憶體電路，其中該記 憶體子陣列係由複數列與行交叉點上之複數記憶胞中之一矩陣所組成。 22.如申請專利範圍第21項所述之磁性隨機存取記憶體電路，其中該交 叉點係為複數磁性記憶體儲存單元（magnetic memory storage cell)。 23·如申請專利範圍第21項所述之磁性隨機存取記憶體電路，其中該列 係為複數字元線。 24·如申請專利範圍第21項所述之磁性隨機存取記憶體電路，其中該行 33 1300562 厂------ 修正本 9兔|.1日懲正麵j 係為複數位元線。 25·如申請專利範圍第23項所述之磁性隨機存取記憶體電路，其中該字 元線係與該列驅動器相連。 26*如申請專利範圍第24項所述之磁性隨機存取記憶體電路，其中該位 元線係與該行驅動器相連。 27·如申請專利範圍第25項所述之磁性隨機存取記憶體電路，其中該列 驅動器與該行驅動器係透過該適當電流產生器驅動。• The magnetic random access memory circuit as described in the patent application 帛I8, further comprising an algorithm controller. 20. The magnetic random access memory circuit according to claim 18, further comprising: a complex address input terminal connected to the address multiplexer; a plurality of bidirectional data input terminals; The memory sub-array is connected; a chip enable input is connected to the algorithm controller; an output enableable input is associated with the algorithm controller And a control input coupled to the algorithm controller. The magnetic random access memory circuit of claim 18, wherein the memory sub-array is composed of a matrix of a plurality of memory cells at a complex column and a row intersection. 22. The magnetic random access memory circuit of claim 21, wherein the intersection is a plurality of magnetic memory storage cells. 23. The magnetic random access memory circuit of claim 21, wherein the column is a complex digital line. 24. The magnetic random access memory circuit according to claim 21, wherein the line 33 1300562 factory ------ amend the 9 rabbit |. 1 day penalty front j system is a complex bit line . The magnetic random access memory circuit of claim 23, wherein the word line is connected to the column driver. 26* The magnetic random access memory circuit of claim 24, wherein the bit line is connected to the row driver. The magnetic random access memory circuit of claim 25, wherein the column driver and the row driver are driven by the appropriate current generator. 28·如申請專利範圍第19項所述之磁性隨機存取記憶體電路，其中該演 算法控制器係控制該適當電流產生器。 29.如申請專利範圍第18項所述之磁性隨機存取記憶體電路，其中該位 址暫存器係存放將被存取之記憶胞的位址。 3〇·如申請專利範圍第18項所述之磁性隨機存取記憶體電路，其中該資 料暫存器係存放用來比較或寫回記憶胞的資料。 31·如申請專利範圍第18項所述之磁性隨機存取記憶體電路，其中該位 址緩衝區係由一外部之位址匯流排（bus)所驅動。 32.如申請專利範圍第18項所述之磁性隨機存取記憶體電路，其中該位 址多工器係由該位址緩衝區或該位址暫存器中選擇該記憶體子陣列之一 位址。 33·如申印專利域第ls項所述之磁性隨機存取記憶體電路，其中該感 應放大器翻於讀取存放在該記憶體子_巾的資料。 34·如申明專利辄圍第ls項所述之磁性隨機存取記憶體電路，其中該輪 34 1300562 修正本 入輸出緩衝區係被_外部之雙向資料紐排（㈣所驅動。 35·如申明專利範圍第2〇項所述之磁性隨機存取記憶體電路，其中該位 址輸入端係允許外部對於該記㈣子_的存取。 36·如申明專利範圍第2〇項所述之磁性隨機存取記憶體電路，其中該雙 向資料輸入端係用於讀寫該記憶體子陣列。 37·如申研專利範圍第μ項所述之磁性隨機存取記憶體電路，其中該晶 片致能輸人端係用以允許和禁止經過晶片之資料流。 _览如申明專利範圍帛2〇項所述之磁性隨機存取記憶體電路，其中該輸 出致能輸入端係用以允許和禁止雙向資料。 39·如申請專利範圍帛20項所述之磁性隨機存取記憶體電路，其中該控 制輸入端係可對該記憶體子陣列進行讀、寫與編程。 4〇· 一種對磁性隨機存取記憶體陣列中隨意的位元組進行編程與測試之 可適性方法，其係包含下列步驟·· a. 設定一候選列電流； b b.設定一候選行電流； c·儲存將被編程之位元組； d·讀取位在同-列上之所有已編程位元組，並儲存到一記錄暫存器 中； e·對將被編程之該位元組或是被干擾之位元組進行編程； f· 讀取將被編程之該位元組； g·比較該讀取的資料與寫入的資料； 35 1300562 !A± 日修正弩換頁丨 h.如果該讀取的資料與寫入的資料之比較結果為負 匹配錯誤訊號； 修正本 面的，則發出一不 k·若發生該秘配錯誤訊號，誠變舰流或行電流財試—有限清單 中之列電流與行電流組合； m.檢查是否所有該列電流與行電流之組合都已經嘗試過； η.若有不随錯舰紐生，而且翁#試過财該·雜行電流之 組合，則重複步驟e、f和g; • G.如綠秘配職峨社’此嘗試過所有制較贿電流之組 合，則發出一不良晶粒訊號； ρ·讀取所有該位在同一列上之已編程位元組； • q·比祕有_在同—行丨《已編餘元組與存在該記錄暫存器中之位 - 元組的值，如果所有該位在同一行上之已編程位元組與該記錄暫存器 中之A位元組的值相同’則發出一無干擾狀況（⑽仏出伽此c〇ncjiti〇n ) 之訊號，並跳到步驟z ; B r_若沒有產生該無干擾狀況，則改變列電流或行電流以嘗試一有限清單 中列電流與行電流之組合； s.檢查是否所有該列電流與行電流之組合都已經嘗試過； t·如果無干擾狀況沒有發生，而且還未嘗試過所有該列電流與行電流之 組合，則重複步驟e、f和g ; u.如果無干擾狀況沒有發生，且已嘗試過所有該列電流與行電流之組 合’則發出一不良晶粒訊號；以及 36 1300562 修正本 z.訊號程序（signalingProcess)結束。 41.如申請專利範圍第40項所述之對磁性隨機存取記憶體陣列中隨意位 元組進行編程與測試之可適性方法，其中該改變列電流與行電流之步 驟，乃是透過程式化可調適電流源來達成。 42·如申請專利範圍第40項所述之對磁性隨機存取記憶體陣列中隨音、位元 組進行編程與測試之可適性方法，其中該改變列電流與行電流之^驟兀 係用以嘗試該有限清單中之列電流與行電流組合，其作用在於列出不會 改變磁場方向、也不會無意地影響到共用同一字元線或同一位元線1 | 數磁性記憶胞之列電流與行電流組合。28. The magnetic random access memory circuit of claim 19, wherein the algorithm controller controls the appropriate current generator. 29. The magnetic random access memory circuit of claim 18, wherein the address register stores an address of a memory cell to be accessed. 3. The magnetic random access memory circuit of claim 18, wherein the data register stores data for comparing or writing back to the memory cell. 31. The magnetic random access memory circuit of claim 18, wherein the address buffer is driven by an external address bus. 32. The magnetic random access memory circuit of claim 18, wherein the address multiplexer selects one of the memory sub-arrays from the address buffer or the address register Address. 33. The magnetic random access memory circuit of claim 1, wherein the inductive amplifier is flipped over to read data stored in the memory. 34. The magnetic random access memory circuit according to the ls item of claim 301, wherein the round 34 1300562 modified input/output buffer is driven by the external bidirectional data line ((4). 35. The magnetic random access memory circuit of claim 2, wherein the address input terminal allows external access to the (4) sub_. 36. The magnetic property as recited in claim 2 a random access memory circuit, wherein the bidirectional data input terminal is used for reading and writing the memory sub-array. 37. The magnetic random access memory circuit according to the invention, wherein the wafer is enabled. The input end is used to allow and prohibit the flow of data through the chip. The magnetic random access memory circuit as described in claim 2, wherein the output enable input is used to allow and disable bidirectional 39. The magnetic random access memory circuit as claimed in claim 20, wherein the control input is capable of reading, writing and programming the memory sub-array. An adaptive method for programming and testing random bytes in a memory array, comprising the following steps: a. setting a candidate column current; b b. setting a candidate row current; c. storing will be programmed Bytes; d·read all programmed bytes in the same-column and store them in a record register; e· the byte to be programmed or the bit that is disturbed The group is programmed; f· reads the byte to be programmed; g· compares the read data with the written data; 35 1300562 !A± day correction 弩 page 丨h. If the data read and The comparison result of the written data is a negative matching error signal; if the original is corrected, a false signal is issued. If the secret error signal occurs, the change of the ship or the current test - the current and the line in the limited list Current combination; m. Check if all combinations of current and line current have been tried; η. If there is a fault with the ship, and Weng # tried the combination of the current and the current, repeat step e, f and g; • G. If the green secret is assigned to the company, this has tried all the system The combination of currents sends out a bad grain signal; ρ·reads all programmed bits of the bit in the same column; • q· is more secret than the same _ in the same line—“Edited tuple and exists The value of the bit-tuple in the record register, if all the bits of the programmed byte on the same line are the same as the value of the A-bit in the record register, then a non-interference condition is issued. ((10) Pull out the signal of gamma c〇ncjiti〇n) and jump to step z; B r_ If the interference-free condition is not generated, change the column current or row current to try a limited list of column currents and row currents Combination; s. check if all combinations of current and line current have been tried; t. If no interference occurs, and have not tried all combinations of current and line current, repeat step e, f and g; u. If no interference occurs, and all combinations of current and line current have been tried, a bad grain signal is sent; and 36 1300562 corrects the end of the z. signaling process. 41. An adaptability method for programming and testing a random byte in a magnetic random access memory array as described in claim 40, wherein the step of changing the column current and the row current is by stylized Adjustable current source to achieve. 42. An adaptability method for programming and testing sounds and bytes in a magnetic random access memory array as described in claim 40, wherein the method of changing column current and row current is used. In order to try the combination of the current and the line current in the limited list, the function is to list the direction of the magnetic field without changing, or inadvertently affect the same word line or the same bit line 1 | Current is combined with line current. 3737
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