JP2003007080A - Fuse circuit block - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a test cost by omitting a shifting process in which a chip on a wafer is shifted from a test device to a cutting device once to cut a fuse of a fuse circuit block in a conventional fuse circuit block. SOLUTION: This device is provided with two non-volatile storage elements 16, 18 storing data of connection or cut off of a fuse circuit, a circuit changing the direction of magnetization of this non-volatile storage elements 16, 18, and a current mirror circuit reading data stored in the non-volatile storage elements 16, 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat circuit block in which a fuse used in a semiconductor integrated circuit can be replaced with a circuit including a non-volatile memory element to obtain the same operation as fuse cutting. More specifically, the present invention relates to a fuse circuit block that replaces a defective memory cell with a redundant memory cell in a redundant circuit of a semiconductor memory.

[0002]

Fuse made of polysilicon or metal is
Widely used in the manufacture of semiconductor chips. Redundant circuits in memory chips are one of the most common applications of fuses. These fuses are also useful for adjusting timing and trimming parameters in analog and digital circuits of all other types of semiconductor chips.

In the conventional fuse cutting process in a semiconductor integrated circuit, since there is no method for surely electrically cutting the fuse, the fuse is mechanically cut by a laser beam or a fuse cutting device. Therefore, a separate device for blowing the fuse is required. Further, the fuse cutting process requires a three-step process including a process of detecting a defective cell, a process of cutting the fuse, and a process of checking that the fuse has been normally cut. The time required for such a process and the investment made in the test equipment and the fuse cutting equipment have a great influence on the total inspection cost.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a fuse circuit block which can electrically connect or disconnect a semiconductor element to a redundant circuit and can reduce the inspection cost of defective cells. To do.

[0005]

A fuse circuit block of the present invention is a nonvolatile memory element for storing data of connection or disconnection of a fuse circuit, a circuit for changing a magnetization direction of the nonvolatile memory element, and the nonvolatile memory element. And a current mirror circuit for reading the data stored in the nonvolatile memory element, and a fuse circuit block including the current mirror circuit.

[0006]

DETAILED DESCRIPTION OF THE INVENTION Embodiments will be described with reference to the drawings. FIG. 1 is a wiring diagram of a fuse circuit block according to the present invention. The fuse circuit block 10 includes a first nonvolatile memory element 16 and a second nonvolatile memory element 18,
A latch 14 for temporarily holding redundant data, a shift register 12 for sending redundant data to a nonvolatile storage element, a circuit for changing the direction of magnetization formed by four switching elements, and another four switching elements. And a current mirror circuit. A plurality of fuse circuit blocks 10 are provided on a word line or a bit line in one memory chip.

In FIG. 1, the first nonvolatile memory element 16
The second non-volatile memory element 18 and at least three layers of films (a free ferromagnetic layer whose magnetization direction can be changed, an insulating layer through which a tunnel current passes, and a fixed ferromagnetic layer whose magnetization direction is fixed).
It is composed of an MTJ element. 1st MT of FIG.
The directions indicated by the arrows of the J element 16 and the second MTJ element 18 indicate the directions of magnetization of the fixed ferromagnetic layers. In the present embodiment, the magnetization direction of the fixed ferromagnetic layer of the first MTJ element 16 and the magnetization direction of the fixed ferromagnetic layer of the second MTJ element 18 are opposite to each other. The fifth switching element 2 is provided between the first MTJ element 16 and the second MTJ element 18.
8 is connected. The fifth switching element 28 is composed of an n-type MOSFET. The write data line 42 is connected to the gate of the fifth switching element 28.

The shift register 12 has a shift data line 44 for inputting redundant data, and the shift register 12
Of the shift clock line 46 for controlling the input of the shift register 12 and the output of the shift register 12
And 8 are connected. The shift register is a circuit in which flip-flops are connected in multiple stages. Two output lines DL and DR are connected to the shift register 12. The redundant data is moved to the flip-flop in the subsequent stage by the clock signal input to the shift clock line 46. When a signal is input to the register enable line, redundant data is output to DL and DR. The latch 14 for temporarily holding redundant data is formed by combining two CMOSs. Two input lines LL and LR and a redundant data line 50 for outputting redundant data are connected to the latch 14. The other end of the redundant data line 50 is connected to the decoder.

The circuit for changing the direction of magnetization is composed of a first switching element 20, a second switching element 22, a third switching element 24 and a fourth switching element 26. These first to fourth switching elements 20, 22, 2
Reference numerals 4 and 26 are composed of n-type MOSFETs. The first switching element 20 and the fourth switching element 26 are connected in series. The input line LR of the latch 14 is connected between the first switching element 20 and the fourth switching element 26.

The second switching element 22 and the third switching element 24 are connected in series. The input line LL of the latch 14 is connected between the second switching element 22 and the third switching element 24.
First switching element 20 and second switching element 22
And are connected in parallel.

The gate of the first switching element 20 and the third
The gate of the switching element 24 is the shift register 12
Is connected to the output line DL. In addition, the gate of the second switching element 22 and the fourth switching element 26
Is connected to the output line DR of the shift register 12.

The current mirror circuit comprises a sixth switching element 30, a seventh switching element 32, an eighth switching element 34 and a ninth switching element 36.
The sixth switching element 30 is composed of an n-type MOSFET. In addition, the seventh switching element 32, the eighth switching element 34, and the ninth switching element 36 are p-type M
It is composed of OSFET.

The eighth switching element 34 and the ninth switching element 36 are connected in parallel. Seventh switching element 32 and eighth switching element 34 connected in parallel
The ninth switching element 36 and the sixth switching element 30 are connected in series.

The first MTJ element 16 is connected between the eighth switching element 34 and the sixth switching element 30. This connection line is also connected to a line connecting the first switching element 20 and the fourth switching element 26. The second MTJ element 18 is connected between the ninth switching element 36 and the sixth switching element 30. This connection line is also connected to a line connecting the second switching element 22 and the third switching element 24.

The gate of the seventh switching element 32 is connected to the redundant set P line 38. The gate of the sixth switching element 30 is connected to the redundant set N line 40. The gate of the eighth switching element 34 and the gate of the ninth switching element 36 are connected. The line connecting the gates is connected to the eighth switching element 34.

The fuse circuit block 10 shown in FIG.
In, the so-called “fuse blow” operation is performed by changing the magnetization direction of the free ferromagnetic layers of the first MTJ element 16 and the second MTJ element 18. Specifically, when the magnetization direction of the free ferromagnetic layer and the magnetization direction of the fixed ferromagnetic layer are the same, the resistance of the MTJ element decreases. On the contrary, when the magnetization direction of the free ferromagnetic layer is opposite to the magnetization direction of the fixed ferromagnetic layer, the resistance of the MTJ element increases. The voltage value applied to the current mirror circuit is controlled by utilizing the characteristics of the MTJ element. The input value of the latch 14 is determined by the controlled voltage value and is temporarily held in the latch 14 as redundant data.

The defective address data revealed by the inspection of the semiconductor memory cell is sent to the shift register 12 through the shift data line 44 by the clock of the shift clock line 46. While the defective address data is being read, the redundancy set P line 38 is set to "high" and the redundancy set N line 4 is set.
Set 0 to “low”. As a result, the seventh switching element 32 and the sixth switching element 30 are turned “OFF”. That is, no current flows in the current mirror circuit. This is to prevent erroneous data from being input to the latch 14.

During the writing of the defective address data, the output lines DL and DR of the shift register 12 are maintained at "low". As a result, no current flows in the circuit that changes the direction of magnetization, and the first MTJ element 16 and the second MTJ element
The magnetization direction of the J element 18 does not change.

When the writing of the redundant data to the shift register 12 is completed, a signal is passed through the register enable line 48 to enable the output of the shift register 12. At this time, either the output line DL or DR is “high” depending on the data written in the shift register 12.
become. At the same time, the write data line 42 is made “high”.
This turns the fifth switching element 28 "ON". As a result, the first MTJ element 16 and the second MTJ element 18 are connected.

For example, when the output line DL of the shift register 12 is "high" and DR is "low",
First switching element 20 and third switching element 24
Are turned on, and the second switching element 22 and the fourth
The switching element and "OFF". This allows
The current is the first switching element 20 and the first MTJ element 1
6, the fifth switching element 28, the second MTJ element 18,
It flows in order of the 3rd switching element 24. By forming this current path, the magnetization direction of the free ferromagnetic layer of the first MTJ element 16 becomes the same as the magnetization direction of the fixed ferromagnetic layer of the first MTJ element 16. In addition, the second MTJ element 18
The magnetization direction of the free ferromagnetic layer is opposite to the magnetization direction of the fixed ferromagnetic layer of the second MTJ element 18. That is, the first
The resistance of the MTJ element 16 decreases, and the second MTJ element 1
The resistance of 8 becomes large.

First MTJ element 16 and second MTJ element 18
When the direction of the magnetization is determined, the write data line 42 is set to "low". The fifth switching element 28 is “OF
It becomes "F". Then, the output lines DL and DR of the shift register 12 are set to "low". As a result, no current flows through the circuit that changes the magnetization direction, and the magnetization directions of the first MTJ element 16 and the second MTJ element 18 do not change. Next, the redundancy set P line 38 is set to "low" and the redundancy set N line 40 is set to "high". As a result, the seventh switching element 32 and the sixth switching element 30 are “ON”.
And a current flows through the current mirror circuit.

By the way, the first MTJ element 16 and the second MTJ element 18 connected to the current mirror circuit are the first
The MTJ element 16 has a small resistance, and the second MTJ element 18
Has great resistance. Therefore, due to the characteristics of the current mirror circuit in which currents of the same value flow through the eighth switching element 34 side and the ninth switching element 36 side, the eighth switching element 34 side
The potential of the ninth switching element 36 side is higher than that of the side thereof. Therefore, the input line LL of the latch 14 is "high".
And LR becomes “low”. This data becomes redundant data, and the latch 14 temporarily holds this redundant data. The combination of the potentials of LL and LR of the latch 14 determines connection / disconnection to the redundant memory block.

Conventionally, the redundant circuit block has been constructed by cutting a metal fuse. However, in the present embodiment, the first MTJ element 16 and the second MTJ element 18
By adopting the method of controlling the magnetic field direction of
The same effect as blowing the fuse can be obtained.

In this embodiment, the output line DL of the shift register 12 is described as "high" and DR as "low". However, conversely DL is “low” and DR is “high”.
It is possible to set LL, which is the input line of the latch 14, to “low” and LR to “high”. In the present embodiment, the magnetization directions of the fixed ferromagnetic layers of the first MTJ element 16 and the second MTJ element 18 are oriented in the direction of the fifth switching element 28, but the magnetization directions are mutually oriented in the fifth switching element 28. May face in opposite directions.

In the present embodiment, a circuit using a non-volatile memory element is substituted for the fuse cutting operation of the redundant circuit, but the fuse circuit block using this non-volatile memory element is not limited to this case. is not. It can also be used in other applications that have the same function as redundant circuits using polysilicon fuses and metal fuses.
For example, it can be used in a timing tuning circuit and a parameter trimming circuit using a polysilicon fuse and a metal fuse.

Further, although the MTJ element is taken up as the nonvolatile memory element in the present embodiment, it is not limited to this particular device. GM, which is a kind of magnetic memory element
MRAM using R (Giant Magnetoresistive) element
(Magnetic RAM) and any element such as a FeRAM (Ferro electric RAM) cell or a flash memory cell may have the same function, although the detailed circuit design varies from case to case.

[0027]

The fuse circuit block of the present invention uses a circuit block composed of a non-volatile storage element instead of a metal fuse. As a result, the defective cell address can be transferred to the redundant circuit in the process of detecting the defective cell, so that the wafer need not be moved to the fuse cutting device. Therefore,
The cost and the number of manufacturing steps for the fuse cutting device can be reduced.

A further advantage is the flexibility in circuit design. Conventionally, when the fuse is cut, the fuse cannot be reconnected to the original circuit. But,
In the case of the present invention, the so-called fuse can be returned to the original state by changing the magnetization direction of the nonvolatile memory element. Therefore, by replacing the conventional fuse circuit block used for the timing adjustment of the semiconductor element circuit and the trimming of the parameter with the fuse circuit block of the present invention, the semiconductor element circuit can be more flexible such as trial and error and fine adjustment. It becomes possible to give a function.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a fuse circuit block in a redundant circuit of the present invention.

[Explanation of symbols]

10: Fuse circuit block 12: Shift register 14: Latch 16: First MTJ element 18: Second MTJ element 20: First switching element 22: Second switching element 24: Third switching element 26: Fourth switching element 28: Fifth switching element 30: Sixth switching element 32: Seventh switching element 34: Eighth switching element 36: 9th switching element 38: Redundant set P line 40: Redundant set N line 42: write data line 44: shift data line 46: Shift clock line 48: Register enable line 50: Redundant data line

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshio Sunaga             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Hisadamu Miyatake             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Tsuneji Kitamura             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Hideo Asano             1 Kirihara Town, Fujisawa City, Kanagawa Japan Eye             BM Corporation Fujisawa Office F-term (reference) 5F038 AV03 AV10 AV13 AV15 DF01                       DF05 EZ20                 5F064 BB12 FF24 FF27 FF30 FF32                       FF42 FF45                 5L106 CC09 CC13

Claims (12)

[Claims] 1. A non-volatile memory element for storing data of connection or disconnection of a fuse circuit, a circuit for changing the direction of magnetization of the non-volatile memory element, and a current mirror for reading data stored in the non-volatile memory element. And a fuse circuit block including a circuit. 2. The fuse circuit block according to claim 1, further comprising: a shift register that sends the connection or disconnection data to the nonvolatile memory element, and a latch that temporarily holds the connection or disconnection data. 3. The fuse circuit block according to claim 1, wherein the nonvolatile memory element includes at least a ferromagnetic layer whose magnetization direction changes and a ferromagnetic layer whose magnetization direction is fixed. . 4. The fuse circuit block according to claim 3, wherein the circuit that changes the direction of magnetization of the nonvolatile memory element is configured by a switching element. 5. The non-volatile storage element is two, and one of the non-volatile storage elements has a magnetization direction of a ferromagnetic layer whose magnetization direction changes and a magnetization direction of a ferromagnetic layer whose magnetization direction is fixed. Are in the same direction, and the other nonvolatile memory element is
5. The fuse circuit block according to claim 1, wherein the direction of magnetization of the ferromagnetic layer whose magnetization direction is changed is opposite to the direction of magnetization of the ferromagnetic layer whose magnetization direction is fixed. 6. The fuse circuit block according to claim 5, wherein the two nonvolatile memory elements are connected via a switching element. 7. The fuse according to claim 6, wherein the magnetization directions of the ferromagnetic layers of the two non-volatile memory elements whose magnetization directions are fixed are directions facing each other or directions facing each other. Circuit block. 8. The two switching elements having different input signals are connected to each other via the two nonvolatile memory elements and a switching element that connects the two nonvolatile memory elements. Fuse circuit block. 9. The fuse circuit block according to claim 1, further comprising a current mirror circuit that generates a differential signal according to resistance values of the two nonvolatile memory elements. 10. The non-volatile storage element is an MTJ (Magnet).
The fuse circuit block according to claim 1, which is an etic tunnel junction) element. 11. The switching element is a MOSFET
The fuse circuit block according to claim 3, which is 12. The fuse circuit block according to claim 2, further comprising a circuit for timing adjustment or parameter trimming, which is connected to the latch circuit.