JP6261041B2 - Nonvolatile content addressable memory cell and nonvolatile content addressable memory - Google Patents

Description

  The present invention relates to a nonvolatile content addressable memory cell and a nonvolatile content addressable memory.

  As a dedicated hardware engine that realizes pattern matching technology, which is one of the important technologies that support the modern network society, a method of using content-addressable memory (CAM) is known. As a representative example of this associative memory, a ternary content-addressable memory (TCAM) has attracted attention.

  Since TCAM can search stored data and input data in parallel, a very high-speed search is possible. The TCAM implements a mask search function by defining three storage states “Don't-care (X)” in addition to the usual “0” and “1”. As described above, the TCAM having both high speed and flexibility of search can be applied to various fields such as network routers, virus search, image / voice recognition, and the like.

  On the other hand, with the extreme miniaturization of transistors, in recent integrated circuits, an increase in power consumed by leakage current during standby, that is, standby power, has become serious. Such standby power can be reduced by temporarily shutting off the power of the circuit block in the non-operating state. However, when the TCAM uses a volatile logic circuit based on SRAM (Static Random Access Memory) or the like as an integrated circuit, all the storage states held in the circuit are lost.

  In order to solve such a problem, development of a nonvolatile TCAM that holds stored data in a nonvolatile device (nonvolatile memory) is in progress. Among nonvolatile memories, in particular, a memory using a magnetic tunnel junction element (Magnetic Tunnel Junction element: MTJ element), which is a kind of spintronic element and is a resistance change type storage element, has high rewrite resistance and CMOS (Complementary Metal). -Oxide Semiconductor) It is considered promising from the viewpoints of affinity, three-dimensional integration, and the like.

  As illustrated in FIGS. 1A and 1B, the MTJ element MTJ includes a free layer FR, a fixed layer FI, and a tunnel barrier TB.

The tunnel barrier TB is made of an insulating thin film such as MgO or Al ₂ O ₃ . The free layer FR and the fixed layer FI are made of a ferromagnetic material such as iron, cobalt, and alloys thereof. The free layer FR is provided with an upper electrode terminal TE, and the fixed layer FI is provided with a lower electrode terminal BE. While the magnetization direction of the free layer FR changes according to the direction of the current flowing through the MTJ element MTJ, the magnetization direction of the fixed layer FI does not change.

  As shown in FIG. 1A, when the magnetization direction of the free layer FR and the direction of the fixed layer FI are the same (parallel), the MTJ element MTJ is in a low electrical resistance state (low resistance state). On the other hand, as shown in FIG. 1B, when the magnetization direction of the free layer FR and the direction of the fixed layer FI are opposite (antiparallel), the MTJ element MTJ has a high electric resistance (high resistance state). Take. 1A and 1B, the magnetization directions of the free layer FR and the fixed layer FI are indicated by broken line arrows.

  By supplying an appropriate current to the MTJ element MTJ, the MTJ element MTJ can be in a desired state of the low resistance state or the high resistance state.

  When the current Imtj from the free layer FR to the fixed layer FI is supplied when the MTJ element MTJ is in the high resistance state shown in FIG. 1B, the MTJ element MTJ becomes low as shown in FIG. Transition to the resistance state. If the current Imtj is supplied when the MTJ element MTJ is in the low resistance state, the low resistance state is maintained.

  On the other hand, when the current −Imtj from the fixed layer FI to the free layer FR is supplied when the MTJ element MTJ is in the low resistance state shown in FIG. 1A, the MTJ element MTJ becomes as shown in FIG. Then, a transition is made to the high resistance state. Note that if the current −Imtj is supplied when the MTJ element MTJ is in the high resistance state, the high resistance state is maintained.

  Therefore, the MTJ element MTJ can be regarded as a variable resistor as shown in FIG.

  By associating the high resistance state of the MTJ element MTJ with one of the logical values “0” or “1” and the low resistance state with the other, the MTJ element MTJ can function as a storage element. Since the RI characteristic of the MTJ element MTJ has hysteresis as shown in FIG. 2, the low resistance state and the high resistance state of the MTJ element MTJ are maintained even if the supply of current to the MTJ element MTJ is cut off. . Therefore, the MTJ element MTJ functions as a nonvolatile memory element. In FIG. 2, Rp represents the electrical resistance value of the MTJ element MTJ in the low resistance state, and Rap represents the electrical resistance value in the high resistance state.

  In addition, the MTJ element MTJ can also function as a switching element by associating the low resistance state of the MTJ element MTJ with the on state and the high resistance state with the off state.

  As a TCAM cell circuit using such an MTJ element, Non-Patent Documents 1 to 6 disclose a cell circuit having a configuration including a transistor and an MTJ element. Non-Patent Document 1 discloses a 2T (two transistors) -2MTJ (two MTJ elements) configuration. Non-Patent Document 2 discloses a 6T-2MTJ configuration. Non-Patent Document 3 discloses a 4T-2MTJ configuration, Non-Patent Document 4 discloses a 9T-2MTJ configuration, Non-Patent Document 5 discloses a 7T-2MTJ configuration, and Non-Patent Document 6 discloses an 11T-3MTJ configuration. Has been.

  FIG. 3A shows the configuration of the TCAM cell CC ′ of Non-Patent Document 2.

  When writing data to the TCAM cell CC ′, the write transistors M5 and M6 are turned on by supplying a voltage to the gates (control terminals) of the write transistors M5 and M6 via the word line WL. Thereafter, data is written to the MTJ elements MTJ1 and MTJ2 using the bit lines BL1 and BL2 while the write transistors M5 and M6 are kept on. The written data is stored in the MTJ elements MTJ1 and MTJ2 in a nonvolatile manner as a low resistance state or a high resistance state. The TCAM cell CC ′ includes two MTJ elements MTJ1 and MTJ2 each capable of storing binary data associated with a high resistance state and a low resistance state, and includes “0”, “1”, “X (Don 't-care)' has three storage states.

During the search operation, the resistance value of the comparison logic circuit 10 indicating the stored data, fixed loading LO is converted into an output voltage V _CO by a current I _LOAD is supplied is detected as the potential of the match line ML. When the stored data matches the input data and when “X (Don't-Care)” is stored (HIT), the match line ML that has been precharged up to the power supply voltage in advance is the high output voltage V _CO−. Discharge to _H. On the other hand, if the stored data and the input data do not match (MISS), the match line ML precharged up to the power supply voltage is discharged to the low output voltage V _CO-M . In this way, the search result in the TCAM word circuit composed of the individual TCAM cells CC ′ and the plurality of TCAM cells CC ′ connected to the common match line ML is output to the outside as the potential of the match line ML. The

As shown in FIG. 3B, the high output voltage V _CO-H that is the output voltage V _CO when the stored data and the input data match (HIT) is the intersection of the current curve I _HIT and the load current curve I _LOAD . Determined by. On the other hand, as shown in FIG. 3B, the low output voltage V _CO-M that is the output voltage V _CO in the case where the stored data and the input data do not match (MISS) is, as shown in FIG. 3B, the current curve I _MISS and the load current curve I _LOAD. Is determined by the intersection of

S. Matsunaga, et al. , “Implementation of a Perpendicular MTJ-Based Read-Disturb-Tolerant 2T-2R Nonvolatile TCAM Based on a Reversed Current Reading Scheme”, Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 475-476, Jan. 2012 S. Matsunaga, et al. , "Fabrication of a 99% -Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierachical Power Gating for a Massively-Parallel Full-Text-Search Engine", IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 106-107, 2013 S. Matsunaga, et al. , “A 3.14 μm 2 4T-2MTJ-Cell Fully Parallel TCAM Based on Nonvolatile Login-in-Memory Architecture, IEEE Symposium on VLSI Circuits. 44-45, 2012 S. Matsunaga, et al. , “Design of Nine-Transistor / Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatility Persistent Content-Addressable Memory.”, Japan. 51, no. 2, pp. 02BM06-1 to 02BM06-5, Feb. 2012 S. Matsunaga, et al. "Design of a 270ps-Access 7T-2MTJ-Cell Nonvolatile Ternary Content-Addressable Memory", Journal of Applied Physics (JAP), vol. 111, no. 7, pp. 07E336-1 to 07E336-3, 2012 W. Xu, et al. , “Design of Spin-Torque Transfer Magnet RAM and CAM / TCAM with High Sensing and Search Speed Vs., IEEE Transactions Vs. 18, no. 1, pp. 66-74, 2010

Since the resistance value and magnetoresistance ratio (resistance change rate) of the current MTJ element are small, the resistance difference (the difference between the resistance value in the high resistance state and the resistance value in the low resistance state) of the MTJ element is the on / off state of the transistor. Small compared to resistance difference. For this reason, in a word circuit composed of a TCAM cell CC ′ using an MTJ element and a plurality of TCAM cells CC ′, the output voltage amplitude ΔV _CO (high output voltage V _CO-H and low output voltage V of the match line ML). the difference between the _CO-M) is small, to retrieve the matching-mismatch comparison operation results of determination successfully, it is difficult in comparison with the configured TCAM by a general transistor.

In particular, in a minute semiconductor manufacturing process of the nanometer generation, the output of the match line ML described above is affected by variations in threshold voltage of transistors and variations in resistance values of variable resistance nonvolatile memory elements such as MTJ elements. the operating margin of the TCAM cell CC 'and a word circuit corresponding to the voltage amplitude [Delta] V _CO is attenuated. For this reason, a defective word circuit in which the comparison result of coincidence / non-coincidence cannot be determined normally occurs, and it is necessary to prepare an extra word circuit to replace it. In addition, high-sensitivity sensing is indispensable, complicating a complicated circuit configuration, and preventing a reduction in chip area.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-volatile associative memory cell and a non-volatile associative memory which have a large output voltage amplitude and can be written in parallel.

In order to achieve the above object, a nonvolatile content addressable memory cell according to a first aspect of the present invention provides:
A first transistor having one end connected to a predetermined connection point and a control end connected to a first search line;
A second transistor having one end connected to the predetermined connection point and a control end connected to a second search line;
A third transistor having one end connected to the predetermined connection point and a control end connected to the second search line;
A fourth transistor having one end connected to the predetermined connection point and a control end connected to the first search line;
A first resistance change type storage element disposed between the other end of the first transistor and a second plate line;
A second resistance change type storage element disposed between the other end of the second transistor and the second plate line;
A third resistance change type storage element disposed between the other end of the third transistor and the first plate line;
A fourth resistance change type storage element disposed between the other end of the fourth transistor and the first plate line;
It is characterized by providing.

Preferably, the nonvolatile content addressable memory cell is
The first transistor and the second transistor are first conductivity type field effect transistors,
The third transistor and the fourth transistor are field effect transistors of a second conductivity type opposite to the first conductivity type.
It is characterized by that.

Preferably, the nonvolatile content addressable memory cell is
Each of the first, second, third, and fourth resistance change memory elements includes a lower electrode terminal and an upper electrode terminal;
The lower electrode terminal of the first resistance change type storage element is connected to the other end of the first transistor;
The lower electrode terminal of the second resistance change type storage element is connected to the other end of the second transistor;
The lower electrode terminal of the third resistance change type storage element is connected to the other end of the third transistor;
The lower electrode terminal of the fourth resistance change type storage element is connected to the other end of the fourth transistor;
It is characterized by that.

Preferably, the nonvolatile content addressable memory cell is
The semiconductor device further includes a fifth transistor having one end connected to the predetermined connection point and the other end connected to a match line.

Preferably, the nonvolatile content addressable memory cell is
The first search line is shared with a first bit line that transmits a control signal to the control terminal of the first transistor and writes data to the first resistance change type storage element.
The second search line is shared with a second bit line that transmits a control signal to the control terminal of the second transistor and writes data to the second resistance change storage element.
It is characterized by that.

The nonvolatile content addressable memory according to the second aspect of the present invention is:
A plurality of nonvolatile content addressable memory cells each sharing the first plate line and the second plate line,
The first potential is supplied by alternately switching a high potential and a low potential to the first plate line during a data write operation to the first resistance change type storage element and the second resistance change type storage element. A plate wire driver,
In the write operation, when the first plate line driver supplies a high potential to the first plate line, a low potential is supplied to the second plate line, and the first plate line driver When a low potential is supplied to the first plate line, a high potential and a low potential are alternately switched to the second plate line so that a high potential is supplied to the second plate line. A second plate line driver to supply;
It is characterized by providing.

Preferably, the non-volatile content addressable memory is
The first plate line driver functions as the power line in the search operation of data written in the first resistance change type storage element and the second resistance change type storage element. Let
The second plate line driver causes the second plate line to function as a ground line during the search operation.
It is characterized by that.

  According to the present invention, it is possible to provide a non-volatile associative memory cell and a non-volatile associative memory having a large output voltage amplitude and capable of being written in parallel and compact.

(A) is a figure which shows the MTJ element in a low resistance state. (B) is a figure which shows the MTJ element in a high resistance state. (C) is a figure which shows the variable resistance equivalent to an MTJ element. It is a figure which shows the RI characteristic of an MTJ element. (A) is a figure which shows the structure of the TCAM memory cell disclosed by the nonpatent literature 2. FIG. (B) is a figure which shows the output voltage amplitude of the TCAM memory cell disclosed by the nonpatent literature 2. FIG. It is a figure which illustrates the whole structure of TCAM provided with the TCAM cell which concerns on embodiment. It is a figure which illustrates the structure of the TCAM cell which concerns on embodiment. (A) is a timing chart showing an operation of writing data to the TCAM cell according to the embodiment. FIG. 5B is a diagram illustrating an operation during a write operation of the TCAM cell according to the embodiment. It is a figure for demonstrating the operation | movement which writes other data in the TCAM cell which concerns on embodiment. (A) is a timing chart, (b) is a diagram showing the operation of the circuit. It is a truth table of the TCAM cell which concerns on embodiment. It is a figure which shows the output voltage amplitude of the TCAM cell which concerns on embodiment. (A) is a figure which shows the simulation waveform at the time of performing 72-bit parallel search operation | movement in the word circuit using the conventional 6T-2MTJ type TCAM cell. (B) is a diagram showing a simulation waveform when a 72-bit parallel search operation is performed in the word circuit using the 5T-4MTJ type TCAM cell according to the embodiment.

  Hereinafter, a nonvolatile content addressable memory cell and a nonvolatile content addressable memory according to the present invention will be described in detail with reference to the drawings.

(Embodiment)
FIG. 4 shows the overall configuration of a word parallel / bit parallel type (fully parallel type) TCAM 100 as a TCAM including the nonvolatile content addressable memory cell according to the embodiment. As shown in FIG. 4, the TCAM 100 includes word circuits WC1 to WCn, a bit line driver BD, a search line driver SD, a word line driver WD, a plate line driver PD, and an output driver OD.

  The word circuits WC1 to WCn store data input to the TCAM 100 from the outside. Further, the word circuits WC1 to WCn determine whether or not the search data input from the outside to the TCAM 100 matches the data stored in each word circuit.

  The word circuits WC1 to WCn include a plurality of TCAM cells CC arranged in an array, match lines ML1 to MLn to which these TCAM cells CC are connected, and sense amplifiers SA1 to SAn.

  Hereinafter, when all the word circuits WC1 to WCn are pointed out and when an unspecified word circuit is pointed out, it is expressed as a word circuit WC. Similarly, the match lines ML1 to MLn and the sense amplifiers SA1 to SAn are also denoted as the match line ML and the sense amplifier SA, respectively, unless they are distinguished from each other.

  Each TCAM cell CC stores 1-bit data among multi-bit data stored in the word circuit WC including each TCAM cell CC. Further, the TCAM cell CC determines whether the stored data matches the search data. That is, in each TCAM cell CC, whether or not the data stored in each word circuit WC matches the search data is determined on a bit basis.

  The result of the match determination by the word circuit WC is sent to the corresponding sense amplifier SA as the voltage of the corresponding match line ML. The sense amplifier SA amplifies the received output of the match line ML and sends it to the output driver OD.

  The bit line driver BD, the word line driver WD, and the plate line driver PD write data input from the outside to the TCAM 100 in each TCAM cell CC of the word circuit WC.

  The bit line driver BD is connected to each TCAM cell CC via the bit lines BL1_1, BL2_1,..., BL1_m, BL2_m. The word line driver WD is connected to the plate line driver PD via the word lines WL1 to WLn. The plate line driver PD is connected to the corresponding word circuit WC via the plate lines PL1_1, PL2_1,..., PL1_n, PL2_n. Hereinafter, when not distinguishing each of the bit lines BL1_1, BL2_1,..., BL1_m, BL2_m, word lines WL1 to WLn, and plate lines PL1_1, PL2_1,. Indicated as WL, plate lines PL1, PL2.

During the write operation, the word line driver WD identifies the plate line driver PD used for writing by decoding the row address input to the TCAM 100 from the outside. In addition, the bit line driver BD decodes a column address input to the TCAM 100 from the outside, and specifies bit lines BL1 and BL2 used for writing. Data input from the outside to the TCAM 100 activates the plate line driver PD to be written from the word line driver WD via the word line WL, and the TCAM cell CC from the plate line driver PD via the plate lines PL1 and PL2. Is written by passing a current through Further, data input from the outside to the TCAM 100 is written from the bit line driver BD to the TCAM cell CC via the bit lines BL1 and BL2.
Note that data write operations by the word line driver WD, the bit line driver BD, and the plate line driver PD will be described later in detail.

  The search line driver SD inputs search data input from the outside to the TCAM 100 to each TCAM cell CC of the word circuit WC.

  The search line driver SD is connected to each TCAM cell CC via search lines SL1, / SL1,..., SLm, / SLm. Hereinafter, the search lines SL1, / SL1,..., SLm, / SLm will be referred to as the search lines SL, / SL when not distinguished from each other. The symbol “/” represents logical inversion.

  During the search operation, the search line driver SD inputs the search data received from the outside to each TCAM cell CC via the first search line / SL and the second search line SL. The search data / S input to the corresponding first search line / SL and the search data S input via the second search line SL are in a complementary relationship. That is, when one of the logical values “1” or “0” is input by the first search line / SL, the other is input by the corresponding second search line SL.

  The output driver OD outputs the determination result of matching / mismatching between the search data and the stored data performed by each word circuit WC to the outside of the TCAM 100.

  Next, the configuration and operation of the TCAM cell CC will be described in detail.

  As shown in FIG. 5, the TCAM cell CC includes five transistors M1 to M3, M1 ′, and M2 ′, and four MTJ elements MTJ1, MTJ2, MTJ1 ′, and MTJ2 ′ serving as resistance change type storage elements. These are 5T-4MTJ type nonvolatile associative memory cells.

  The TCAM cell CC includes a comparison logic circuit 10, a complementary logic circuit 20, and a transistor M3 that functions as a diode switch.

  The comparison logic circuit 10 includes first and second transistors M1 and M2 and first and second MTJ elements MTJ1 and MTJ2 as resistance change type storage elements.

  The transistors M1 and M2 are first conductivity type field effect transistors. Specifically, the transistors M1 and M2 are N-type MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).

  The drain of the first transistor M1 (one end of the current path) is connected to the output line OL of the comparison logic circuit 10 as a predetermined connection point. The source of the first transistor M1 (the other end of the current path) is connected to the lower electrode terminal BE provided in the fixed layer FI of the first MTJ element MTJ1. The gate (control end) of the first transistor M1 is connected to the first bit line BL1 and the first search line / SL.

  The drain of the second transistor M2 is connected to the output line OL. The source of the second transistor M2 is connected to the lower electrode terminal BE provided in the fixed layer FI of the second MTJ element MTJ2. The gate of the second transistor M2 is connected to the second bit line BL2 and the second search line SL.

  As shown in FIG. 1, each of the two MTJ elements MTJ1 and MTJ2 includes a free layer FR whose magnetization direction is not fixed and a fixed layer FI whose magnetization direction is fixed. The high resistance state and the low resistance state are transitioned according to the combination of the magnetization direction and the magnetization direction of the fixed layer FI. Specifically, when the direction of magnetization of the free layer FR and the direction of the fixed layer FI are the same (parallel), a low resistance state is taken, and when it is opposite (antiparallel), a high resistance state is taken.

  The lower electrode terminal BE provided in the fixed layer FI of the first MTJ element MTJ1 is connected to the output line OL via the first transistor M1. The upper electrode terminal TE provided in the free layer FR of the first MTJ element MTJ1 is connected to the second plate line PL2 and the ground line GND.

  The lower electrode terminal BE provided in the fixed layer FI of the second MTJ element MTJ2 is connected to the output line OL via the second transistor M2. The upper electrode terminal TE provided in the free layer FR of the second MTJ element MTJ2 is connected to the second plate line PL2 and the ground line GND.

  The complementary logic circuit 20 includes third and fourth transistors M1 'and M2' and third and fourth MTJ elements MTJ1 'and MTJ2' as resistance change type storage elements.

  The third and fourth transistors M1 'and M2' are field effect transistors of the second conductivity type having the opposite conductivity type to the first and second transistors M1 and M2. Specifically, the third and fourth transistors M1 'and M2' are P-type MOSFETs.

  The drain of the third transistor M1 'is connected to the output line OL. The source of the third transistor M1 'is connected to the lower electrode terminal BE provided in the fixed layer FI of the third MTJ element MTJ1'. The gate of the third transistor M1 'is connected to the second bit line BL2 and the second search line SL.

  The drain of the fourth transistor M2 'is connected to the output line OL. The source of the fourth transistor M2 'is connected to the lower electrode terminal BE provided in the fixed layer FI of the fourth MTJ element MTJ2'. The gate of the fourth transistor M2 'is connected to the first bit line BL1 and the first search line / SL.

  As shown in FIG. 1, each of the two MTJ elements MTJ1 ′ and MTJ2 ′ includes a free layer FR whose magnetization direction is not fixed and a fixed layer FI whose magnetization direction is fixed. The high resistance state and the low resistance state are transitioned according to the combination of the magnetization direction of the FR and the magnetization direction of the fixed layer FI. Specifically, when the direction of magnetization of the free layer FR and the direction of the fixed layer FI are the same (parallel), a low resistance state is taken, and when it is opposite (antiparallel), a high resistance state is taken.

The lower electrode terminal BE provided in the fixed layer FI of the third MTJ element MTJ1 ′ is connected to the output line OL via the third transistor M1 ′. The upper electrode terminal TE provided in the free layer FR of the third MTJ element MTJ1 ′ is connected to the first plate line PL1 and the power supply line V _DD .

The lower electrode terminal BE provided in the fixed layer FI of the fourth MTJ element MTJ2 ′ is connected to the output line OL via the third transistor M2 ′. The upper electrode terminal TE provided in the free layer FR of the fourth MTJ element MTJ2 ′ is connected to the first plate line PL1 and the power supply line V _DD .

  The transistor M3 that is the fifth transistor is, for example, an N-type MOSFET. The drain and gate of the transistor M3 are both connected to the match line ML, and the source is connected to the output line OL.

The transistor M3 functions as a diode switch. Specifically, the potential of the match line ML, that is, when the potential of the drain and the gate is higher than the output voltage V _CO of TCAM cell CC, transistor M3 is turned on, a current flows. When the potential of the match line ML is less than or equal to the output voltage _{V CO} of TCAM cell CC, transistor M3 is turned off, the discharge path from the match line ML is cut off.

In order to realize a compact cell configuration in the TCAM cell CC, the first search line / SL transmits a control signal to the gate of the first transistor M1 and writes data to the first MTJ element MTJ1. It is shared with the first bit line BL1. Specifically, one wiring provided in the vertical direction functions as the first bit line BL1 during the write operation, and functions as the first search line / SL during the search operation. Similarly, the second search line SL is shared with the second bit line BL2 that transmits a control signal to the gate of the second transistor M2 and writes data to the second MTJ element MTJ2. Furthermore, the first plate line PL1 (during write operation) and the power supply line V _DD (during search operation), the second plate line PL2 (during write operation) and the ground line GND (during search operation) are the same wiring. It is realized by.

  That is, the four transistors M1, M2, M1 ', and M2' function as both a write operation transistor and a search operation transistor. With such a configuration, the TCAM cell CC can perform data writing and retrieval with a smaller number of transistors than the conventional TCAM cell CC ′ shown in FIG. 3A, for example.

  The operation of the TCAM cell CC having the above configuration will be described in detail. First, a data write operation to the TCAM cell CC will be described. Data is written to the MTJ elements MTJ1, MTJ2, MTJ1 ', and MTJ2' included in the TCAM cell CC by using a bit parallel writing method called phase selective parallel writing.

  When the high voltage H is supplied to the word line WL and the low voltage L is supplied as the search permission signal SE, the TCAM cell CC shifts to the write phase. As shown in the timing chart of FIG. 6A, the write phase includes a “0” write phase and a “1” write phase. The “0” write phase and the “1” write phase are switched according to the voltage signal supplied to the first and second plate lines PL1 and PL2.

  The first plate line PL1 is supplied with a voltage signal by the first plate line driver PD1 provided in the plate line driver PD, and the second plate line PL2 is supplied with a voltage signal by the second plate line driver PD2 provided in the plate line driver PD. Supplied. The voltage signal supplied to the first plate line PL1 and the voltage signal supplied to the second plate line PL2 are in a complementary relationship. The first plate line driver PD1 alternately supplies a high potential and a low potential to the first plate line PL1, and the second plate line driver PD2 supplies the first plate line driver PD1 to the first plate line driver PD1. When a high potential is supplied to the plate line PL1, a low potential is supplied to the second plate line PL2, and when the first plate line driver PD1 is supplying a low potential to the first plate line PL1, In order to supply a high potential to the second plate line PL2, a high potential and a low potential are alternately switched and supplied to the second plate line PL2. That is, when one of the high potential H and the low potential L is supplied to the first plate line PL1, the other is supplied to the second plate line PL2.

  The “0” write phase is a state in which the low potential L is supplied to the first plate line PL1 and the high potential H is supplied to the second plate line PL2. The “1” write phase is a state in which the high potential H is supplied to the first plate line PL1 and the low potential L is supplied to the second plate line PL2.

  When writing “0” to the first MTJ element MTJ1 and “1” to the third MTJ element MTJ1 ′, as shown in FIG. 6A, in the “0” write phase, the first bit A high potential H is supplied to the line BL1, and a low potential L is supplied to the second bit line BL2. Then, as shown in FIG. 6B, the first transistor M1 and the third transistor M1 'are turned on. On the other hand, the second transistor M2 and the fourth transistor M2 'are kept off. In the “0” write phase, since the low potential L is supplied to the first plate line PL1 and the high potential H is supplied to the second plate line PL2, the write shown in FIG. 6B is performed in the TCAM cell CC. A current Iw1 flows.

  The write current Iw1 flows from the free layer FR to the fixed layer FI in the first MTJ element MTJ1, and from the fixed layer FI to the free layer FR in the third MTJ element MTJ1 '. As a result, the first MTJ element MTJ1 transitions to the low resistance state, and the third MTJ element MTJ1 'transitions to the high resistance state. In this way, the logical value “0” associated with the low resistance state is associated with the first MTJ element MTJ1, and the logical value “1” associated with the high resistance state is associated with the third MTJ element MTJ1 ′. Are written respectively.

  On the other hand, when “0” is written to the second MTJ element MTJ2 and “1” is written to the fourth MTJ element MTJ2 ′, as shown in FIG. A low potential L is supplied to the first bit line BL1, and a high potential H is supplied to the second bit line BL2. Then, the second transistor M2 and the fourth transistor M2 'are turned on. On the other hand, the first and third transistors M1 and M1 'are maintained in the off state. In the “0” write phase, the low potential L is supplied to the first plate line PL1, and the high potential H is supplied to the second plate line PL2. Therefore, a write current flows from the second plate line PL2 to the first plate line PL1 through the second and fourth transistors M2 and M2 'that are turned on. This write current flows from the free layer FR to the fixed layer FI in the second MTJ element MTJ2, and from the fixed layer FI to the free layer FR in the fourth MTJ element MTJ2 '. As a result, the second MTJ element MTJ2 transitions to the low resistance state, and the fourth MTJ element MTJ2 'transitions to the high resistance state. That is, “0” is written in the second MTJ element MTJ2, and “1” is written in the fourth MTJ element MTJ2 ′.

  When writing “1” into the first MTJ element MTJ1 and “0” into the third MTJ element MTJ1 ′, as shown in FIG. 7A, in the “1” write phase, the first bit A high potential H is supplied to the line BL1, and a low potential L is supplied to the second bit line BL2. Then, as shown in FIG. 7B, the first transistor M1 and the third transistor M1 'are turned on. On the other hand, the second transistor M2 and the fourth transistor M2 'are kept off. In the “1” write phase, since the high potential H is supplied to the first plate line PL1 and the low potential L is supplied to the second plate line PL2, the write shown in FIG. 7B is performed in the TCAM cell CC. Current Iw2 flows.

  The write current Iw2 flows from the fixed layer FI to the free layer FR in the first MTJ element MTJ1, and from the free layer FR to the fixed layer FI in the third MTJ element MTJ1 '. As a result, the first MTJ element MTJ1 transitions to the high resistance state, and the third MTJ element MTJ1 'transitions to the low resistance state. That is, “1” is written in the first MTJ element MTJ1 and “0” is written in the third MTJ element MTJ1 ′.

  On the other hand, when writing “1” to the second MTJ element MTJ2 and “0” to the fourth MTJ element MTJ2 ′, as shown in FIG. A low potential L is supplied to the first bit line BL1, and a high potential H is supplied to the second bit line BL2. Then, the second and fourth transistors M2 and M2 'are turned on. On the other hand, the first and third transistors M1 and M1 'are maintained in the off state. In the “1” write phase, a high potential H is supplied to the first plate line PL1, and a low potential L is supplied to the second plate line PL2. Therefore, a write current flows from the first plate line PL1 to the second plate line PL2 through the second and fourth transistors M2 and M2 'that are turned on. This write current flows from the fixed layer FI to the free layer FR in the second MTJ element MTJ2, and from the free layer FR to the fixed layer FI in the fourth MTJ element MTJ2 '. As a result, the second MTJ element MTJ2 transitions to the high resistance state, and the fourth MTJ element MTJ2 'transitions to the low resistance state. That is, “1” is written in the second MTJ element MTJ2, and “0” is written in the fourth MTJ element MTJ2 ′.

  As described above, in the phase selective parallel writing, the MTJ element is selected by selecting the first and second bit lines BL1 and BL2 in the write phase corresponding to the data (“0” or “1”) desired to be written. Write data to. When writing is desired for the first and third MTJ elements MTJ1 and MTJ1 ', the first bit line BL1 is selected. When writing to the second and fourth MTJ elements MTJ2 and MTJ2 'is desired, the second bit line BL2 is selected.

  The data b1 stored in the first MTJ element MTJ1 and the data stored in the third MTJ element MTJ1 'are in a complementary relationship. That is, when one of “0” or “1” is stored in the first MTJ element MTJ1, the other is stored in the third MTJ element MTJ1 ′. Similarly, the data b2 stored in the second MTJ element MTJ2 and the data stored in the fourth MTJ element MTJ2 'are in a complementary relationship.

  As described above, the TCAM cell CC can store 2-bit binary data of b1 and b2. The TCAM cell CC has three storage states of “0”, “1”, and “X (Don't-care)”. These three storage states are represented as 2-bit binary data (1, 0), (0, 1), (1, 1) of b1 and b2, respectively, as shown in the truth table of FIG. . In the truth table of FIG. 8, B represents the storage state of the TCAM cell CC, S represents the search data input via the second search line SL, and ML represents the output of the match line ML.

The potential of the match line ML indicating the result of the match / mismatch determination in the TCAM cell CC is determined by the resistance value of the TCAM cell CC.
When the stored data and the search data match (for example, when search data S = 0 is input to the TCAM cell CC in the storage state B = 0, or to the TCAM cell CC in the storage state B = 1) When the search data S = 1 is input), the potential of the match line ML becomes the high output voltage _VCO-H . Similarly, when the TCAM cell CC stores “X”, the stored data and the search data are considered to match, and the potential of the match line ML becomes the high output voltage V _CO-H . In these cases, “HIT” is represented in the truth table of FIG.
On the other hand, when the storage data and the search data do not match (for example, when search data S = 1 is input to the TCAM cell CC in the storage state B = 0, or to the TCAM cell CC in the storage state B = 1) When the search data S = 0 is input), the potential of the match line ML becomes the low output voltage V _CO-M . In this case, “MISS” is represented in the truth table of FIG.
More generally, the logic level of the match line ML when the search data S is input to the TCAM cell CC in which the storage data (b1, b2) is stored via the second search line SL is: ML = / S · b1 + S · b2.

Next, a search operation for the TCAM cell CC will be described. The first and second plate line drivers PD1 and PD2 shift to the search phase when the low voltage L is supplied to the word line WL and the high voltage H is supplied as the search permission signal SE. In the search phase, the first and second plate line drivers PD1 and PD2 cause the first and second plate lines PL1 and PL2 to function as the power supply line _VDD and the ground line GND, respectively.

  In the search operation, first, the match line ML is precharged to the power supply voltage. Thereafter, data is input via the first and second search lines SL and / SL. The search data S input to the second search line SL and the data input to the first search line / SL are in a complementary relationship. By selecting the second search line SL or the first search line / SL, the first and third transistors M1, M1 'or the second and fourth transistors M2, M2' are turned on. As a result, the current paths of the comparison logic circuit 10 and the complementary logic circuit 20 are selected, the charge of the match line ML is discharged to the ground line GND, and the match / mismatch determination between the input data and the stored data is performed.

The discharge of the match line ML is controlled by the transistor M3 that functions as a diode switch. If the potential of the match line ML is higher than the output voltage _{V CO} of TCAM cell CC, transistor M3 is turned on, the charge of the match line ML is discharged to the ground line GND. When the potential of the match line ML is below V _CO, transistor M3 is turned off, discharging of the match line ML is cut off. For this reason, the potential of the match line ML precharged to the power supply voltage at the time of the search operation is stored up to the high output voltage V _CO-H when the stored data matches the input data (HIT). When the data and the input data do not match (MISS), each is discharged to the low output voltage V _CO-M . Therefore, by detecting the potential of the match line ML, it is possible to obtain the result of the match / mismatch determination in each TCAM cell CC.

Further, the result of determination of coincidence / mismatch between the stored data and the input data in the TCAM word circuit composed of a plurality of TCAM cells CC connected to the common match line ML is also obtained by detecting the potential of the match line ML. it can. When the word circuit includes at least one TCAM cell CC in which stored data and input data do not match (MISS), the charge on the match line ML is discharged to the low output voltage V _CO-M through the TCAM cell CC. The When the stored data and the input data match in all TCAM cells CC of the word circuit (HIT), the charge on the match line ML is discharged to the high output voltage _VCO-H .

As shown in FIG. 9, the high output voltage V _CO-H that is the output voltage V _CO when the stored data and the input data match in the TCAM cell CC is a load that is complementary to the current curve I _HIT and this current curve. Determined by the intersection with the current curve I _HIT '. On the other hand, the low output voltage V _CO-M , which is the output voltage V _CO when the stored data and the input data do not match in the TCAM cell CC, is complementary to the current curve I _MISS and the current curve as shown in FIG. Determined by the intersection with the load current curve I _MISS '. The output voltage amplitude ΔV _CO of the TCAM cell CC, that is, the difference between the high output voltage V _CO-H and the low output voltage V _CO-M is the same as the output voltage amplitude ΔV _{CO of the} conventional TCAM cell CC ′ shown in FIG. Compared to

In the TCAM cell CC ′ of Non-Patent Document 2 shown in FIG. 3A, the comparison logic circuit 10 composed of a combination of an N-type field effect transistor and an MTJ element is operated with a fixed load LO as a load. It was. On the other hand, in the TCAM cell CC according to the present embodiment, a complementary logic circuit based on complementary logic configured by a P-type field effect transistor and an MTJ element in which inverted data is written is provided for the comparison logic circuit 10. 20 is operated as a load. As a result, TCAM cell according to the present embodiment, the output voltage amplitude [Delta] V _CO was significantly (improving the operation margin), it is possible to suppress the variation among elements of the resistance value due to the device characteristics. Since the output voltage amplitude ΔV _CO in the TCAM cell CC and the word circuit WC is greatly increased, it is possible to easily determine the comparison operation result in the sense amplifier and to reduce the error rate (false determination rate) of the search operation. it can.

  This can reduce the number of redundant word circuits WC provided to replace defective word circuits during chip manufacture, leading to a reduction in chip area. Furthermore, since a sufficient match line output voltage amplitude can be ensured, the sense amplifier SA does not need to be highly sensitive, and the chip area can be further reduced by using a simple sense amplifier.

  In addition, the TCAM cell CC according to the present embodiment eliminates the write-only access transistor and shares the write operation transistor and the search operation transistor, thereby reducing the number of elements compared to the conventional TCAM cell CC ′. Has a reduced compact configuration. Furthermore, the word circuit WC according to the present embodiment uses the bit lines BL1 and BL2 as the write data phase in the “0” write phase and the “1” write phase that are alternately repeated by the two plate line drivers PD1 and PD2. By using it for selection, data can be written in bit parallel to a plurality of TCAM cells. Since bit-parallel writing is possible without using a write-only access transistor, large-capacity data can be written at high speed. That is, the TCAM cell CC according to the present embodiment achieves high reliability of the search operation and high speed of the write operation while maintaining compactness.

(Evaluation)
Next, the evaluation results of the detection margin and the error rate during the search operation of the nonvolatile TCAM cell according to the embodiment will be described.

  A 72-bit nonvolatile TCAM using the conventional 6T-2MTJ type TCAM cell CC ′ shown in FIG. 3A and the 5T-4MTJ type TCAM cell CC according to the embodiment shown in FIG. A word circuit was designed.

Using the designed non-volatile TCAM word circuit, a Monte Carlo simulation of 1000 trials was performed under 90 nanometer CMOS technology, and the worst case “HIT” and 1-bit “MISS” The detection margin and error rate were evaluated.

The voltage of the power supply line V _DD was set to 1.2 V, and the clock cycle was set to 5 nanoseconds (200 MHz). It was assumed that the variation of all transistors and MTJ elements in the designed word circuit was random. The standard deviation σ of the threshold voltage of each transistor was set based on the gate region and the Pelgrom coefficient of each transistor using 90 nanometer CMOS technology. The resistance values of the MTJ elements in the “0” state and “1” state were set to 3.0 kΩ and 7.5 kΩ, respectively. The standard deviation σ of each resistor was set to 5%, which is the value of the standard deviation σ of a typical resistor.

  FIG. 10A shows a simulation waveform when a parallel search operation is performed with 72 bits in a word circuit using a conventional 6T-2MTJ type TCAM cell CC '. The upper diagram shows the waveforms of signals flowing through the match line ML when the search word and the storage word match (“HIT”) and when they do not match (“MISS”). The middle and lower diagrams show the waveforms of the output signals in the case of “HIT” and “MISS”, respectively.

In the upper figure, lower output voltage amplitude [Delta] V _CO of TCAM cells CC ', for the variation of the waveform is large, as the detection margin between the signal in the case of the "HIT" signal and a "MISS" in the case of, as 39mV It can be seen that there is only a small detection margin. For this reason, in the middle diagram, the error that detects “HIS” is detected once, and in the lower diagram, the error that detects “MISS” is detected as “HIT”. Each occurred 4 times. As a result, the error rate was evaluated to be 0.25% (= 5/2000).

  FIG. 10B shows simulation waveforms when a parallel search operation is performed with 72 bits in the word circuit using the 5T-4MTJ type TCAM cell CC according to the embodiment. Each figure is viewed in the same manner as in FIG. In the upper diagram, it can be seen that a detection margin of 5.2 times larger than the conventional detection margin of 204 mV was obtained due to the effect of the complementary cell structure. For this reason, as shown in the middle and lower figures, the detection error disappeared. In addition, since the voltage amplitude of the match line ML is increased to 5.2 times, the delay of the match determination in the evaluation phase is shortened from 2.1 nanoseconds to 1.3 nanoseconds in the conventional word circuit.

  As described above, the word circuit using the 5T-4MTJ type TCAM cell CC according to the above-described embodiment has a larger detection margin than the word circuit using the conventional 6T-2MTJ type TCAM cell CC ′. It was found that detection errors can be reduced. Therefore, according to the nonvolatile content addressable memory cell according to the present invention, as described above, the circuit operation of the nonvolatile TCAM is highly reliable and compact.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible. For example, in the above-described embodiment, the first and second transistors M1 and M2 are N-type MOSFETs, and the third and fourth transistors M1 'and M2' are P-type MOSFETs. However, the first and second transistors M1 and M2 may be P-type MOSFETs, and the third and fourth transistors M1 'and M2' may be N-type MOSFETs. That is, the first and second transistors M1 and M2 and the third and fourth transistors M1 'and M2' need only have opposite conductivity types.

  The configuration of the MTJ element is also arbitrary. That is, in the above-described embodiment, as shown in FIGS. 1A to 1C, the upper electrode terminal TE is provided in the free layer FR of each MTJ element, and the lower electrode terminal BE is provided in the fixed layer FI. However, unlike this, the lower electrode terminal BE may be provided in the free layer FR of each MTJ element, and the upper electrode terminal TE may be provided in the fixed layer FI. That is, the directions of the four MTJ elements MTJ1, MTJ2, MTJ1 ′, and MTJ2 ′ are opposite, and the electrodes on the free layer FR side of the first and second MTJ elements MTJ1 and MTJ2 are the first and second electrodes, respectively. The electrodes on the free layer FR side of the third and fourth MTJ elements MTJ1 ′ and MTJ2 ′ are connected to the sources of the third and fourth transistors M1 ′ and M2 ′, respectively, connected to the sources of the transistors M1 and M2. May be.

  Further, the TCAM cell CC according to the above-described embodiment stores data by associating the logic value “0” with the low resistance state of the MTJ element and the logic value “1” with the high resistance state. The logic value “1” may be associated with the state, and the logic value “0” may be associated with the high resistance state. The nonvolatile content addressable memory cell according to the present invention may be configured by a resistance change type storage element other than the MTJ element.

CC, CC 'TCAM cells MTJ1, MTJ2, MTJ1', MTJ2 'MTJ elements M1 to M6, M1', M2 'Transistor FR Free layer FI Fixed layer TB Tunnel barrier TE Upper electrode terminal BE Lower electrode terminal LO Fixed load WD Word line Driver SD Search line driver BD Bit line driver PD, PD1, PD2 Plate line driver OD Output driver SA Sense amplifier WC Word circuit ML Match line WL Word line BL1, BL2 Bit line PL1, PL2 Plate line SL, / SL Search line OL Output Line V _DD Power supply line GND Ground line 10 Comparison logic circuit 20 Complementary logic circuit 100 TCAM

Claims (7)

A first transistor having one end connected to a predetermined connection point and a control end connected to a first search line;
A second transistor having one end connected to the predetermined connection point and a control end connected to a second search line;
A third transistor having one end connected to the predetermined connection point and a control end connected to the second search line;
A fourth transistor having one end connected to the predetermined connection point and a control end connected to the first search line;
A first resistance change type storage element disposed between the other end of the first transistor and a second plate line;
A second resistance change type storage element disposed between the other end of the second transistor and the second plate line;
A third resistance change type storage element disposed between the other end of the third transistor and the first plate line;
A fourth resistance change type storage element disposed between the other end of the fourth transistor and the first plate line;
A non-volatile associative memory cell comprising: The first transistor and the second transistor are first conductivity type field effect transistors,
The third transistor and the fourth transistor are field effect transistors of a second conductivity type opposite to the first conductivity type.
The nonvolatile content addressable memory cell according to claim 1. Each of the first, second, third, and fourth resistance change memory elements includes a lower electrode terminal and an upper electrode terminal;
The lower electrode terminal of the first resistance change type storage element is connected to the other end of the first transistor;
The lower electrode terminal of the second resistance change type storage element is connected to the other end of the second transistor;
The lower electrode terminal of the third resistance change type storage element is connected to the other end of the third transistor;
The lower electrode terminal of the fourth resistance change type storage element is connected to the other end of the fourth transistor;
The nonvolatile associative memory cell according to claim 1 or 2.   4. The nonvolatile memory according to claim 1, further comprising a fifth transistor having one end connected to the predetermined connection point and the other end connected to a match line. Sex-associative memory cell. The first search line is shared with a first bit line that transmits a control signal to the control terminal of the first transistor and writes data to the first resistance change type storage element.
The second search line is shared with a second bit line that transmits a control signal to the control terminal of the second transistor and writes data to the second resistance change storage element.
The nonvolatile content addressable memory cell according to claim 1, wherein the nonvolatile content addressable memory cell is a memory cell. 6. Each of the nonvolatile content addressable memory cells according to claim 1, wherein a plurality of nonvolatile content addressable memory cells share the first plate line and the second plate line. ,
The first potential is supplied by alternately switching a high potential and a low potential to the first plate line during a data write operation to the first resistance change type storage element and the second resistance change type storage element. A plate wire driver,
In the write operation, when the first plate line driver supplies a high potential to the first plate line, a low potential is supplied to the second plate line, and the first plate line driver When a low potential is supplied to the first plate line, a high potential and a low potential are alternately switched to the second plate line so that a high potential is supplied to the second plate line. A second plate line driver to supply;
A non-volatile associative memory comprising: The first plate line driver functions as the power line in the search operation of data written in the first resistance change type storage element and the second resistance change type storage element. Let
The second plate line driver causes the second plate line to function as a ground line during the search operation.
The nonvolatile content addressable memory according to claim 6.

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