JP5603895B2 - Semiconductor memory device driving method and semiconductor memory device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor memory device driving method and a semiconductor memory device.

  One of the resistance change type memories is a magnetic random access memory (MRAM). An MRAM using an STT (Spin Transfer Torque) type MTJ element has a smaller resistance change rate due to miniaturization. In this case, since the read signal difference is small, highly accurate data detection is required when reading data. For high-precision data detection, the reference data is preferably close to the middle between data “1” and data “0”. However, in the miniaturized MRAM, it is difficult to set the reference data between the data “1” and the data “0” due to variations in element characteristics.

US Patent Application Publication No. 2009/0323402

  A semiconductor memory device capable of detecting a minute signal difference with high accuracy and a driving method thereof are provided.

The driving method of the semiconductor memory device according to the present embodiment includes a plurality of resistance change type storage elements, a signal holding unit that holds a plurality of voltages corresponding to data stored in the storage element, and a signal holding unit. A method for driving a semiconductor storage device comprising a sense amplifier that detects data stored in a storage element based on a voltage,
In the reading operation of the target data stored in the first storage element selected from among the plurality of storage elements,
The first voltage corresponding to the target data is held in the signal holding unit,
Writing the first sample data of the first logic into the first memory element;
Holding a second voltage corresponding to the first sample data in the signal holding unit;
Write second sample data of the second logic, which is opposite to the first logic, to the first memory element,
Holding a third voltage corresponding to the second sample data in the signal holding unit;
In the sense amplifier, by comparing the read signal based on the first voltage with the reference signal generated based on the second and third voltages, the logic of the target data stored in the first storage element is obtained. The signal holding unit is connected in parallel with each other, and the first and second transistors receiving the first voltage at the gate electrode are connected in parallel with each other, and the second voltage and the third voltage A third and a fourth transistor each receiving a voltage at the gate electrode;
The first voltage is held at the gate electrodes of the first and second transistors,
The second voltage is held at the gate electrode of the third transistor,
The third voltage is held at the gate electrode of the fourth transistor.

The block diagram which shows the memory chip of the magnetic random access memory according to this embodiment. 3 is an explanatory diagram showing a configuration of a single memory cell MC. FIG. FIG. 3 is a circuit diagram showing a schematic configuration of the MRAM according to the present embodiment. FIG. 5 is a timing chart showing a data read operation of the MRAM according to the present embodiment. FIG. 5 is a flowchart showing a data read operation of the MRAM according to the present embodiment. FIG. 3 is a schematic diagram of a signal holding circuit SSC and a sense amplifier SA. The graph explaining each reference signal of MRAM by this embodiment and MRAM by a comparative example.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  FIG. 1 is a block diagram showing a memory chip of a magnetic random access memory (hereinafter referred to as MRAM) according to the present embodiment. The present embodiment is not limited to this, and can also be applied to a memory (for example, PCRAM, ReRAM, etc.) using a resistance variable element other than MRAM.

  The MRAM according to the present embodiment includes a memory cell array MCA, a sense amplifier SA, a main data controller MDC, a DQ buffer DQB, a column controller CC, a row controller RC, a clock buffer CLKB, a command controller CMDC, and an address controller. An ADDC and an array controller AC are provided.

  The memory cell array MCA includes a plurality of memory cells MC that are two-dimensionally arranged in a matrix, for example. Each memory cell MC is arranged corresponding to the intersection of a bit line pair (for example, BL1 and BL2) and a word line WL. That is, one end of the memory cell MC is connected to one BL1 of the bit line pair, and the other end is connected to the other BL2 of the bit line pair. The bit line pair BL1, BL2 extends in the column direction. The word line WL extends in the row direction orthogonal to the column direction.

  The sense amplifier SA is connected to the memory cell MC via, for example, the bit line BL1, and has a function of detecting data in the memory cell MC. The write driver WD is connected to the memory cell MC via, for example, the bit lines BL1 and BL2, and has a function of writing data to the memory cell MC.

  The main data controller MDC transfers the data received from the DQ buffer DQB to the write driver WD so as to write to the desired column under the control of the column controller CC, or receives the desired data under the control of the column controller CC. The data read from the first column is transferred to the DQ buffer DQB.

  A DQ buffer DQB as a data buffer temporarily holds read data detected by the sense amplifier SA and outputs the read data to the outside of the memory chip 1. Alternatively, the DQ buffer DQB temporarily holds the write data received via the DQ pad DQ and transfers the write data to the write driver WD.

  The column controller CC operates the sense amplifier SA or the write driver WD so as to selectively drive the bit line BL of a desired column according to the column address.

  The row controller RC operates the word line driver WLD so as to selectively drive a desired word line WL according to the row address.

  The clock buffer CLKB receives a clock signal that determines the operation timing of the entire memory chip 1.

  The command controller CMDC receives commands indicating various operations such as a read operation and a write operation, and controls the column controller CC and the row controller RC according to those commands.

  The address controller ADDC receives a row address and a column address, decodes these addresses, and sends these addresses to the column controller CC and the row controller RC.

  The array controller AC performs overall control of the memory cell array MCA.

  FIG. 2 is an explanatory diagram showing a configuration of a single memory cell MC. Each memory cell MC includes a magnetic tunnel junction element (MTJ (Magnetic Tunnel Junction) element) and a cell transistor CT. The MTJ element and the cell transistor CT are connected in series between the bit line BL1 and the bit line BL2. In the memory cell MC, the cell transistor CT is disposed on the bit line BL2 side, and the MTJ element is disposed on the bit line BL1 side. The gate of the cell transistor CT is connected to the word line WL.

    An STT-MTJ element using the TMR (tunneling magnetoresistive) effect has a laminated structure composed of two ferromagnetic layers and a nonmagnetic layer (insulating thin film) sandwiched between them, and is magnetized by a spin-polarized tunnel effect. Digital data is stored by changing resistance. The MTJ element can take a low resistance state and a high resistance state depending on the magnetization arrangement of the two ferromagnetic layers. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element. Of course, the low resistance state may be defined as data “1”, and the high resistance state may be defined as data “0”. For example, the MTJ element is formed by sequentially laminating a fixed layer P, a tunnel barrier layer B, and a recording layer Fr as shown in FIG. The fixed layer P and the recording layer Fr are made of a ferromagnetic material, and the tunnel barrier layer B is made of an insulating film. The fixed layer P is a layer whose magnetization direction is fixed, and the recording layer Fr has a variable magnetization direction, and stores data according to the magnetization direction.

    When a current equal to or greater than the reversal threshold current is passed in the direction of the arrow A1 during writing, the recording layer Fr is in an anti-parallel state with respect to the magnetization direction of the fixed layer P, and is in a high resistance state (data “1”). When a current equal to or greater than the inversion threshold current is passed in the direction of the arrow A2 at the time of writing, the magnetization directions of the fixed layer P and the recording layer Fr are in a parallel state and a low resistance state (data “0”). Thus, the TMJ element can write different data depending on the direction of current.

  In the data read operation of the MRAM, the sense amplifier SA detects a difference in resistance value of the memory cell MC by supplying a current (cell current) to the memory cell MC. At this time, the cell current is less than the inversion threshold current at the time of writing, and therefore the read current is necessarily a very small value.

  For example, the sense amplifier SA includes a constant current type sense amplifier and a constant voltage clamp type sense amplifier. When a constant current sense amplifier is used, the voltage difference (signal difference) between data “0” and data “1” is several tens of mV. When a constant voltage clamp type sense amplifier is used, the current ratio (signal ratio) between data “0” and data “1” is several μA.

  In order to detect such a fine signal difference, highly accurate data detection is necessary. In order to perform highly accurate data detection, appropriate reference data set near the center of data “1” and data “0” is necessary. In order to generate such appropriate reference data, the configuration shown in FIG. 3 is used in the present embodiment.

  FIG. 3 is a circuit diagram showing a schematic configuration of the MRAM according to the present embodiment. FIG. 3 shows a memory cell MC selected in the memory cell array MCA and a circuit connected to the selected memory cell MC in the data read operation. The other unselected memory cells, the word lines WL, and the bit lines BL are not shown.

  The MRAM according to the present embodiment includes a memory cell array MCA, a write bias circuit WBC, a read bias circuit RBC, a signal holding circuit SSC, and a sense amplifier SA.

  The write bias circuit WBC includes n-type transistors Tw0 and Tw1 and p-type transistors Tbw0 and Tbw1. The transistors Tw0 and Tbw0 are transistors that are turned on when data “0” is written to the selected memory cell MC. The gate signals W0 and bW0 of the transistors Tw0 and Tbw0 are complementary signals, and drive the transistors Tw0 and Tbw0 simultaneously. The transistors Tw1 and Tbw1 are transistors that are turned on when data “1” is written to the selected memory cell MC. The gate signals W1 and bW1 of the transistors Tw1 and Tbw1 are complementary signals, and drive the transistors Tw1 and Tbw1 simultaneously.

  When transistors Tw0 and Tbw0 are conductive, current I0 flows through selected memory cell MC, and data “0” is written. When the transistors Tw1 and Tbw1 are in a conductive state, a current I1 flows through the selected memory cell MC, and data “1” is written.

  The read bias circuit RBC includes two n-type transistors Tre, an n-type transistor Tclmp, and a p-type transistor Tload. The transistor Tre is a transistor that becomes conductive in the data read operation. The transistor Tre is controlled by a read enable signal RE. The transistor Tclmp is a transistor that determines a voltage to be applied to the selected memory cell MC at the time of reading. The transistor Tclmp is controlled by the clamp signal VCLMP and becomes conductive in the data read operation. The transistor Tload is a transistor that determines the voltage Vx of the node Nx. The transistor Tload is controlled by the load signal VLOAD and becomes conductive in the data read operation.

  A node Nx between the transistors Tload and Tclmp is connected to the signal holding circuit SSC. The voltage Vx of the node Nx is transmitted to the signal holding circuit SSC as a signal corresponding to the data in the selected memory cell MC.

  In the data read operation, the read bias circuit RBC applies a predetermined voltage to the selected memory cell MC and causes a current Iread to flow through the selected memory cell MC. At this time, the read bias circuit RBC supplies the voltage Vx of the node Nx to the signal holding circuit SSC.

  The signal holding circuit SSC includes n-type transistors Tp1 to Tp4, p-type transistors Tbp1 to Tbp4, and n-type transistors T1 to T4. Transistors Tp1 and Tbp1 are connected in parallel to each other. Thus, the transistors Tp1 and Tbp1 function as a first transfer gate TG1 that transfers the voltage Vx to the gate electrode (gate node) NG1 of the transistor T1. Transistors Tp2 and Tbp2 are connected in parallel to each other. Thus, the transistors Tp2 and Tbp2 function as a second transfer gate TG2 that transfers the voltage Vx to the gate electrode (gate node) NG2 of the transistor T2. Transistors Tp3 and Tbp3 are connected in parallel to each other. Thus, the transistors Tp3 and Tbp3 function as a third transfer gate TG3 that transfers the voltage Vx to the gate electrode (gate node) NG3 of the transistor T3. Transistors Tp4 and Tbp4 are connected in parallel to each other. Thereby, the transistors Tp4 and Tbp4 function as a fourth transfer gate TG4 that transfers the voltage Vx to the gate electrode (gate node) NG4 of the transistor T4.

  The gate signals P1 and bP1 are complementary signals, and are signals that drive the first transfer gate TG1. The gate signals P2 and bP2 are complementary signals, and are signals that drive the second transfer gate TG2. The gate signals P3 and bP3 are complementary signals, and are signals that drive the third transfer gate TG3. The gate signals P4 and bP4 are complementary signals, and are signals that drive the fourth transfer gate TG4.

The gate electrode NG1 of the first transistor T1 is connected to the node Nx via the first transfer gate TG1. The gate electrode NG2 of the second transistor T2 is connected to the node Nx via the second transfer gate TG2. The first transistor T1 and the second transistor T2 are connected in parallel to each other.

  The drains of the first transistor T1 and the second transistor T2 are connected to the sense node bSN of the sense amplifier SA via the transistor Tsen12 and the like.

  The gate electrode NG3 of the third transistor T3 is connected to the node Nx via the third transfer gate TG3. The gate electrode NG4 of the fourth transistor T4 is connected to the node Nx via the fourth transfer gate TG4. The third transistor T3 and the fourth transistor T4 are connected in parallel to each other.

  The drains of the third transistor T3 and the fourth transistor T4 are connected to the sense node SN of the sense amplifier SA via the transistor Tsen34 and the like.

  The signal holding circuit SSC having such a configuration can hold the voltage Vx of the node Nx at any of the gate nodes NG1 to NG4 by controlling the transfer gates TG1 to TG4.

  The sense amplifier SA includes n-type transistors Tsen12 and Tsen34, p-type transistors Tsep12 and Tsep34, and a latch circuit LC.

  The transistor Tsen12 is connected between the drains of the transistors T1 and T2 of the signal holding circuit SSC and the latch circuit LC. The transistor Tsen34 is connected between the drains of the transistors T3 and T4 of the signal holding circuit SSC and the latch circuit LC. The transistors Tsen12 and Tsen34 receive the sense enable signal SE in common and are driven simultaneously.

  The latch circuit LC includes n-type transistors TLCn1 and TLCn2 and p-type transistors TLCp1 and TLCp2.

  The transistors TLCn1 and TLCp1 are directly connected between the power supply voltage VDD and the transistor Tsen12. The gate electrodes of the transistors TLCn1 and TLCp1 are commonly connected to a sense node SN between the transistors TLCn2 and TLCp2.

  The transistors TLCn2 and TLCp2 are directly connected between the power supply voltage VDD and the transistor Tsen34. The gate electrodes of the transistors TLCn2 and TLCp2 are commonly connected to a sense node bSN between the transistors TLCn1 and TLCp1.

  Thus, the gate electrodes of the transistors TLCn1 and TLCp1 and the gate electrodes of the transistors TLCn2 and TLCp2 are cross-coupled.

  The sense node bSN between the transistor TLCn1 and the transistor TLCp1 is connected to the power supply voltage VDD via the transistor Tsep12. A sense node SN between the transistors TLCn2 and TLCp2 is connected to the power supply VDD via the transistor Tsep34.

  The sense amplifier SA having such a configuration amplifies the voltage difference between the voltage obtained via the transistor Tsen12 and the voltage obtained via the transistor Tsen34, and the voltage difference is applied to the sense nodes SN and bSN of the latch circuit LC. Can be latched. Then, the voltage held at the sense node SN is output as a detection result.

  Next, the operation of the MRAM according to the present embodiment will be described.

  FIG. 4 is a timing diagram showing a data read operation of the MRAM according to the present embodiment. FIG. 5 is a flowchart showing a data read operation of the MRAM according to the present embodiment. The selected memory cell MC as the first storage element stores certain logical data as a read target. According to the data read sequence shown in FIG. 4, the MRAM detects read target data in the selected memory cell MC. Note that in the data read operation, the transistors Tload and Tclmp in FIG. 3 maintain the conductive state.

  First, from t0 to t1, the MRAM executes the first read operation (S10). In the first read operation, the signal holding circuit SSC holds the first voltage based on the read target data stored in the selected memory cell MC (S20).

  More specifically, the read enable signal RE is activated to logic high. As a result, the read bias circuit RBC shown in FIG. 3 passes the read current Iread to the selected memory cell MC. Also, the gate signals P1 and P2 are activated to logic high. Accordingly, the gate signals bP1 and bP2 are activated to logic low. As a result, the first and second transfer gates TG1 and TG2 shown in FIG. 3 become conductive. The first voltage corresponding to the read target data is transmitted to the gate nodes NG1 and NG2 via the first and second transfer gates TG1 and TG2.

  Then, the first and second transfer gates TG1 and TG2 are made non-conductive by inactivating the gate signals P1 and P2 to logic low and inactivating the gate signals bP1 and bP2 to logic high. To do. As a result, the first voltage is held at the gate nodes NG1 and NG2.

  Next, from t1 to t2, the MRAM performs a write operation of data “0” as the first sample data (S30). In the write operation of data “0”, the write bias circuit WBC writes data “0” to the selected memory cell MC.

  More specifically, the gate signal W0 of the transistor Tw0 in FIG. 3 is activated to logic high, and the gate signal bW0 of the transistor Tbw0 is activated to logic low. As a result, the write bias circuit WBC shown in FIG. 3 causes the current I0 to flow through the selected memory cell MC and writes data “0” into the selected memory cell MC.

  At this time, the data to be read is overwritten with data “0” in the selected memory cell MC. However, there is no problem because the information of the read target data is held in the signal holding circuit SSC as the first voltage.

  Next, from t2 to t3, the MRAM executes a second read operation (S40). In the second read operation, the signal holding circuit SSC holds the second voltage based on the data “0” stored in the selected memory cell MC (S50).

  More specifically, the read enable signal RE is activated to logic high. As a result, the read bias circuit RBC passes the read current Iread to the selected memory cell MC. Also, the gate signal P3 is activated to logic high. Accordingly, gate signal bP3 is activated to a logic low. As a result, the third transfer gate TG3 shown in FIG. 3 becomes conductive. The second voltage corresponding to the data “0” is transmitted to the gate node NG3 via the third transfer gate TG3.

  Then, the third transfer gate TG3 is made nonconductive by inactivating the gate signal P3 to logic low and inactivating the gate signal bP3 to logic high. As a result, the second voltage is held at the gate node NG3.

  Next, from t3 to t4, the MRAM performs a write operation of data “1” as the second sample data (S60). In the write operation of data “1”, the write bias circuit WBC writes data “1” to the selected memory cell MC.

  More specifically, the gate signal W1 of the transistor Tw1 of FIG. 3 is activated to logic high, and the gate signal bW1 of the transistor Tbw1 is activated to logic low. As a result, the write bias circuit WBC shown in FIG. 3 causes the current I1 to flow through the selected memory cell MC and writes data “1” into the selected memory cell MC.

  At this time, the data “0” is overwritten by the data “1” in the selected memory cell MC. However, there is no problem because the information of data “0” is held in the signal holding circuit SSC as the second voltage.

  Next, from t4 to t5, the MRAM executes a third read operation (S70). In the third read operation, the signal holding circuit SSC holds the third voltage based on the data “1” stored in the selected memory cell MC (S80).

  More specifically, the read enable signal RE is activated to logic high. As a result, the read bias circuit RBC passes the read current Iread to the selected memory cell MC. Also, the gate signal P4 is activated to logic high. Accordingly, gate signal bP4 is activated to a logic low. As a result, the fourth transfer gate TG4 shown in FIG. 3 becomes conductive. The third voltage corresponding to the data “1” is transmitted to the gate node NG4 via the fourth transfer gate TG4.

  Then, the fourth transfer gate TG4 is made non-conductive by inactivating the gate signal P4 to logic low and inactivating the gate signal bP4 to logic high. As a result, the third voltage is held at the gate node NG4.

  Here, the signal holding circuit SSC holds the first voltage corresponding to the read target data at the gate nodes NG1 and NG2, holds the second voltage corresponding to the data “0” at the gate node NG3, and A third voltage corresponding to the data “1” is held at the gate node NG4. Therefore, the first voltage is applied to the gate electrodes of the first and second transistors T1 and T2. The second voltage is applied to the gate electrode of the third transistor T3. The third voltage is applied to the gate electrode of the fourth transistor T4.

  The states of the signal holding circuit SSC and the sense amplifier SA holding the first to third voltages are simply shown in FIGS. 6 (A) and 6 (B).

  FIG. 6A is a schematic diagram of the signal holding circuit SSC and the sense amplifier SA when the read target data is data “0”. FIG. 6B is a schematic diagram of the signal holding circuit SSC and the sense amplifier SA when the data to be read is data “1”. V0 is a voltage held in the gate nodes NG1 to NG4 when data “0” is stored in the selected memory cell MC. V1 is a voltage held in the gate nodes NG1 to NG4 when data “1” is stored in the selected memory cell MC.

  As shown in FIG. 6A, when the read target data is “0”, V0 is applied as the first voltage to the gate electrodes (NG1, NG2) of the first and second transistors T1, T2. Is done. On the other hand, as shown in FIG. 6B, when the read target data is “1”, the gate electrodes (NG1, NG2) of the first and second transistors T1, T2 have V1 as the first voltage. Is applied. Note that V0 is applied to the gate electrode (NG3) of the third transistor T3 as the second voltage in both cases of FIG. 6A and FIG. 6B. V1 is applied to the gate electrode (NG4) of the fourth transistor T4 as the third voltage in both cases of FIG. 6A and FIG. 6B.

  As described above, the conduction state of the third and fourth transistors T3 and T4 does not change depending on the logic of the read target data, but the conduction state of the first and second transistors depends on the logic of the read target data. Change.

  Therefore, at time t5 in FIG. 4, the first and second transistors T1 and T2 are in a conductive state (or non-conductive state) according to the first voltage corresponding to the data to be read. Therefore, the first and second transistors T1 and T2 can supply a read signal to the sense amplifier SA based on the first voltage.

  The third transistor T3 is in a conductive state (or non-conductive state) corresponding to the second voltage corresponding to the data “0”. The fourth transistor T4 is in a conductive state (or non-conductive state) corresponding to the third voltage corresponding to the data “1”.

  Here, since the third and fourth transistors T3 and T4 are connected in parallel, they are in an intermediate conductive state corresponding to intermediate data between the data “0” and the data “1”. Therefore, the third and fourth transistors T3 and T4 can supply an intermediate reference signal between the second voltage and the third voltage to the sense amplifier SA. The reference signal is an intermediate signal obtained according to an intermediate conductor state of the third and fourth transistors T3 and T4 by an intermediate voltage between the second voltage and the third voltage.

At t5 to t6 shown in FIG. 4, the sense amplifier SA detects the logic of the read target data (S90). More particularly, by sensor Sui enable signal SE is activated to a logic high, transistors Tsen12 and Tsen34 becomes conductive. Incidentally, when the sensor Sui enable signal SE is inactive state to a logic low, transistor Tsep12, Tsep34 is in a conductive state. Therefore, the sense nodes SN and bSN are precharged to the power supply voltage VDD. At this time, the transistors TLCn1 and TLCn2 are in a conductive state, and the transistors TLCp1 and TLCp2 are in a nonconductive state.

By Sen Sui enable signal SE is activated to a logic high, the transistor Tsen12 and Tsen34 becomes conductive, the transistors Tsep12 and Tsep34 is nonconducting. As a result, the power supply voltage VDD is disconnected from the sense nodes SN and bSN. The voltage at the sense node bSN is a voltage corresponding to the conduction state of the first and second transistors T1 and T2. The voltage of the sense node SN is a voltage corresponding to the conduction state of the third and fourth transistors T3 and T4.

  That is, a read signal based on read target data (first voltage) is transmitted to the sense node bSN. A reference signal based on intermediate data (an intermediate voltage between the second voltage and the third voltage) is transmitted to sense node SN.

  The latch circuit LC compares the voltage of the sense node bSN and the voltage of the sense node SN, amplifies the voltage difference, and latches. Thereby, the sense amplifier SA can detect read target data.

Thereafter, from t6 to t7, data restoration is executed as necessary (S100). When the logic of the second sample data is different from the logic of the read target data, the write bias circuit WBC needs to write back data having the same logic as the read target data to the selected memory cell MC.

  For example, at time t6, the selected memory cell MC stores data “1” as the second sample data. Therefore, if the read target data is data “0”, it is necessary to write back data “0” to the selected memory cell MC from t6 to t7. The write operation of data “0” is the same as the write operation of data “0” from t1 to t2. On the other hand, if the data to be read is data “1”, the data restore operation is unnecessary.

  Thus, in the present embodiment, the signal holding circuit SSC includes the first voltage based on the read target data, the second voltage based on the data “0”, and the third voltage based on the data “1”. Hold the voltage. The signal holding circuit SSC gives a read signal to the sense amplifier SA based on the first voltage, and gives a reference signal to the sense amplifier SA based on the second voltage and the third voltage. The sense amplifier SA detects the logic of the read target data stored in the selected memory cell MC by comparing the read signal with the reference signal.

  Note that the logic of the first and second sample data may be reversed. That is, data “1” may be used as the first sample data, and data “0” may be used as the second sample data. In this case, the logic of data restored at t6 to t7 is reversed.

  The MRAM according to the present embodiment generates a reference signal using data “0” actually stored in the selected memory cell MC and data “1” actually stored in the selected memory cell MC. The reference signal is used to detect read target data stored in the same selected memory cell MC. That is, in the present embodiment, data to be read is detected by a self-referencing method. Therefore, even if the characteristics of the MTJ element, the characteristics of the cell transistor, and the characteristics of the transistors constituting the signal holding circuit SSC and the sense amplifier SA vary due to process variations, the reference signal is centered between data “1” and data “0”. It can be set in the vicinity. Thereby, the MRAM according to the present embodiment can detect a fine signal obtained from the MTJ element with high accuracy.

  FIG. 7A to FIG. 7C are graphs illustrating reference signals of the MRAM according to the present embodiment and the MRAM according to the comparative example. FIG. 7A shows a reference signal of the MRAM according to the present embodiment. FIG. 7B shows a reference signal generated using a reference cell as a comparative example. FIG. 7C shows a reference signal generated using a self-referencing method as a comparative example.

  In FIG. 7B, the reference signal is generated using a reference cell different from the selected memory cell that actually stores the read target data. Therefore, the reference signal is preferably located in the middle of each signal distribution of data “0” and data “1”. However, the signal distribution of data “0” and data “1” has a certain extent according to the normal distribution. Therefore, the margin between the reference signal Vref and the data “0” and the margin between the reference signal Vref and the data “1” are small.

  In the self-referencing method shown in FIG. 7C, first, a voltage based on target data read from the selected memory cell MC is held. Thereafter, sample data of a predetermined logic is written into the selected memory cell, and the sample data is read from the selected memory cell again. Next, in order to generate the reference signal Vref, the offset voltage Vos is added to or subtracted from the sample data read out for the second time. The reference signal thus obtained is compared with the target data read for the first time to detect the target data.

  However, since the offset voltage Vos is set regardless of the characteristics of the actual MTJ element, cell transistor, etc., it is still vulnerable to process variations.

  On the other hand, in the MRAM according to the present embodiment, all the information used for obtaining the reference signal is information obtained from the actual selected memory cell MC. Accordingly, as shown in FIG. 7A, even if the characteristics of the selected memory cell MC or the cell transistor vary depending on the process, the reference signal moves accordingly.

  For example, a signal read from the selected memory cell MC1 storing data “0” is MC1_0, and a signal read from the selected memory cell MC1 storing data “1” is MC1_1. In this case, the reference signal is Vref1 near the center between MC1_0 and MC1_1. A signal read from the selected memory cell MC2 storing data “0” is MC2_0, and a signal read from the selected memory cell MC2 storing data “1” is MC2_1. In this case, the reference signal is Vref2 near the center of MC2_0 and MC2_1. As described above, in the MRAM according to the present embodiment, not only the read target data but also the reference signal Vref changes with variations in the characteristics of the actual selected memory cell and its peripheral elements. Therefore, the MRAM according to the present embodiment can obtain a reference signal that eliminates the influence of process variations. As a result, the MRAM according to the present embodiment can read data with high accuracy even if there are variations in characteristics of the memory cells MC and the like.

  In the MRAM according to the present embodiment, three read operations and two write operations are required to detect the target data of the selected memory cell MC. However, the operation speed of the MRAM is orders of magnitude faster than that of, for example, a NAND flash memory. Further, unlike the NAND flash memory, the MRAM has no limit on the number of writable times. Therefore, it can be said that the reading method according to the present embodiment is suitable for a resistance change type memory such as an MRAM.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

MC ... memory cell, MCA ... memory cell array, WBC ... write bias circuit, RBC ... read bias circuit, SSC ... signal holding circuit, SA ... sense amplifier, LC ... latch Circuit, Tp1 to Tp4, Tbp1 to Tbp4 ... transistor, TG1 to TG4 ... Transfer gate, T1 ... First transistor, T2 ... Second transistor, T3 ... Third transistor, T4 ... fourth transistor, Nx ... node, SN, bSN ... sense node

Claims (6)

A plurality of resistance change type storage elements, a signal holding unit that holds a plurality of voltages according to data stored in the storage element, and a voltage stored in the memory element based on the voltage held in the signal holding unit A method of driving a semiconductor memory device including a sense amplifier that detects data, wherein a target data stored in a first memory element selected from the plurality of memory elements is read out.
A first voltage corresponding to the target data is held in the signal holding unit,
Writing first sample data of first logic to the first memory element;
Holding a second voltage corresponding to the first sample data in the signal holding unit;
Writing second sample data of second logic, which is opposite to the first logic, to the first memory element;
Holding a third voltage corresponding to the second sample data in the signal holding unit;
In the sense amplifier, the read signal based on the first voltage is compared with the reference signal generated based on the second and third voltages, and stored in the first storage element. Detecting the logic of the target data ,
The signal holding unit is connected in parallel to each other, and the first and second transistors receiving the first voltage at the gate electrode are connected in parallel to each other, and the second voltage and the third voltage are respectively received. A third and a fourth transistor received by the gate electrode;
The first voltage is held at gate electrodes of the first and second transistors,
The second voltage is held at the gate electrode of the third transistor;
The method of driving a semiconductor memory device, wherein the third voltage is held in a gate electrode of the fourth transistor . The first and second transistors provide the read signal to the sense amplifier based on the first voltage,
2. The drive of a semiconductor memory device according to claim 1 , wherein the third and fourth transistors supply the reference signal to the sense amplifier based on the second voltage and the third voltage. Method. It said reference signal, according to claim 1 or claim 2, characterized in that the said second voltage and the third voltage is a signal obtained from the sum of the driving currents of the third and the fourth transistor A method for driving the semiconductor memory device according to the above. If the logic of the second sample data is different from the logic of the object data, according claim 1, further comprising a writing of the object data of the same logic data to the first storage element 4. A method for driving a semiconductor memory device according to any one of items 3 to 4 . A plurality of resistance change memory elements;
A signal holding unit that holds a plurality of voltages according to data stored in the storage element;
A sense amplifier that detects data stored in the storage element based on a voltage held in the signal holding unit;
The signal holding unit holds a first voltage corresponding to target data stored in a first storage element selected from the plurality of storage elements, and the first voltage written in the first storage element The second voltage corresponding to the first sample data of logic is held, and the second sample data of the second logic that is opposite to the first logic written in the first storage element Holding a third voltage in the signal holding unit;
The sense amplifier stores the read signal based on the first voltage and the reference signal generated based on the second and third voltages, thereby storing the read signal based on the first voltage. Detect the logic of the target data ,
The signal holding unit is
First and second transistors connected in parallel to each other and receiving the first voltage at a gate electrode;
A third transistor and a fourth transistor connected in parallel with each other and receiving the second voltage and the third voltage at their gate electrodes, respectively;
The first and second transistors provide the read signal to the sense amplifier;
The semiconductor memory device, wherein the third and fourth transistors supply the reference signal to the sense amplifier . The signal holding unit is
A first transfer gate for transferring the first voltage to the gate electrode of the first transistor;
A second transfer gate for transferring the first voltage to the gate electrode of the second transistor;
A third transfer gate for transferring the second voltage to the gate electrode of the third transistor;
6. The semiconductor memory device according to claim 5 , further comprising a fourth transfer gate that transfers the third voltage to a gate electrode of the fourth transistor.

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