TW200539408A - Method of manufacturing circuit device - Google Patents

Method of manufacturing circuit device Download PDF

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Publication number
TW200539408A
TW200539408A TW094113197A TW94113197A TW200539408A TW 200539408 A TW200539408 A TW 200539408A TW 094113197 A TW094113197 A TW 094113197A TW 94113197 A TW94113197 A TW 94113197A TW 200539408 A TW200539408 A TW 200539408A
Authority
TW
Taiwan
Prior art keywords
circuit
conductive pattern
coating resin
circuit device
resin
Prior art date
Application number
TW094113197A
Other languages
English (en)
Other versions
TWI317997B (en
Inventor
Sadamichi Takakusaki
Motoichi Nezu
Takaya Kusabe
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200539408A publication Critical patent/TW200539408A/zh
Application granted granted Critical
Publication of TWI317997B publication Critical patent/TWI317997B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

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200539408 九、發明說明： [發明所屬之技術領域] 本發明係關於電路裝置之製造方法，更詳而言之，係 關於具有被覆導電圖案之被覆樹脂之電路裝置之紫造方 法。 [先前技術] 參照第7圖說明習知混合積體電路裝置之構成（例 如·參閱專利文獻1)。弟7圖（A)為混合積體電路穿置1〇〇 隹之立體圖，第7圖（B)為沿第7圖（A)之χ—χ,線之剖視圖。 習知混合積體電路裝置100具有如下構成。混合積體 電路裝置1〇〇包括：矩形的基板106;設於基板1〇6表面 之絕緣層107;形成於該絕緣層107上之導電圖案1⑽；固 定於導電圖案108之電路元件104;電性連接電路元件1〇4 與導電圖案108之金屬細線105 ;以及與導電圖案1〇8電 性連接之引線（lead)lOl。另外，混合積體電路裝置！⑼全 •部用密封樹脂U)2加以密封。而且，形成於絕緣層ι〇7表 面之導電圖案108除了要進行電性連接的部位之外的區域 全部用被覆樹脂109加以被覆。 於 後 次 的 定 下面說明上述混合積體電路裝置之製造方法。首先， 由金屬構成之電路基板⑽之表面形成絕緣層107。然 ’為構成預定之電路而進行導電圖案⑽之圖案化。盆 ’以被覆要固定電路元件1 〇4 八 ^ , ^ Φ , 千104之區域外之導電圖案108 式形成被後树脂1〇9。然後，經由電路元件104之固 、密封樹脂1 02之形点笪τ产 田 等序，隶終製成上述混合積體 317010 5 .200539408 ’ 電路裝置100。 (專利文獻1)曰本特開平6 — 177295號公報（第4頁、 第1圖） ， [發明内容] _(發明所欲解決之課題） 但是，於上述混合積體電路裝置之製造方法中，係藉 由光刻（photolithography)工序部分去除被覆樹脂1〇9而使 導電圖案108露出者。具體地說係塗布被覆樹脂丨〇9以全 面被覆導電圖案108後，藉由光刻工序選擇性地去除被覆 樹脂。但是，這種方法必須進行預留將光刻工序之精度考 慮進去的裕度（margin)之設計’如此會阻礙整個裝置之小 型化。另外，為部分去除被覆樹脂109而進行之光刻工序 本身也造成製造成本之升高。 本發明係簍於上述習知技術之問題而完成者，本發明 之主要目的在於提供一種可簡單且高精度 被覆樹脂露出之電路裝置之製造方法。 “圖案仉 (解決問題之手段） 本發明之電路農置之製造方法的特 有向厚度方向突出之突出部括·將形成 表面之工庠·，ν 案形成於電路基板的 的表面形成被覆樹脂之工序；以及藉導電基板 覆樹脂而使前述突出部m =由攸表面1虫刻前述被 ^大出邛自則述被覆樹脂露出之工序。 而且，於本發明之電路裝置之 元件電性連接於前述突出 、/中，係將電路 317010 6 .200539408 而且，於本發明之電路裝置之製造方法中，係藉由從 表面均勻去除前述被覆樹脂而使前述突出部露出。 而且，於本發明之電路裝置之製造方法中，係進行前 述名虫刻直至前述突出部之側面部分露出。 而且，於本發明之電路裝置之製造方法中，前述電路 基板為由金屬構成之基板，且將前述導電圖案形成於以覆 盍丽述電路基板之表面的方式形成之絕緣層的表面。 (發明之效果） 藉由本發明之電路裝置之製造方法，可不使用曝光遮 罩地高精度使導電圖案部分地自被覆樹脂露出。具體地說 係將形成有比其他區域突出之突出部之導電圖案用被覆樹 ，加以被覆後’藉由從表面均句去除被覆樹脂即可使突出 部露出°因此’因不必進行f知技術中之光刻工序就可使 ^電圖案部分露出’所以可進行不考慮光刻工序所產生之 誤差之圖案之設計。因此，可實現電路裝置整個之小型化。 而且，因不必進行細工序，故可提供製造成本降低之電 路裝置之製造方法。 [實施方式] 茶第1圖說明作為本發明之電路裝置之一例之混合 積電路#置10之構成。第i圖⑷為混合積體電路裝置 10之立體圖’第1圖⑻為第1圖⑷之X-X,截面之剖視 圖。第i圖⑹為導電圖案19形成有突出部25之區域的放 大剖視圖。 本實施形態之混合積體電路裝置10具備：表面形成有 317010 7 .200539408 .2緣層17之電路基板16以及於該絕緣層i7之表面進行圖 木化而形成之導電圖案18。而且，除電性連接區域以外之 邛刀的導电圖案1 8由被覆樹脂26加以被覆。另外，盥導 ''电圖案18電性連接之電路元件14由密封樹脂12予以密 •封γ面具體說明如此構成之混合積體電路裝置1〇。 ，板16自散熱方面考慮可為由金屬或陶究等構 ^板。但是’也可以為由軟性板（⑽⑽— =印刷基板等，只要至少基板之表面進行過絕緣處理 P 〇另外，電路基板16之材料可採用Al、Cu或Fe it才料=采用A03,等陶竟。另外，電路基板 4也可選用其他機械強度、散熱性較好之材料
外’電路基板16之材料選用A1時，電路基板16之表面可 以形成氧化膜。 ® J 此時，如第U(B)所^為使載置於電路基板Μ 路元件"所產生之熱量較好地向外部發散，電路基 反16之月面自密封樹脂i 2露出於外部。另外為提 =體之耐祕，也可將包括電路基板16之背面在内之整個 私路基板16用密封樹脂12予以密封。 電路元件固定於導電圖案18上，電路元件14 電圖案18構成敎之電路。電路元件14可採用電晶體、 -極體等主動元件以及電容器、電阻等被動元件。 功率系半導體元件等發熱量較大之元件可以 成之散熱器（heat sink)而固定於電路基板16上。此日士構 晶面朝上（faee，）方式安裝之主動元件等係透過金屬 317010 8 •200539408 15與導電圖案1 §電性連接。 作為具體之例子，上述電路元件14可為LSI晶片、電 容器、電阻等。 一另外，在電路元件14之背面與接地電位連接時，電路 凡：14之背面用焊料或導電糊等固定。而在電路元件μ 之月面不與他者電性連接（fl〇ati叩）時使用絕緣性之 固定料元件一14之背面。再者，以晶面朝下（face如n) 式安裝電路7C件MS，，透過由谭錫等構成之凸塊電極 行安裝。 另外’上述電路元件14也可採用控制大電流之功率系 電晶體’例如功率M0S電晶體、仍仏贿、閉流體 (thyristor)等。另外，也可為功率系。 也追求尺寸小而且要薄且高性& ’、广年來’因晶片 立“ θ 呵性迠’所以與以往相比，也會 置之熱。例如：控制電腦之CPU等即是如此。 地』電另T:銅等金屬構成，與電路基板16相絕緣 =成。另外，於引線0ead)11導出之邊形成有 案18構成之烊塾（pad)。這裏引線11#自—個 數根，但也可自複數個側邊導出引線u。另外， = 多層導電圖案18。此時，於乂成 出部25。 於取上層之導電圖案18形成突 突出部25係比導電圖案18之其他區域 部分，其上面自被覆樹脂26露 -大之 路元件14、引線u電性連接。突出之上面與電 十，程度，可根據需要進行增之突出高度為幾 317010 9 200539408 絕緣層】7形成於電路基板16之表面全域，具有使導 電圖案18與電路基板16絕緣之作用。另外，絕緣層口 係將氧化師lumina)等之無機填料⑽叫高度填充至樹脂 而形成者，熱傳導性良好。導電圖案18之下端與電路基板 16之表面之距離(絕、㈣17之最小厚度)可依耐壓而變 4匕，但最好纟50师程度以上。另外，在電路基板16由絕 、、彖性材㈣成時，可省略該絕緣層17而構成混合積 裝置10。 •引線11固定於設於電路基板16之周邊部之焊墊上， 具有例如進行與外部之輸入、輸出之作用。這裏係在一邊 設有多個引線η。引、線U與焊墊之黏結係透過焊錫（焊 等導電性黏結劑而進行。 密封樹脂12藉由使用熱硬化性樹脂之傳遞成型 (transfer molding)或使用熱可塑性樹脂之射出成型而形 成。這裏係以密封電路基板16及形成於其表面之電路的^ # j形成密封樹脂12,使電路基板16之背面自密封樹脂12 露出。另外，透過成型（m〇lding)進行密封之方法以外之密 封方法也可適用於本實施形態之混合積體電路裝置，例 如：利用樹脂之澆灌進行密封、利用殼材進行密封等密封 方法也可適用。 、 被覆樹脂26以使突出部25之上面露出而被覆導電圖 案18的形悲形成於電路基板16之表面。透過設置該被覆 樹脂26可防止在製造工序中途階段附著 引起之導電圖案18之間之短路。另外，可防2== 317010 10 200539408 之中途或在使用狀態下導電圖案1 8受到損傷。 士弟1圖（B)所示，晶片烊墊（廿“ pacj) 13 A、接合焊墊 (b^dlng pad)】3B及焊墊j %係由自被覆樹脂％部分露出 $突出部25構成之部位。晶片焊墊13A上透過焊料19固 定有電路元件14。接合焊墊〗3B係以打線接合 bonding)方式接合有金屬細線15而與電路元件μ電性連 接=焊墊。焊墊13C係透過谭料固定有引線η之焊塾， 於电路基板16之周邊部成列形成有複數個該焊墊we。 如第1圖（C)所示，突出部25其上面自被覆樹脂26露 出但也可使與上面連續之側面也自被覆樹脂26露出。藉 由如此構成，即使在去除被覆樹脂26之蝕刻產生偏差時： 也可確保突出部25之上面自被覆樹脂26露出。另外，在 考慮士於露出之突出部25上透過焊錫等焊料固定電路元件 14日守’因可使焊料附著於包括側面部在内之突出部^，故 可提高焊料之連接強度。另外，形成有突出部^之部分的 導電圖案18由於突出部25所突出之量而變厚。因此，因 突出部25具有散熱器之作用’故可提升散熱效果。 另外，也可使導電圖案18延伸至電路元件14之下方。 此時’電路元件14與延伸至其下方之導電圖案18藉由被 =電圖案18之被覆樹脂26而相互絕緣。藉由形成如此 構成，可於電路元件14之下方彡 高裝置整體之配線密度。成構成電路之配線，可提 法。接著參照第2圖說明本實施形態之電路裝置之製造方 317010 11 200539408 第1工序：於本工序中，進行具有突出部25之導電 二之形成。首先，如第2圖⑷及第2剛所示，：：
導電ί:絶緣層之電路基板16上黏貼導電箔20。且，J 料可採用以銅;面主使要:::::1圖案化。導電落2°之材 為主要材枓之材料，也可採用以Fe—犯 電圖宰主==材料。導電荡2〇之厚度依所要形成之導 之區域_ Λ 阻劑21被覆與預定形成突出部2 5 • ^ Α對應之導電箔2〇之表面。 行渴n=(c)所示’接著以阻劑21作為_遮罩而進 :，未由阻劑2"皮覆之區域之導電— i::刻此 出為⑽阻劑21被覆之部分形成突 25。於本工序結束後，阻劑21被剝離。 基板16上之二=2圖^^ < _电 >白20之圖幸化。呈辦从％ .預定夕道+门 心口系化八骽地况，在形成具有 •叫而、隹，案18的形狀之阻劑21後，藉由進行渴式蝕 ;而：:圖案化。這裏，被覆包含有突出部25之；電： 18之阻劑21也被覆突出部25之周邊部 ；= 進行阻劑21夕闰娈， 疋因為考慮到 圖宰化… 時之遮罩偏移。如此考慮、阻劑21之 電落20之分離。：/ 25 一點’可確貫遠行利用姓刻之導 之周邊部合H 本實施形態中，係以突出部25 化。。日形成緣部18D之方式進行導電圖案Μ之圖案 如上所述，緣部18D係超出突出部25之形成區域而 317010 12 200539408 I成之部位。因此，綾邱1 2 η ° 攸平面看係包圍突出部2 5 而形成。換言之，藉由蔣阳添丨 tL 由將阻刎21形成得比突出部25寬一 些而形成緣部18D。如此，拉Λ十丨 ^ ^ 匕稭由將阻劑21形成得較寬而以 仗千面看超出突出部25的方式祐礓 電圖案18，可進行稃定H =成有突 之導 门^ t疋之蝕刻。亦即，因濕式蝕刻為各向 同性，故導電圖案18合夸钊也丨；i *丨 s又到侧面蝕刻，圖案化後之導電圖 ：之侧面成為錐面狀。因此’藉由進行如此之較寬姓 刻’可防止由於側面蝕刻而導致之導電圖案18之浸蝕。 如第3圖所示，接著說明形成導電圖案18之其他方 法。該圖所示之圖案形成方法基本與上述參閱第2圖說明 2法相同，不同點在於在導電圖案18之表面及背面均設 置犬出部25。以該不同點為中心進行下面說明。另外，於 ::說明中，將向上方突出而自被覆樹脂露出之突出部稱 出部25A’將向T方突出而埋人絕緣層17之突出部稱 為突出部25Β。 如第3圖⑷所示’首先形成在背面形成之突出部 MB。具體地說係在對應於預定形成突出部25β之區域形 成阻劑21然後進行姓刻，從而形成突出部25β。 如第3圖（Β)所示’以使突出部25Β埋入絕緣層”之 方式將導電羯20貼緊絕緣層之表面。經餘刻而形成之突出 部25Β之側面成為彎曲之形狀。因此，可抑制空隙在形成 突出部25Β之部位產生。 2第3圖（C)及第3圖（D)所示，為形成向紙面上方突 出之突出部25Α而進行阻劑21之形成，然後進行钱刻。 317010 13 200539408
由此形成突出部25A。這裏，突出部25A與突出部25B 形成於同樣之位置，但也可分別形成於不同之位置。 接著，如第3圖（E)及第3圖（F)所示，透過重新進行 圖案化而形成之阻劑21進行蝕刻，而形成導電圖案Μ。 第2工序：於本工序中，將除突出部25以外之區域之 導電圖案18用被覆樹脂加以被覆。具體地說，本工序係在 以全面覆蓋包含突出部25在内之導電圖案18的方式形成 被覆樹脂26後，從表面全面地蝕刻被覆樹脂％。透過本 工序’、设置於導電圖案18之突出部25即自被覆樹脂露出。 ^先，如第4圖（A)所示，以全面覆蓋包含突出部乃 之表面在内之導電圖案18的方式於電路基板16之表面形 成被覆樹脂26。被覆樹脂26之材料可採用熱硬化性樹脂 或熱可塑性樹脂。另外，被覆樹脂26之形成方法可採用使 片狀的樹脂片層疊之方法。另外，將液態或半固態之樹脂 ^布於电路基板16之表面，也可形成被覆樹脂％。另外， 被覆樹脂26之材料因考慮到後面之蝕刻工序，最好使用未 添加填料之樹脂。另外，即使在被覆樹脂％中混入填料的 情況，混人之填料之量也最好與絕緣層⑴目比為較少量。 因混入大量填料時，有可能會妨礙姓刻工序。另外，為均 勻進行後面之鞋刻，最好使被覆樹脂26之表面平坦化。 如第4圖⑻所示，接著藉由從表面蝕刻被覆樹脂26, 使突出部25之上面自被覆樹脂％露出。於本工序中，係 不使用㈣遮罩而對被覆樹脂26之表面全域進行均勾姓 刻。因此，伴隨姓刻之進行，突出部25之上面自被覆樹脂 317010 14 •200539408 26路出。於本工序中’考慮到蝕刻之偏差，可進行蝕刻直 至突出部25之側面露出。具體地說，在只進行到使突出部 2\之^面露出程度之蝕刻時，因為蝕刻存在偏差，所以有 •可=貫際上突出部25之上面並沒有露出。因此，於本實施 •形‘悲中’進仃被覆樹脂26之蝕刻直至突出部2 也露出，叫保突出部25之上面癌實露出。]面^ 參照第4圖（C)之立體圖說明透過本工序使 露出後之狀態。於該圖中，由被覆樹脂26被覆之部分的導 電圖案18以虛線表示。 如第4圖(C)所示，表面露出之突出部2 = 接區域’於本實施形態中將其統稱為焊塾。沿電路 心固二::==;，該等烊…係 以固定半導體元件:晶片烊墊UA係用 置之電路元件u相同:::::二焊塾，具有與預定載 ㈣係為了使用全屬面大小。另外，接合焊墊 出之桿墊。 與電路元件14電性連接而露 第卫序··於本工序中’進行電路元件之固定等。如 圖（A)所示，首先透過焊錫、 ： 固定於導雷円宏…一汗场V電糊專將電路元件14 之單元24//彳。攻晨’構成—個混合積體電路裝置 :::4係在一個電路基板16上形成複數 灯曰曰片烊接及打線接合。這裏，主動元件係以 （進 式安農，但亦可視需要而以晶面朝下方式安裳㈤月上方 參照第5圖⑻詳細說明如何透過焊料心 3)7010 15 -200539408 件14之固^。如上所述，於本實施形態卜可使突出部 匕之上面及側面均自被覆樹脂26露出。並且，此時為覆 =部25之上面及側面而附著焊料19。透過如此形成 ㈣19’可使焊料19之側面成為沒有縮頭部之光滑曲面。 透過該種形狀之焊料19可提高應對熱應力科力之可靠 如第5圖（〇所示，透過金屬細線15進行電路元件14 in:案、:8之電性連接。於本實施形態中’除電性連接 :置以外'導電圖案18之表面全部由被覆樹脂％加以被 後。因此，猎由本工序，即使在產生導電性粉塵時也可防 止因該粉塵之附著所致之導電圖案18之間之短路。 上述工序結束後’進行各單元24之分離。各單元之分 離可藉由使用衝床之衝切、㈣㈣進行 11固定於各單元之電路基板16。 肘q綠 、如第6圖所示’進行各電路基板16之樹脂密封。這裏， 透過使用熱硬化性樹脂之傳遞成型進行密封。亦即 路基板16收納於由上模3〇A及下模30B構成之模且3〇内 由使兩模具喃合而進行引線U之固定。’然後，透過 向杈穴31内注入樹脂而進行樹脂密封之工序。進行上述工 序後’製成第1圖所示之混合積體電路裝置。 [圖式簡單說明] 第1圖為本發明之電路裝 ⑻、剖視叫 ⑽裂置之立體圖⑷、剖視圖 第2圖為說明本發明之電路裝置之製造方法之剖_ 317010 16 •200539408 (A)至(E); 弟3圖為說明本發明之電路裝置之製造方法之剖 (A)至(F); 第4圖4言兒明本發明之電路裝置之製造方 法之剖視圖 (A)、剖視圖（B)、立體圖（〇 ; 第5圖為說明本發明之電路裝置之製造方法之剖視圖 (A)、剖視圖（B)、剖視圖（c); 第6圖為說明本發明之電路裝置之製造方法之剖視 圖；以及 第7圖為習知電路裝置之立體圖（A)、剖視圖（B)。 [主要元件符號說明] 10、100混合積體電路裝置 1卜 101引線 12、 102密封樹脂 13A 晶片焊塾 13B 接合焊墊 13C 焊墊 14、 104電路元件 15〜 105 金屬細線 16 電路基板 17、 10 7 絕緣層 18、 108導電圖案 18D 緣部 19 焊料 20 導電箔 21 阻劑 23 凹部 24 單元 25、 25A、25B 突出部 26、 109被覆樹脂 30 模具 30A 上模 30B 下模 31 模穴 106 基板 317010 17

Claims (1)

  1. -200539408 十、申請專利範圍： 】.一種電職置之製造方法，其特徵為包括： 將形成有向厚度方向突出之突出部 成於電路基板的表面之工序； 十电圖木形 以被覆前述導電圖案的方式於前述 面形成被覆樹脂之工序；以及 基板的表 藉由從表面蝕刻前述被覆樹脂而使 前述被覆樹脂露出之工序。 、大出邛自 2·如申凊專利耗圍第！項之電路裝置之製造方法，， 將電路元件電性連接於前述突出部。 〃 3· ^申請專利範圍第i項之電路裝置之製造方法，其 糟由從表面均勻去除前述被覆樹脂而使前述突出部露 出0 互 4·如申請專利範圍第i項之電路裝置之製造方法，其中， 進行前述蝕刻直至前述突出部之側面部分露出。、 • 5·=申請專利範圍第1項之電路裝置之製造方法，其中， 、这電路基板為由金屬構成之基板·’且將前述導電圖案 形成於以覆蓋前述電路基板的表面之方式形成之絕緣 JLL·. <4- _ ^ 317010 18
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JP2005347356A (ja) 2005-12-15
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CN100413029C (zh) 2008-08-20
US20050263482A1 (en) 2005-12-01
KR20060049442A (ko) 2006-05-19

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