1307143 丨之义 Ί 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種載板之製造方法’特別一種封裝用載 板之製造方法及其晶片封裝結構製造方法。 【先前技術】 按，半導體科技隨著電腦與網路通訊等產品功能急速提 昇，必需具備多元化、可攜性與輕薄微小化之需求，使晶片 封裝業必須朝高功率、高密度、輕、薄與微小化等高精密度 製程發展，除此之外，電子封裝（Electronics Packaging)仍需 具備高可靠度、散熱性佳等特性，以作為傳遞訊號、電能， 以及提供良好的散熱途徑及結構保護與支持等作用。 習知半導體封裝製程，係先於載板上製作導電線路後， 設置晶片，接著，電性連接晶片與導電線路，之後，利用封 裝體包覆上述元件後移除載板。為於導電線路上設置與外界 ，性接觸之凸塊，在導電線路上須預留導電線，以在欲焊接 ^位=仃電鍍金屬凸塊之流程。此種製造方法，於移除載板 =發生導電線外翻或因導電線殘留而影響電性之問 度。4問題都會影響到晶片封袭製程良率以及產品的信賴 提南製程良率及信賴度將 a 故，如何顧及簡化製作流程 是半導體產業—個重要議題。 【發明内容】 5 1307143 I年' ’片日修(¾正替換頁 '-—___ ___ 本發明目的之一係提供一種封裝用載板之製造方法及^ 晶片封裴結構製造方法，於載板中設置導熱層以改善封裝體散 熱不良之問題。 本發明目的之一係提供一種封裝用載板之製造方法及其 晶片封叢結構製造方法，於晶片封裝前先形成焊接層，因此在 設計電路時’不用預留導電線路給封裝完後之電鍍流程使 用，故可減少製程。 本發明目的之一係提供一種封裝用載板之製造方法及其 晶片封裝結構製造方法，除可減少製程之外，亦可增加電路設 計（layout)之彈性，此外，晶片封裝前預先形成焊接層，可避 免移除載板時導電線外翻之問題，亦無導電線殘留影響電性 之疑慮。 本發明目的之一係提供一種封裝用載板之製造方法及其 晶片封裝結構製造方法，於導熱層上做一超粗化處理，可增加 導熱層與封裝樹脂之鍵結力以提高封裝結構之信賴度。 為了達到上述目的，本發明一實施例之一種封裝用載板 製造方法，包括：提供一載板，其上設置一第一遮罩，其中 第一遮罩為圖案化遮罩以暴露出部分載板；蝕刻載板以形成 複數凹槽於暴露出之載板上；形成一焊接層於凹槽上；形成 一導熱層於凹槽上；設置一第二遮罩於載板上’其中第二遮 罩為圖案化遮罩以暴露出部份導熱層；形成一連接層於暴露 出之導熱層上；以及移除第一遮罩與第二遮罩。 為了達到上述目的，本發明又一實施例之一種晶片封裝 結構製造方法，包含：提供一載板，其上設置一第一遮罩， 其中第一遮罩為圖案化遮罩以暴露出部分載板；蝕刻载板以 形成複數凹槽於暴露出之載板；形成一焊接層於凹槽上；形 成一導熱層於凹槽上；設置一第二遮罩於載板上’其中第二 6 遮罩為圖案化遮罩以暴露出部份導熱層；形成一連接層於暴 露出之導熱層上；移除第一遮罩與第二遮罩；進行一晶片封 裝程序；以及移除載板。 為了達到上述目的，本發明又一實施例之一種封裝用載 板製造方法，包括：提供一載板，分別設置一第一遮罩及一 第三遮罩於載板之上表面及下表面，其中第一遮罩為圖案化 遮罩以暴露出部分載板；蝕刻載板以形成複數凹槽於暴露出 之載板；形成一焊接層於凹槽上；形成一導熱層於凹槽上； 分別設置一第二遮罩及一第四遮罩於載板之上表面及下表 面，其中第二遮罩為圖案化遮罩以暴露出部份導熱層；形成 一連接層於暴露出之導熱層；以及移除第一遮罩、第二遮罩、 第三遮罩與第四遮罩。 為了達到上述目的，本發明再一實施例之一種晶片封裝 結構製造方法，包括：提供一載板，分別設置一第一遮罩及 一第三遮罩於載板之上表面及下表面，其中第一遮罩為圖案 化遮罩以暴露出部分載板；蝕刻載板以形成複數凹槽於暴露 出之載板；形成一焊接層於凹槽上；形成一導熱層於凹槽上； 分別設置一第二遮罩及一第四遮罩於載板之上表面及下表 面，其中第二遮罩為圖案化遮罩以暴露出部份導熱層；形成 一連接層於暴露出之導熱層上；移除第一遮罩、第二遮罩、 第三遮罩與第四遮罩；進行一晶片封裝程序；以及移除載板。 【實施方式】 其詳細說明如下，所述較佳實施例僅做一說明非用以限 定本發明。 第1A圖、第1B圖、第1C圖、第1D圖、第1E圖、第 1F圖及第1G圖所示為根據本發明封裝用載板製造方法之第 1307143 I .； 一實施例之各步驟結構剖面示意圖。如第1A圖所示，首先， 提供一載板10,其上設置一第一遮罩20,其中第一遮罩20 為圖案化遮罩以暴露出部分載板10。接著，參考第1B圖， 以第一遮罩20為罩幕，蝕刻載板10以形成複數個凹槽12 於暴露出之載板10上。接著，請參閱第1C圖，形成一焊接 層30於凹槽12上，其中焊接層30可以是由錫、錫鉛、金鎳、 鎳鈀金或銀等金屬材質所構成。於一實施例中，焊接層30 係部分填滿凹槽12。之後，如第1D圖所示，形成一導熱層 40於凹槽12内之焊接層30上，其中導熱層40可以由銅、 鎳材質或其他散熱性佳之金屬所構成，導熱層40之設置可改 善散熱不良之問題。再來，請參考第1E圖，如圖所示，設 置一第二遮罩22於載板10上，其中第二遮罩22為圖案化遮 罩以暴露出部份導熱層40。接著，如第1F圖所示，以第二 遮罩22為罩幕，形成一連接層50於暴露出之導熱層40上， 連接層50之設置係用以其後做晶片封裝製程時與晶片做電 性連接。於一實施例中，連接層5 0可以是錫、錫錯、鎳金、 鎳IG金或銀等可供打線或表面黏著（surface mount technology, SMT)之材質所構成。最後，移除第一遮罩20與第二遮罩22, 此時封裝用載板之結構，如1G圖所示，載板10上含有複數 個凹槽12，其中焊接層30填滿並凸出凹槽12。導熱層40 設置於焊接層30上以增加封裝後之散熱效果。其中導熱層 40並可區分為一晶片承載區與一導電接點區。接著，連接層 50設置於導熱層40上以形成複數導電接點於晶片承載區與 導電接點區中，以方便其後與晶片電性連接。 接續上述說明，於一實施例中，第一遮罩20與第二遮 罩22為圖案化之光阻層，利用微影製程之方法透過第一遮罩 20上之開口可於載板10上蝕刻出凹槽12 ;以及，利用微影 製程之方法透過第二遮罩22上之開口可於導熱層40上形成 8 13071431307143 丨 义 九 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Prior Art] According to the rapid advancement of products such as computer and network communication, the need for diversification, portability, and miniaturization of semiconductor technology must make the chip packaging industry must be high-power, high-density, and light. In addition to the development of high-precision processes such as thinness and miniaturization, Electronics Packaging still needs to have high reliability and good heat dissipation characteristics to transmit signals, power, and provide good heat dissipation and structure. Protection and support. The conventional semiconductor packaging process is to form a wafer after the conductive line is formed on the carrier, and then electrically connect the wafer and the conductive line, and then the package is covered with the package to remove the carrier. In order to provide bumps on the conductive line that are in sexual contact with the outside, a conductive line must be reserved on the conductive line to be in the process of soldering the metal bumps. This manufacturing method is used to remove the carrier board = the occurrence of conductive wire eversion or the influence of electrical conductivity on the conductive line. 4 The problem will affect the yield of the chip encapsulation process and the trust of the product. The yield and reliability of the process will be improved. Therefore, how to take into account the simplified production process is an important issue in the semiconductor industry. SUMMARY OF THE INVENTION 5 1307143 I Year ''Picture Repair' (3⁄4 Positive Replacement Page'--______ One of the objects of the present invention is to provide a method for manufacturing a package for packaging and a method for manufacturing a wafer package structure on a carrier board The heat conducting layer is provided to improve the problem of poor heat dissipation of the package. One of the objects of the present invention is to provide a method for manufacturing a carrier for packaging and a method for manufacturing the same, which form a solder layer before the wafer is packaged, and thus design a circuit When the conductive circuit is not reserved for the plating process after the package is used, the process can be reduced. One of the objects of the present invention is to provide a method for manufacturing a package for packaging and a method for manufacturing the same, which can reduce the process. The flexibility of the circuit layout can also be increased. In addition, the solder layer is pre-formed before the wafer is packaged, which avoids the problem of the eversion of the conductive line when the carrier is removed, and has no doubt that the residual of the conductive line affects the electrical property. One is to provide a method for manufacturing a carrier board for packaging and a method for manufacturing the same, and to perform an over-roughening treatment on a heat conductive layer to increase heat conduction The bonding force with the encapsulating resin is used to improve the reliability of the package structure. In order to achieve the above object, a method for manufacturing a carrier board for packaging according to an embodiment of the invention includes: providing a carrier board on which a first mask is disposed, Wherein the first mask is a patterned mask to expose a portion of the carrier; the carrier is etched to form a plurality of recesses on the exposed carrier; a solder layer is formed on the recess; and a thermally conductive layer is formed on the recess Providing a second mask on the carrier board, wherein the second mask is a patterned mask to expose a portion of the heat conducting layer; forming a connecting layer on the exposed heat conducting layer; and removing the first mask and The second mask is a method for manufacturing a chip package structure according to another embodiment of the present invention, comprising: providing a carrier board on which a first mask is disposed, wherein the first mask is a patterned mask To expose a portion of the carrier; etching the carrier to form a plurality of recesses on the exposed carrier; forming a solder layer on the recess; forming a thermally conductive layer on the recess; and providing a second mask on the carrier 'The second 6 masks are for the picture Forming a mask to expose a portion of the thermally conductive layer; forming a tie layer on the exposed thermally conductive layer; removing the first mask and the second mask; performing a wafer packaging process; and removing the carrier. In a further aspect of the present invention, a method for manufacturing a carrier for a package includes: providing a carrier, respectively disposed with a first mask and a third mask on the upper surface and the lower surface of the carrier, wherein a mask is patterned to expose a portion of the carrier; the carrier is etched to form a plurality of recesses on the exposed carrier; a solder layer is formed on the recess; a thermally conductive layer is formed on the recess; a second mask and a fourth mask are disposed on the upper surface and the lower surface of the carrier, wherein the second mask is a patterned mask to expose a portion of the heat conducting layer; and a connecting layer is formed on the exposed heat conducting layer; And removing the first mask, the second mask, the third mask, and the fourth mask. In order to achieve the above object, a method for manufacturing a chip package structure according to another embodiment of the present invention includes: providing a carrier board, respectively Set a first mask and a third Covering the upper surface and the lower surface of the carrier, wherein the first mask is a patterned mask to expose a portion of the carrier; the carrier is etched to form a plurality of recesses on the exposed carrier; forming a solder layer in the recess Forming a heat conducting layer on the groove; respectively providing a second mask and a fourth mask on the upper surface and the lower surface of the carrier, wherein the second mask is a patterned mask to expose a portion of the heat conduction a layer; forming a connection layer on the exposed heat conduction layer; removing the first mask, the second mask, the third mask, and the fourth mask; performing a wafer packaging process; and removing the carrier. [Embodiment] The detailed description is as follows, and the preferred embodiment is not intended to limit the invention. 1A, 1B, 1C, 1D, 1E, 1F, and 1G are the 1307143 I of the method for manufacturing a carrier for packaging according to the present invention; Schematic diagram of the step structure. As shown in FIG. 1A, first, a carrier 10 is provided on which a first mask 20 is disposed, wherein the first mask 20 is a patterned mask to expose a portion of the carrier 10. Next, referring to FIG. 1B, with the first mask 20 as a mask, the carrier 10 is etched to form a plurality of grooves 12 on the exposed carrier 10. Next, referring to Fig. 1C, a solder layer 30 is formed on the recess 12, wherein the solder layer 30 may be made of a metal material such as tin, tin-lead, gold-nickel, nickel-palladium-gold or silver. In one embodiment, the solder layer 30 partially fills the recess 12. Then, as shown in FIG. 1D, a heat conducting layer 40 is formed on the solder layer 30 in the recess 12, wherein the heat conducting layer 40 may be made of copper, nickel or other heat dissipating metal, and the heat conducting layer 40 may be disposed. Improve the problem of poor heat dissipation. Referring again to FIG. 1E, as shown, a second mask 22 is disposed on the carrier 10, wherein the second mask 22 is a patterned mask to expose a portion of the thermally conductive layer 40. Next, as shown in FIG. 1F, a second mask 22 is used as a mask to form a connection layer 50 on the exposed heat conduction layer 40. The connection layer 50 is disposed for the wafer package process and the wafer. Make an electrical connection. In one embodiment, the connection layer 50 may be made of tin, tin, nickel, nickel, IG gold or silver for surface mounting or surface mount technology (SMT). Finally, the first mask 20 and the second mask 22 are removed. At this time, the structure of the package carrier is as shown in FIG. 1G. The carrier 10 includes a plurality of grooves 12, wherein the solder layer 30 is filled and convex. The groove 12 is out. The heat conductive layer 40 is disposed on the solder layer 30 to increase the heat dissipation effect after packaging. The heat conductive layer 40 can be divided into a wafer carrying area and a conductive contact area. Next, the connection layer 50 is disposed on the heat conduction layer 40 to form a plurality of conductive contacts in the wafer carrying region and the conductive contact region to facilitate subsequent electrical connection with the wafer. Following the above description, in an embodiment, the first mask 20 and the second mask 22 are patterned photoresist layers, and the openings on the first mask 20 can be applied to the carrier 10 by a lithography process. Etching the recess 12; and forming a 1 1307143 on the thermally conductive layer 40 through the opening in the second mask 22 by means of a lithography process
^^7]―日修(妁正替換頁I i ________j 連接層50。但第一遮罩20與第二遮罩22並i限於此，於又 一實施例中，第一遮罩20與第二遮罩22也可以是圖案化模 板，於同樣圖案設計之製程中，圖案化模板可重複使用，減 少製程及生產成本。 於一實施例中，形成焊接層30、導熱層40及連接層50 之方法，可以是利用電鍍法和無電解電鍍法其中之任一所成 形。且，在形成連接層50之前，更可進行一超粗化處理來增 加導熱層40和其後封裝樹脂之間的鍵結力，以提高製程信賴 度。^^7]―日修(妁正换页 I i ________j connection layer 50. However, the first mask 20 and the second mask 22 are limited thereto, and in still another embodiment, the first mask 20 and the first The second mask 22 can also be a patterned template. In the same pattern design process, the patterned template can be reused to reduce the process and production cost. In one embodiment, the solder layer 30, the heat conductive layer 40 and the connection layer 50 are formed. The method may be formed by any one of an electroplating method and an electroless plating method, and an ultra-roughening treatment may be further performed before the formation of the connection layer 50 to increase the space between the heat conductive layer 40 and the encapsulating resin thereafter. Bonding force to improve process reliability.
第2A圖、第2B圖、第2C圖、第2D圖、第2E圖及第 2F圖所示為根據本發明封裝用載板製造方法之第二實施例 之各步驟結構剖面示意圖。如第2A圖所示，首先，提供一 载板10,分別設置一第一遮罩20及一第三遮罩60於載板10 之上表面及下表面，其中第一遮罩20為圖案化遮罩以暴露出 部分載板10。接著，參考第2B圖，以第一遮罩20為罩幕， 蝕刻載板10以形成複數個凹槽12於暴露出之載板10。接 著，請參閱第2C圖，形成一坪接層30於凹槽12上。於一 實施例中，焊接層30係部分填滿凹槽12。之後，如第2D圖 所示，形成一導熱層40於凹槽12内之焊接層30上，導熱層 40之設置係可改善散熱不良之問題。再來，請參考第2E圖， 如圖所示，分別設置一第二遮罩22及一第四遮罩62於載板 10上，其中第二遮罩22為圖案化遮罩以暴露出部份導熱層 40。接著，如第2F圖所示，以第二遮罩22為罩幕，形成一 連接層50於暴露出之導熱層40上，連接層50之設置係用以 其後做晶片封裝製程時電性連接晶片用。於一實施例中，連 接層50可以是錫、錫鉛、鎳金、鎳鈀金或銀等可供打線或 SMT之材質所構成。最後，移除第一遮罩20、第二遮罩22、 第三遮罩60及第四遮罩62。此時封裝用載板之結構，如1G 9 圖所示，與上一實施例相同，載板10上含有複數凹槽12， 其中焊接層30填滿並凸出凹槽12,其中焊接層30可以是由 錫、錫錯、金鎳、錄纪金或銀材質所構成。導熱層40，例如 銅、鎳材質或其他散熱性佳之金屬所構成，設置於焊接層30 上以增加封裝後之散熱效果。其中導熱層40並可區分為一晶 片承載區與一導電接點區。接著，連接層50設置於導熱層 40上以形成複數導電接點於晶片承載區與導電接點區中，以 方便其後與晶片電性連接，其中連接層30可以是由錫、錫 錯、鎳金、鎳把金或銀材質所構成。 接續上述說明，於一實施例中，第一遮罩20及第二遮 罩22為圖案化之光阻層，利用微影製程之方法透過第一遮罩 20上之開口可於載板10上蝕刻出凹槽12 ;以及，利用微影 製程之方法透過第二遮罩22上之開口可於導熱層40上形成 連接層50。但本發明並不限於此，於又一實施例中，第一遮 罩20及第二遮罩22也可以是圖案化模板，於同樣圖案設計 之製程中，圖案化模板可重複使用，減少製程及生產成本。 於一實施例中，第三遮罩60及第四遮罩62亦可為圖案化光 阻層或是圖案化模板，以對載板10進行雙面製程作業。 與上一實施例相同，形成焊接層30、導熱層40及連接 層50之方法，可以是利用電鍍法和無電解電鍍法其中之任一 所成形。且，亦可在形成連接層50之前，進行一超粗化處理 來增加導熱層40和其後封裝樹脂之間的鍵結力，以提高製程 信賴度。 第3A圖及第3B圖所示為根據本發明晶片封裝結構製造方 法於晶片封裝後一實施例之結構剖面示意圖。於此實施例 中，於封裝用載板製造完成前之步驟與第一實施例相同，此 處即不再贅述。在封裝用載板製造步驟中，移除第一遮罩與 10 1307143 Γ 97.12.0 4 : 叹 第二遮罩後，進行一晶片封裝程序，請參考第3Α圖，於此 實施例中，晶片封裝程序包括：以適當方式設置一晶片70 於導熱層40或連接層50上，接著，利用焊線電性連接晶片 70與連接層50，最後，利用灌模方式形成一封裝膠體80， 例如環氧樹脂（epoxy)，包覆晶片70、導熱層40、連接層50 與部分焊接層30，如凸出載板10之部分。接著，在形成封 裝膠體80後，移除載板10以形成如第3B圖所示之晶片封 裝結構。如圖所示，移除載板10之後，焊接層30係部分包 覆於封裝膠體80内且部分凸出封裝膠體80，其中凸出封裝 膠體80之部分焊接層30係方便其後與其他電子裝置電性連 接。由於焊接層30較以往附著面積大以增加其附著力，可改 善晶片對於系統運作之可靠度（board level reliability )。 接續上述說明，由於焊接層30已先以電鍍法或無電解 電鍍法設置於載板10上，故於移除載板10之後，不須在進 行電鍍流程，可減少製程。又，於一實施例中，於導熱層40 形成之後，亦可進行一超粗化處理以增加導熱層40與封裝膠 體80之間的鍵結力，進而避免脫層的情況發生。 於又一實施例中，於封裝用載板製造完成前之步驟亦可 與第二實施例相同，其後進行晶片封裝程序與移除載板之動 作亦與上述說明相同，此處即不再重複描述。 依據上述，本發明的特徵之一係可利用圖案化薄膜或圖 案化模板作為遮罩進行蝕刻或材料塗佈，製程上相當彈性， 且對於相同圖案設計之載板製程，圖案化模板可重複使用， 以減少製造成本；又，本發明的特徵之一係於晶片封裝後無 須再進行電鍍流程，可減少製程步驟及其製作時間，另，由 於步驟的簡化，亦可減少製作的出錯機率。 1307143 r~V7：i2.ll-^ i千月s修(.¾正替狭貞j 綜合上述，本發明係提供一種封裝用載板之製造方法及 其晶片封裝結構製造方法，於載板中設置導熱層以改善封裝體 散熱不良之問題。又，於晶片封裝前先形成焊接層，因此在 設計電路時，不用預留導電線路給封裝完成後之電鍍流程使 用’故可減少製程《除此之外，亦可增加電路設計（layout) 之彈性’此外，晶片封裝前預先形成焊接層，可避免移除載 板時導電線外翻之問題，亦無導電線殘留影響電性之疑慮。 再者’於導熱層上做一超粗化處理，可增加導熱層與封裝樹 脂之鍵結力以提高封裝結構之信賴度。 以上所述之實施例僅係為說明本發明之技術思想及特 點’其目的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以實施，當不能以之限定本發明之專利範圍，即大凡依 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 發明之專利範圍内。 【圖式簡單說明】 第1A圖、第1B圖、第1C圖、第1D圖、第1E圖、第if圖及第沿 圖所示為根據本發明封裝用載板製造方法第一實施例之各步驟結 構剖面不意圖。 第2A圖 '第2B圖、第2C ®、第2D圖、第2E圖及第2F圖所示為 ΪΪΪ發明封裝用載板製造方法之第二實施例之各步驟結構剖面 第3Α圖及第3β圖所示為根 封裝後-實施例之結構剖面示意圖。曰片 封裝結構製造方法於晶 片 【主要元件符號說明】 10 12 載板 凹槽 12 1307143 *'.......,.. A ' ..i:"齡:. 20 第一遮罩 22 第二遮罩 30 焊接層 40 導熱層 50 連接層 60 第三遮罩 62 第四遮罩 70 晶片 80 封裝膠體 132A, 2B, 2C, 2D, 2E, and 2F are schematic cross-sectional views showing the steps of the second embodiment of the method for manufacturing a carrier for packaging according to the present invention. As shown in FIG. 2A, first, a carrier 10 is provided, and a first mask 20 and a third mask 60 are respectively disposed on the upper surface and the lower surface of the carrier 10, wherein the first mask 20 is patterned. The mask is exposed to expose a portion of the carrier 10. Next, referring to FIG. 2B, with the first mask 20 as a mask, the carrier 10 is etched to form a plurality of grooves 12 on the exposed carrier 10. Next, referring to Fig. 2C, a gusset 30 is formed on the recess 12. In one embodiment, the solder layer 30 partially fills the recess 12. Thereafter, as shown in Fig. 2D, a thermally conductive layer 40 is formed on the solder layer 30 in the recess 12, and the arrangement of the thermally conductive layer 40 improves the problem of poor heat dissipation. Referring to FIG. 2E, as shown, a second mask 22 and a fourth mask 62 are respectively disposed on the carrier 10, wherein the second mask 22 is a patterned mask to expose the portion. Thermal conductive layer 40. Next, as shown in FIG. 2F, the second mask 22 is used as a mask to form a connection layer 50 on the exposed heat conduction layer 40. The connection layer 50 is disposed for subsequent electrical processing in the wafer packaging process. Used to connect wafers. In one embodiment, the connection layer 50 may be made of tin, tin-lead, nickel-gold, nickel-palladium-gold or silver, or the like. Finally, the first mask 20, the second mask 22, the third mask 60, and the fourth mask 62 are removed. At this time, the structure of the package carrier, as shown in FIG. 1G, is the same as the previous embodiment, the carrier 10 includes a plurality of grooves 12, wherein the solder layer 30 fills and protrudes the groove 12, wherein the solder layer 30 It can be made of tin, tin, gold, gold or silver. The heat conductive layer 40, for example, made of copper, nickel or other heat-dissipating metal, is disposed on the solder layer 30 to increase the heat dissipation effect after packaging. The heat conducting layer 40 can be divided into a wafer carrying area and a conductive contact area. Next, the connection layer 50 is disposed on the heat conduction layer 40 to form a plurality of conductive contacts in the wafer carrying region and the conductive contact region to facilitate subsequent electrical connection with the chip, wherein the connection layer 30 may be tin, tin, Nickel gold and nickel are made of gold or silver. Following the above description, in an embodiment, the first mask 20 and the second mask 22 are patterned photoresist layers, and the openings on the first mask 20 can be applied to the carrier 10 by a lithography process. The recess 12 is etched; and the connection layer 50 is formed on the thermally conductive layer 40 through the opening in the second mask 22 by a lithography process. However, the present invention is not limited thereto. In another embodiment, the first mask 20 and the second mask 22 may also be patterned templates. In the same pattern design process, the patterned template can be reused to reduce the process. And production costs. In one embodiment, the third mask 60 and the fourth mask 62 may also be a patterned photoresist layer or a patterned template to perform a two-sided process on the carrier 10. As in the previous embodiment, the method of forming the solder layer 30, the heat conductive layer 40, and the connection layer 50 may be formed by any one of electroplating and electroless plating. Further, an over-roughening treatment may be performed to increase the bonding force between the thermally conductive layer 40 and the post-encapsulation resin before the formation of the connection layer 50 to improve process reliability. 3A and 3B are cross-sectional views showing the structure of a wafer package structure manufacturing method according to an embodiment of the present invention after wafer package mounting. In this embodiment, the steps before the manufacturing of the package carrier is completed are the same as those of the first embodiment, and the details are not described herein again. In the package manufacturing step of the package, after removing the first mask and 10 1307143 Γ 97.12.0 4 : after smashing the second mask, perform a wafer packaging process, please refer to FIG. 3 , in this embodiment, the wafer The package process includes: disposing a wafer 70 on the heat conductive layer 40 or the connection layer 50 in an appropriate manner, and then electrically connecting the wafer 70 and the connection layer 50 by using a bonding wire, and finally, forming a package colloid 80, such as a ring, by filling. An epoxy, a coated wafer 70, a thermally conductive layer 40, a tie layer 50 and a portion of the solder layer 30, such as portions of the raised carrier 10. Next, after the encapsulant 80 is formed, the carrier 10 is removed to form a wafer package structure as shown in Fig. 3B. As shown, after the carrier 10 is removed, the solder layer 30 is partially covered in the encapsulant 80 and partially protrudes from the encapsulant 80, wherein a portion of the solder layer 30 protruding from the encapsulant 80 is convenient for subsequent electrons. The device is electrically connected. Since the solder layer 30 has a larger adhesion area than before to increase its adhesion, the board level reliability of the wafer can be improved. Following the above description, since the solder layer 30 has been previously provided on the carrier 10 by electroplating or electroless plating, after the carrier 10 is removed, the plating process is not required, and the process can be reduced. Moreover, in an embodiment, after the heat conductive layer 40 is formed, an ultra-roughening treatment may be performed to increase the bonding force between the heat conductive layer 40 and the encapsulant 80, thereby preventing delamination. In another embodiment, the steps before the manufacturing of the package carrier is completed may be the same as that of the second embodiment, and then the wafer packaging process and the removal of the carrier are the same as the above description, and no longer Repeat the description. According to the above, one of the features of the present invention is that the patterned film or the patterned template can be used as a mask for etching or material coating, which is quite flexible in the process, and the patterned template can be reused for the carrier process of the same pattern design. In order to reduce the manufacturing cost; one of the features of the present invention is that the electroplating process is not required after the wafer is packaged, the process steps and the fabrication time thereof can be reduced, and the error probability of the fabrication can be reduced due to the simplification of the steps. 1307143 r~V7: i2.ll-^ i thousand months s repair (.3⁄4 positive replacement narrow j) In summary, the present invention provides a method for manufacturing a package carrier and a method for manufacturing the same, in a carrier board The thermal conductive layer is provided to improve the problem of poor heat dissipation of the package. Moreover, the solder layer is formed before the wafer is packaged, so that the conductive circuit is not reserved for the plating process after the package is completed, so that the process can be reduced. In addition, the flexibility of the circuit layout can be increased. In addition, a solder layer is formed in advance before the package is packaged, which avoids the problem of the conductive line eversion when the carrier board is removed, and there is no doubt that the conductive line residue affects the electrical property. 'Ultra-roughening treatment on the heat-conducting layer can increase the bonding force between the heat-conducting layer and the encapsulating resin to improve the reliability of the package structure. The embodiments described above are only for explaining the technical idea and characteristics of the present invention' The purpose of the present invention is to enable those skilled in the art to understand the scope of the present invention and the scope of the invention is not limited thereto. Variations or modifications are still to be covered by the scope of the present invention. [Simplified Schematic] FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, FIG. 1E, FIG. The cross-sectional structure of each step of the first embodiment of the method for manufacturing a carrier for packaging according to the present invention is not intended. FIG. 2A's FIG. 2B, 2C, 2D, 2E, and 2F show the invention. FIG. 3 is a cross-sectional view showing the structure of each step of the second embodiment of the method for manufacturing a package, and FIG. 3 is a schematic cross-sectional view of the structure after the package is mounted. The method for manufacturing the package structure of the wafer is described on the main component. 】 10 12 Carrier groove 12 1307143 *'..,.. A ' ..i:" Age: 20 First mask 22 Second mask 30 Solder layer 40 Thermal layer 50 Connection Layer 60 third mask 62 fourth mask 70 wafer 80 encapsulant 13