CN110718529A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

Info

Publication number
CN110718529A
CN110718529A CN201910626207.2A CN201910626207A CN110718529A CN 110718529 A CN110718529 A CN 110718529A CN 201910626207 A CN201910626207 A CN 201910626207A CN 110718529 A CN110718529 A CN 110718529A
Authority
CN
China
Prior art keywords
semiconductor chip
conductive
wiring layer
heat
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910626207.2A
Other languages
Chinese (zh)
Inventor
胁坂伸治
河野一郎
冈田修
福岛正人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aoi Electronics Co Ltd
Original Assignee
Aoi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aoi Electronics Co Ltd filed Critical Aoi Electronics Co Ltd
Publication of CN110718529A publication Critical patent/CN110718529A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a semiconductor device configured by stacking a plurality of semiconductor chips, when heat dissipation from the semiconductor chips is insufficient, the operation is unstable due to heat. A semiconductor device (80) is provided with: a wiring layer (22); a first semiconductor chip (25) having a main surface connected to the wiring layer (22) via a first connection section (28); a plurality of conductive posts (24) arranged outside the first semiconductor chip (25) in plan view and extending in a direction perpendicular to the wiring layer (22); a heat-conducting member (30) connected to the back surface of the first semiconductor chip (25) on the side opposite to the main surface and at least one (24G) of the plurality of conductive posts; a sealing resin (29) in contact with the surface other than the back surface of the first semiconductor chip, the wiring layer, and the side surface of the conductive post; and a second semiconductor chip (125) connected to an end portion of the conductive post on the side opposite to the wiring layer via a second connection portion (71).

Description

Semiconductor device and method for manufacturing semiconductor device
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
Background
In order to improve the mounting efficiency of semiconductor components to electronic devices and to improve the performance of electronic devices, semiconductor components (semiconductor devices) in which a plurality of semiconductor packages including semiconductor chips are stacked have been used. (see patent document 1)
Documents of the prior art
Patent document 1: U.S. patent application publication No. 2017/294422 specification
Disclosure of Invention
Problems to be solved by the invention
Since the power consumed by the semiconductor chip during operation is converted into heat, the semiconductor chip needs to be sufficiently radiated in order to stably operate the semiconductor chip. Patent document 1 discloses a technique of forming a heat conductor on the back surface of a semiconductor chip. However, when the heat conductor is formed only on the back surface of the stacked semiconductor chips, even if heat is transferred from the semiconductor chips to the heat conductor, the heat is not sufficiently dissipated from the heat conductor to other portions. Therefore, heat dissipation from the semiconductor chip is insufficient, and it is difficult to stably operate the semiconductor chip and the semiconductor product.
The semiconductor device of the present invention includes: a wiring layer; a first semiconductor chip having a main surface connected to the wiring layer via a first connection portion; a plurality of conductive posts which are arranged outside the first semiconductor chip in a plan view and extend in a direction perpendicular to the wiring layer; a heat conductive member connected to a back surface of the first semiconductor chip on a side opposite to the main surface and at least one of the plurality of conductive posts; a sealing resin which is in contact with a surface other than the back surface of the first semiconductor chip, the wiring layer, and a side surface of the conductive post; and a second semiconductor chip connected to an end portion of the conductive post on a side opposite to the wiring layer via a second connection portion.
The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a wiring layer; forming a plurality of conductive posts extending in a direction perpendicular to the wiring layer; preparing a first semiconductor chip, and bonding a main surface of the first semiconductor chip to the wiring layer via a first connection portion; resin-sealing the first semiconductor chip, the wiring layer, and the conductive post; polishing a sealing resin formed by the resin sealing to a height of a back surface of the first semiconductor chip on a side opposite to the main surface and an end surface of the conductive post on a side opposite to the wiring layer; forming a heat-conducting member connecting the back surface of the first semiconductor chip and at least one of the plurality of conductive posts; and connecting the second semiconductor chip to the end surface of the conductive post via a second connection portion.
The effects of the invention are as follows.
According to the present invention, the heat generated by the semiconductor chip is conducted to the conductive post via the heat conductive member, whereby the semiconductor chip and the semiconductor device can be efficiently cooled.
Drawings
Fig. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and is a diagram illustrating a first half of the steps.
Fig. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and is a diagram illustrating steps subsequent to fig. 1.
Fig. 3 is a diagram for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, and is a diagram showing steps subsequent to fig. 2.
Fig. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, and is a diagram illustrating steps subsequent to fig. 3.
Fig. 5 is a diagram for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, and is a diagram showing steps subsequent to fig. 4.
In the figure:
80-semiconductor device, 10-supporting substrate, 11-peeling layer, 12-thin copper layer, 14-lower layer pad (wiring layer), 15-lower layer wiring (wiring layer), 17-interlayer wiring (wiring layer), 20a, 20 b-upper layer pad (wiring layer), 16-interlayer insulating film, 22-wiring layer, 24-conductive terminal, 25 a-first semiconductor chip, 28-first junction, 29, 129-sealing resin, 30-heat conducting member, 71-second junction, 125-second semiconductor chip, 32, 132-solder ball.
Detailed Description
(one embodiment)
Fig. 1 to 5 are diagrams for explaining a method for manufacturing a semiconductor device 80 according to an embodiment of the present invention. Although fig. 1 to 5 show a process for manufacturing one semiconductor device 80 described below, the support substrate 10 may be a larger substrate than the semiconductor device 80, and a plurality of semiconductor devices 80 (more precisely, the intermediate product 50 described below) may be formed in an array on the support substrate 10.
(supporting substrate)
Fig. 1 (a) is a view showing a cross section of a support substrate 10 for manufacturing a semiconductor device 80, and a peeling layer 11 and a thin copper layer 12 are formed on an upper surface of the support substrate 10 in this order from the support substrate 10 side. The support substrate 10 is made of glass, for example, and the thickness of the support substrate 10 is preferably about 100 to 2000 μm.
In each of fig. 1 (a) and the following drawings, for ease of understanding, the length of the direction (vertical direction in the drawing) perpendicular to the surface of the support substrate 10 is drawn in an enlarged manner with respect to the in-plane direction (horizontal direction in the drawing) of the support substrate 10.
In each of the drawings after fig. 1 (b), a part of the thickness of the support substrate 10 is omitted.
In view of ease of peeling and film formability, the peeling layer 11 is preferably a layer mainly containing carbon, and the thickness of the peeling layer 11 is preferably about 1 to 20 nm. The release layer 11 may include a layer containing a metal in addition to a layer containing carbon as a main component.
The thin copper layer 12 is a layer having a thickness of about 50 to 2000nm and mainly composed of copper.
When the support substrate 10 formed with the peeling layer 11 or the like suitable for the above conditions is sold, it can be purchased and used.
(formation of Wiring layer)
Fig. 1 (b) shows a state in which a lower layer pad 14 and a lower layer wiring 15 are formed on a thin copper layer 12 as the uppermost layer on a support substrate 10. When the lower layer pad 14 and the lower layer wiring 15 are formed, first, the photoresist 13 is formed on the entire surface of the thin copper layer 12, and a desired opening corresponding to the shape of the lower layer pad 14 and the lower layer wiring 15 is formed in the photoresist layer. The supporting substrate 10 is immersed in a plating solution and subjected to copper electroplating, whereby the exposed portion of the thin copper layer 12 (i.e., the opening of the photoresist 13) is plated with copper, thereby forming the lower pad 14 and the lower wiring 15. The lower layer wiring 15 is a wiring for connecting the plurality of lower layer pads 14 to each other. After that, the photoresist 13 is removed.
Fig. 1 (c) shows a state in which an interlayer insulating film 16 is formed on the support substrate 10 so as to cover the lower layer pad 14 and the lower layer wiring 15, and a through hole 16a is formed at a predetermined position of the interlayer insulating film 16.
The interlayer insulating film 16 is made of photosensitive polyimide or the like, and a predetermined portion of the interlayer insulating film 16 is irradiated with light trimmed by laser or the like to be exposed to light, and the polyimide is removed by development, thereby forming a through hole 16 a.
Fig. 1 (d) shows a state in which a plating seed layer 18 is formed on the surface of the interlayer insulating film 16, and a patterned photoresist 19 is formed on the plating seed layer 18.
The plating seed layer 18 is formed by forming a film of a metal such as copper on the support substrate 10 shown in fig. 1 (c) by a dry film forming method such as electroless plating or sputtering. The thickness of the seed crystal layer 18 is about 50 to 200 nm.
After the plating seed layer 18 is formed, a photoresist 19 is formed on the entire surface of the plating seed layer 18, and the photoresist 19 is exposed and developed, thereby patterning the photoresist 19 to form the photoresist 19.
The support substrate 10 in this state is immersed in a plating solution to perform copper electroplating, whereby the portion 19a where the plating seed layer 18 is exposed (i.e., the portion where the photoresist 19 is removed) is plated with copper. Also inside the through hole 16a shown in fig. 1 (c), as a plating seed layer 18, copper is filled by electroplating to form an interlayer wiring 17.
After that, the photoresist 19 is removed.
Fig. 1 (e) shows a state of the support substrate 10 after the photoresist 19 is removed. The portion 19a of the seed layer 18 where the photoresist 19 is removed in fig. 1 (d) is plated with a metal such as copper, and upper pads 20a and 20b and an upper wiring 21 are formed in this portion.
Here, the upper layer pad 20a is a pad to be connected to the first semiconductor chip 25 or the conductive post 24 described below, and may be connected to the lower layer pad 14 via the interlayer wiring 17. The upper layer pad 20b is connected to the lower layer pad 14 via the interlayer wiring 17. The upper layer wiring 21 is a wiring for connecting the plurality of upper layer pads 20a and 20b to each other.
In this specification, the lower pad 14, the lower wiring 15, the upper pads 20a and 20b, the upper wiring 21, and the interlayer wiring 17 are collectively or individually referred to as a wiring layer 22.
(formation of conductive post)
In comparison with the support substrate 10 in the state shown in fig. 1 (e), the dry film 23 is formed on the upper layer pads 20a and 20b, the upper layer wiring 21, and the plating seed layer 18, and the opening 23a is formed at a predetermined portion of the dry film 23.
Fig. 2 (a) shows a state where the dry film 23 and the opening 23a are formed.
The dry film 23 is formed by bonding a dry film sheet to the support substrate 10 on which the upper layer pad 20a and the like are formed. The dry film 23 is exposed by irradiating a predetermined position on the dry film 23 with light trimmed by laser or the like, developed, and the dry film 23 is partially removed, thereby forming an opening 23 a. The side surface of the opening 23a is formed substantially perpendicular to the surface of the dry film 23.
Fig. 2 (b) shows a state in which a conductive post 24 made of a low-resistance metal such as copper is formed inside the opening 23a of the dry film 23 so as to be in contact with the upper layer pad 20 a.
The support substrate 10 in the state shown in fig. 2 (a) is immersed in a plating solution, and plating is performed using the plating seed layer 18 as an electrode, whereby the conductive post 24 is formed on the upper layer pad 20a connected to the plating seed layer 18 by plating a low-resistance metal such as copper.
The metal constituting the conductive post 24 is not limited to copper, and may be a low resistance metal or alloy, and the resistivity thereof may be 100[ n Ω · m ] or less.
For example, the length (the length in the vertical direction in the drawing) of the conductive post 24 is about 150 μm to 500 μm.
After the conductive post 24 is formed, the dry film 23 is removed, and the plating seed layer 18 is additionally removed by etching. The plating seed layer 18 is etched using the upper layer pads 20a and 20b and the upper layer wiring 21 as an etching mask. At this time, the upper layer pads 20a and 20b and the upper layer wiring 21 are also slightly dissolved by etching. However, by making the thicknesses of the upper layer pads 20a, 20b and the upper layer wiring 21 thicker than the thickness of the plating seed layer 18 in advance, the plating seed layer 18 can be completely removed, and the upper layer pads 20a, 20b and the upper layer wiring 21 can be left.
Fig. 2 (c) shows the support substrate 10 in a state where the plating seed layer 18 is removed.
The conductive posts 24 are connected to the wiring layer 22 ( upper layer pads 20a, 20b, etc.) formed along the upper surface of the support substrate 10, and are formed extending in a direction perpendicular to the wiring layer 22 (upward in the drawing).
In addition, as described above, the support substrate 10 is a substrate larger than the semiconductor devices 80 described below, and when a plurality of semiconductor devices 80 are formed in an array on the support substrate 10, a plurality of structures of the conductive posts 24 and the wiring layers (the upper pads 20a, 20b, and the like) shown in fig. 2 (c) are formed in an array on the support substrate 10 in the number corresponding to the number of the semiconductor devices 80 to be formed.
(bonding of first semiconductor chip and resin sealing)
Fig. 3 (a) shows the support substrate 10 in a state where the first semiconductor chip 25a is bonded and sealed with the sealing resin 29.
The first semiconductor chip 25a is a semiconductor integrated circuit chip cut out from a silicon wafer, such as a logic circuit IC such as a CPU, a memory IC such as a DRAM, and the like.
As shown in fig. 3a, a connection post 26 and a solder 27 are formed in advance on a part of a main surface (a lower surface in fig. 3 a) of the first semiconductor chip 25a on which the semiconductor integrated circuit is formed, before bonding to the support substrate 10.
Further, if necessary, a barrier metal layer may be formed in advance between the connection post 26 and the solder 27.
In some cases, the connection post 26 may be omitted, and the upper layer pad 20a and the pad formed on the main surface of the first semiconductor chip 25a may be bonded together by the solder 27.
In this specification, the connection post 26, the solder 27, and the barrier metal layer added as necessary are referred to as a first connection portion 28, respectively or collectively.
Note that, since the connection post 26, the solder 27, and the barrier metal layer are formed on the first semiconductor chip 25a by a known method, the description thereof is omitted.
The first semiconductor chip 25a is bonded to the predetermined upper layer pad 20a by heat treatment with its main surface facing downward and aligned so that the connection post 26 and the solder 27 face each other. The bonding of the first semiconductor chip 25a can be performed using various flip chip mounters.
In addition, as described above, in the case where the structure in which the plurality of conductive posts 24 and the wiring layer 22 are formed in the array in the number corresponding to the number of the semiconductor devices 80 to be formed is formed on the support substrate 10, the plurality of first semiconductor chips 25a may be temporarily pressure-bonded by aligning the plurality of first semiconductor chips 25a with the corresponding upper-layer pads 20a, and then heat-treated to collectively bond the plurality of first semiconductor chips 25 a.
The support substrate 10 to which the first semiconductor chip 25a is bonded is resin-sealed. As the sealing resin 29, for example, a resin in which a filler such as silica is filled in an epoxy resin is used. When sealing is performed, a liquid resin is pressurized in a metal mold by a compression molding method. Further, the processing may be performed by transfer molding. Further, a resin in the form of a pellet or powder may be used.
The upper surface of the wiring layer 22 formed on the support substrate 10, the first semiconductor chip 25a, and the side surfaces and end surfaces of the conductive posts 24 are sealed with a sealing resin 29.
(polishing of sealing resin and first semiconductor chip)
The surface of the sealing resin 29 and the back surface (surface on the opposite side from the main surface) of the first semiconductor chip formed as described above are polished. For the polishing, an end face of the conductive post 24 on the side opposite to the wiring layer 22 (upper end side in fig. 3 a) is polished by mechanical polishing or mechanochemical polishing until exposed from the sealing resin 29.
Fig. 3 (b) shows a state of the support substrate 10 after polishing.
The thickness of the first semiconductor chip 25a before polishing is about 600 to 800 μm, and the thickness of the first semiconductor chip 25 after polishing is about 100 to 200 μm.
In addition, the first semiconductor chip 25 polished to about 100 to 200 μm before bonding may be bonded to the supporting substrate 10, instead of the first semiconductor chip 25a having a bonding thickness of 600 to 800 μm on the supporting substrate 10, and then polished. In this case, the polishing of the first semiconductor chip 25a on the support substrate 10 can be significantly reduced, the thickness of the sealing resin 29 can be reduced, and the time required for polishing the sealing resin 29 can be reduced.
(formation of Heat-conductive Member)
Fig. 4 (a) shows a cross-sectional view of the support substrate 10 on which the heat conductive member 30 is formed, and fig. 4 (b) shows a plan view thereof.
The heat-conducting member 30 is formed so as to be connected to at least one of the back surface (upper surface in a cross-sectional view) of the first semiconductor chip 25 and the plurality of conductive posts 24 formed around the first semiconductor chip 25 in a plan view.
In this specification, a plan view refers to a state in which the first semiconductor chip 25 is viewed from above from a side perpendicular to the main surface and opposite to the wiring layer 22.
The heat-conducting member 30 is made of a metal containing copper or titanium, for example, and is formed on the back surface of the first semiconductor chip 25, the upper surface of the sealing resin 29, and the upper surface of the conductive post 24 (the end surface on the side opposite to the wiring layer 22) by dry film formation such as sputtering. After the film formation, portions other than necessary portions are removed by a photolithography step, thereby forming the heat conductive member 30 that connects the back surface of the first semiconductor chip 25 and at least one of the conductive posts 24 (conductive post 24G).
Further, from the viewpoint of heat dissipation, the heat conductive member 30 need not cover the entire back surface of the first semiconductor chip 25, and it is sufficient to cover a certain degree of portion. However, from the viewpoint of sealing the first semiconductor chip 25, it is preferable to cover the entire back surface of the first semiconductor chip 25.
The heat conductive member 30 may be a heat conductive sheet made of silicone, acrylic, polyolefin, or the like. In this case, a heat conductive sheet may be attached to the back surface of the first semiconductor chip 25 and the conductive post 24, and unnecessary portions may be cut off by photolithography, a laser cutter, or the like to have a desired shape as shown in fig. 4 (b).
The heat generated in the first semiconductor chip 25 is transferred to the conductive post 24G via the heat conductive member 30, and is transferred from the conductive post 24G to a wiring substrate of an electronic apparatus on which a semiconductor device 80 described below is mounted via the wiring layer 22. Therefore, the heat generated by the first semiconductor chip 25 can be efficiently dissipated.
Hereinafter, the first semiconductor chip 25, the conductive post 24, the wiring layers 22(14, 20a, etc.), the interlayer insulating film 16, and the sealing resin 29 themselves, which are integrally sealed (held) by the sealing resin 29, are referred to as an intermediate product 50 together with the thermally conductive member 30.
(peeling of supporting substrate)
The support substrate 10 is peeled from the intermediate product 50 sealed with the sealing resin 29. For peeling the support substrate 10, first, the peripheral portion of the support substrate 10 is cut or the peripheral portion of the support substrate 10 is hollowed out on the sealing resin 29 side, and the peeling layer 11 is exposed at the cut portion or the cross section of the hollowed-out portion. Then, a metal blade having a blade edge is pressed against the peeling layer 11 exposed in the cross section, and the support substrate 10 is peeled from the intermediate product 50 by moving the blade in the in-plane direction of the support substrate 10 while cracking the peeling layer 11.
After the support substrate 10 is peeled, the peeling layer 11 and the thin copper layer 12 remaining on the lower surface of the interlayer insulating film 16 are removed by etching.
When the peeling layer 11 and the thin copper layer 12 are etched, burrs that may be formed at the end of the conductive post 24 when the above-described polishing is performed may be removed at the same time.
In addition, as described above, when the plurality of semiconductor devices 80 are formed in an aligned manner on the support substrate 10, the shape of the cut portion or the dug portion in a plan view is preferably a shape that substantially follows the outer shape of the plurality of semiconductor devices 80 (the first semiconductor chip 25 and the like) formed on the support substrate 10, and this is preferable in that the area of the cut portion can be minimized.
That is, in the case where the external shape of the support substrate 10 is a quadrangle, and the plurality of first semiconductor chips 25 and the like are arranged in the quadrangle such that the external shape is substantially a quadrangle, it is desirable that the shape of the cut portion or the dug portion in a plan view be a quadrangle.
On the other hand, in the case where the supporting substrate 10 has a circular outer shape and a plurality of first semiconductor chips 25 and the like are arranged in the circular outer shape so as to be substantially circular, it is desirable that the cut portion or the dug portion have a circular shape in a plan view.
(formation of solder ball)
As shown in fig. 5 (a), a solder resist 31 is formed on the lower surfaces of the interlayer insulating film 16 and the lower layer pad 14. Then, the solder resist 31 is exposed by irradiating the position of the solder resist 31 corresponding to the lower layer pad 14 with light finished by laser or the like, and the solder resist 31 is partially removed by developing, thereby forming an opening and exposing the lower layer pad 14 at the opening.
Next, the solder ball 32 is mounted on the lower layer pad 14 exposed from the opening of the solder resist 31, and reflow soldering is performed by heating, so that at least a part of the solder ball 32 is melted, and the solder ball 32 is fixed to the lower layer pad 14.
Thereby, the first semiconductor package 60 is completed.
In addition, as described above, when a plurality of semiconductor devices 80 are formed in an array on the support substrate 10, the semiconductor devices 80 are cut (separated) into individual semiconductor devices 80 by using a dicing saw after the solder balls are formed.
In addition, the solder ball forming step described above may be omitted depending on the application of the semiconductor device 80 to be manufactured. At this time, the intermediate product 50 becomes the first semiconductor package 60.
(bonding of second semiconductor chip)
Fig. 5 (b) is a diagram showing a completed semiconductor device 80 in which the second semiconductor package 70 is bonded to the first semiconductor package 60 shown in fig. 5 (a).
The second semiconductor package 70 includes a second semiconductor chip 125, a connection post 126, solder 127, a second wiring layer 122, a sealing resin 129, a solder resist 131, a solder ball 132, and the like, as in the first semiconductor package 60 described above. The second semiconductor chip 125 is a semiconductor integrated circuit chip cut out from a silicon wafer, such as a logic circuit IC such as a CPU, a memory IC such as a DRAM, and the like. The second wiring layer 122 has lower layer pads 114, lower layer wirings 115, upper layer pads 120a, 120b, upper layer wirings 121, and interlayer wirings 117, as in the wiring layer 22 of the first semiconductor package 60 described above.
The manufacturing process of the second semiconductor package 70 is substantially the same as the manufacturing process of the first semiconductor package 60 described above, and therefore, the description thereof is omitted. However, in the second semiconductor package 70, the sealing resin 129 does not need to be polished until the rear surface (upper surface in the drawing) of the second semiconductor chip 125 is exposed, and the rear surface of the second semiconductor chip 125 is covered with the sealing resin 129.
The solder balls 132 of the second semiconductor package 70 are bonded to the end portions of the conductive posts 24 of the first semiconductor package 60 by heat treatment. Thereby, the wiring layer 22 of the first semiconductor package 60 is electrically connected to the second semiconductor chip 125 in the second semiconductor package 70.
In the present specification, the portion of the second semiconductor chip 125 electrically connected to the conductive post 24, that is, the connection post 126, the solder 127, the second wiring layer 122, and the solder ball 132 are collectively referred to as a second connection portion 71.
Further, in the case where the heat conductive member 30 is made of a conductive material, the solder ball 132 can be connected to the end portion of the conductive post 24G via the heat conductive member 30.
On the other hand, when the heat-conducting member 30 is made of a non-conductive material, the heat-conducting member 30 may be connected to the side surface (other than the end surface) of the conductive post 24G in advance, and then the solder ball 132 may be connected to the end portion of the conductive post 24.
In the case where the heat-conducting member 30 is made of a non-conductive material, an electrically conductive post 24G for conducting heat may be provided, and the non-conductive heat-conducting member 30 may be connected to the electrically conductive post 24G.
In any of the above cases, the conductive posts 24G connected to the thermally conductive member 30 are preferably connected to a wiring (wiring in the wiring layer 22) held at a ground potential.
At this time, since the potential of conductive post 24G is maintained at a constant value, the potential of the back surface of first semiconductor chip 25 is also maintained at a constant ground potential, and it is possible to prevent unnecessary electrical noise from being applied to first semiconductor chip 25.
The cross-sectional shape of the conductive post 24 may be circular as shown in fig. 4 (b), or may be rectangular including square.
Further, the conductive post 24 is formed along the inner shape of the opening 23a formed in the dry film 23. Therefore, even when the cross-sectional shape of the conductive post 24 is rectangular, the four corners thereof are rounded with a radius of curvature of a resolution limit of photolithography (exposure and etching) which is generally used to form the opening 23 a. Therefore, the rectangular cross-sectional shape of the conductive post 24 means a shape having a substantially rectangular cross-sectional shape, and includes a shape having a radius of curvature at four corners to the resolution limit of photolithography (exposure and etching).
If the cross-sectional shape is rectangular, even if there is an error in the alignment of conductive post 24 and solder ball 132 of second semiconductor package 70 and there is a positional deviation therebetween, the area of the joint portion can be increased compared to the case where the cross-sectional shape is circular, and the reliability of the joint can be increased. Further, since the sectional area of conductive post 24 is increased, the value of the resistance of conductive post 24 can be reduced.
(Effect of one embodiment)
(1) The semiconductor device 80 according to the above embodiment includes: a wiring layer 22; a first semiconductor chip 25 whose main surface is connected to the wiring layer 22 via a first connection portion 28; a plurality of conductive posts 24 arranged outside the first semiconductor chip 25 in a plan view and extending in a direction perpendicular to the wiring layer 22; a heat-conducting member 30 connecting a back surface of the first semiconductor chip 25 on the opposite side of the main surface to at least one (24G) of the plurality of conductive posts 24; a sealing resin 29 which is in contact with the surface other than the back surface of the first semiconductor chip 25, the wiring layer 22, and the side surfaces of the conductive posts 24; and a second semiconductor chip 125 connected to an end portion of the conductive post 24 on the opposite side from the wiring layer 22 via the second connection portion 71.
With this configuration, the heat generated in the first semiconductor chip 25, which is sealed and is difficult to dissipate to the surroundings, can be conducted to the circuit board on which the semiconductor device 80 is mounted via the heat-conducting member 30, the conductive post 24, the wiring layer 22, and the solder ball 32, and thus the heat can be efficiently dissipated (cooled). This enables the first semiconductor chip 25 to operate in a thermally stable state.
(2) In addition to (1), the back surface of the first semiconductor chip 25, the surface of the conductive post 24 opposite to the wiring layer 22, and the surface of the sealing resin 29 are on the same plane, and the heat-conducting member 30 is formed on the same plane, whereby the formation of the heat-conducting member 30 is facilitated, the heat-conducting path in the heat-conducting member 30 can be made shortest, and the heat-conducting efficiency can be improved.
(3) In addition to (1) or (2), by using a metal containing copper or titanium as the heat conductive member 30, the heat conductivity can be improved and the durability can be improved.
(4) In addition to (1) or (2), the heat-conductive member 30 is formed as a heat-conductive sheet, whereby the heat-conductive member 30 can be formed at low cost.
(5) In addition to any of (1) to (4), the conductive post 24G to which the thermally conductive member 30 is connected is set to a conductive post that transmits a ground potential, whereby the potential of the back surface of the first semiconductor chip 25 can be constantly maintained, and it is possible to prevent unwanted noise from being mixed into the first semiconductor chip 25.
(6) In addition to any of (1) to (5), by forming the cross-sectional shape of the conductive post 24 in a rectangular shape, even when there is an error in the alignment of the conductive post 24 and the solder ball 132 of the second semiconductor package 70 and a positional deviation occurs therebetween, the area of the joint portion can be increased compared to the case where the cross-sectional shape is circular, and the reliability of the joint can be improved.
(7) The method for manufacturing the semiconductor device 80 according to the above embodiment includes the steps of: forming a wiring layer 22; forming a plurality of conductive posts 24 extending in a direction perpendicular to the wiring layer 22; preparing a first semiconductor chip 25, and bonding a main surface of the first semiconductor chip 25 to the wiring layer 22 via a first connection portion 28; resin-sealing the first semiconductor chip 25, the wiring layer 22, and the conductive posts 24; polishing a sealing resin 29 formed by resin sealing to a height of a back surface of the first semiconductor chip 25 on a side opposite to the main surface and an end surface of the conductive post 24 on a side opposite to the wiring layer 22; forming a heat-conducting member 30 that connects the back surface of the first semiconductor chip 25 with at least one (24G) of the plurality of conductive posts 24; and connecting the second semiconductor chip 125 with the end face of the conductive post 24 via the second connection portion 71.
With this configuration, the heat generated in the first semiconductor chip 25, which is sealed and is difficult to dissipate to the surroundings, can be conducted to the circuit board on which the semiconductor device 80 is mounted via the heat-conducting member 30, the conductive post 24, the wiring layer 22, and the solder ball 32, and a semiconductor device that efficiently dissipates (cools) heat can be manufactured. That is, a semiconductor device in which the first semiconductor chip 25 is operated in a thermally stable state can be manufactured.
(8) In addition to (7), since the back surface of the first semiconductor chip 25a can be polished in the above polishing, the step of polishing the first semiconductor chip 25 before bonding to the support substrate 10 can be omitted.
(9) In addition to (7) or (8), the heat conductive member 30 can be formed by dry-film-forming a metal containing copper or titanium on the rear surface of the first semiconductor chip 25, the surface of the sealing resin 29, and the end surfaces of the conductive posts 24. By directly forming the film on the back surface of the first semiconductor chip 25 and utilizing the height of the adhesion, high heat dissipation performance and heat-resistant adhesion during heat generation can be improved.
(10) In addition to (7) or (8), the heat-conductive member 30 can be formed by attaching the heat-conductive sheet to the back surface of the first semiconductor chip 25 and the conductive posts 24, whereby the heat-conductive member 30 can be formed at low cost.
(11) In addition to any of (7) to (10), by connecting the heat conductive member 30 to a post (conductive post 24G) that transmits a ground potential among the plurality of conductive posts 24, the potential of the back surface of the first semiconductor chip 25 can be constantly maintained, and a semiconductor device in which unwanted noise is prevented from being mixed into the first semiconductor chip 25 can be manufactured.
In the above-described embodiment and modification, the wiring layer 22 is a double-layer wiring including the lower layer wiring 15 and the lower layer pad 14, the upper layer wiring 21 and the upper layer pads 20a and 20b, and the interlayer wiring 17, but the wiring layer 22 is not limited thereto, and may be a single-layer wiring. Alternatively, a wiring structure having three or more layers, such as an interlayer wiring, a top pad, and a top wiring, may be formed on the upper wiring 21 and the upper pads 20a and 20 b.
In addition, the semiconductor device may be formed by stacking a plurality of semiconductor packages over three or more stages, instead of stacking only two stages of the first semiconductor package 60 and the second semiconductor package 70. In this case, similarly to the first semiconductor package 60, the semiconductor package disposed in the intermediate layer preferably includes the heat conductive member 30 for connecting the rear surface of the semiconductor chip in the semiconductor package to at least one of the plurality of conductive posts.
In the above-described embodiment and modification, the wiring layer 22 is a double-layer wiring including the lower layer wiring 15 and the lower layer pad 14, the upper layer wiring 21 and the upper layer pads 20a and 20b, and the interlayer wiring 17, but the wiring layer 22 is not limited thereto, and may be a single-layer wiring. Alternatively, the wiring may be formed of three or more layers of wirings, such as an interlayer wiring, a top pad, and a top wiring, which are further formed on the upper layer wiring 21 and the upper layer pads 20a and 20 b.
The thicknesses (lengths in a direction perpendicular to the upper surface of the support substrate 10) of the lower layer pad 14, the lower layer wire 15, the upper layer pads 20a, 20b, the upper layer wire 21, and the interlayer wire 17 constituting the wiring layer 22 are about 1 μm to about 20 μm, respectively. Therefore, the entire wiring layer 22 has a thickness of about 5 μm to 100 μm.
On the other hand, the lateral width (length in the left-right direction in fig. 4 (c)) of the semiconductor device 80 is about 5mm to 20 mm. Therefore, the wiring layer 22 can be considered as a constituent on a flat plate thinner than the semiconductor device 80 as a whole, and the conductive posts 24 can be considered as extending in a direction perpendicular to the wiring layer 22.
The present invention is not limited to the above. Other modes considered to be within the scope of the technical idea of the present invention are also included in the scope of the present invention.

Claims (11)

1. A semiconductor device is characterized by comprising:
a wiring layer;
a first semiconductor chip having a main surface connected to the wiring layer via a first connection portion;
a plurality of conductive posts which are arranged outside the first semiconductor chip in a plan view and extend in a direction perpendicular to the wiring layer;
a heat conductive member connected to a back surface of the first semiconductor chip on a side opposite to the main surface and at least one of the plurality of conductive posts;
a sealing resin which is in contact with a surface other than the back surface of the first semiconductor chip, the wiring layer, and a side surface of the conductive post; and
and a second semiconductor chip connected to an end portion of the conductive post on a side opposite to the wiring layer via a second connection portion.
2. The semiconductor device according to claim 1,
the back surface of the first semiconductor chip, the surface of the conductive post opposite to the wiring layer, and the surface of the sealing resin are flush with each other,
the heat-conducting members are formed on the same plane.
3. The semiconductor device according to claim 1 or 2,
the heat conductive member is a metal containing copper or titanium.
4. The semiconductor device according to claim 1 or 2,
the heat conductive member is a heat conductive sheet.
5. The semiconductor device according to any one of claims 1 to 4,
the conductive post to which the heat conductive member is connected is a conductive post that transmits a ground potential.
6. The semiconductor device according to any one of claims 1 to 5,
the cross section of the conductive binding post is rectangular.
7. A method for manufacturing a semiconductor device, comprising:
forming a wiring layer;
forming a plurality of conductive posts extending in a direction perpendicular to the wiring layer;
preparing a first semiconductor chip, and bonding a main surface of the first semiconductor chip to the wiring layer via a first connection portion;
resin-sealing the first semiconductor chip, the wiring layer, and the conductive post;
polishing a sealing resin formed by the resin sealing to a height of a back surface of the first semiconductor chip on a side opposite to the main surface and an end surface of the conductive post on a side opposite to the wiring layer;
forming a heat-conducting member connecting the back surface of the first semiconductor chip and at least one of the plurality of conductive posts; and
the second semiconductor chip is connected to the end surface of the conductive post via a second connection portion.
8. The method for manufacturing a semiconductor device according to claim 7,
in the polishing, the back surface of the first semiconductor chip is also polished.
9. The method for manufacturing a semiconductor device according to claim 7 or 8,
the heat conductive member is formed by dry-film-forming a metal containing copper or titanium on the back surface of the first semiconductor chip, the surface of the sealing resin, and the end surface of the conductive post.
10. The method for manufacturing a semiconductor device according to claim 7 or 8,
the heat conductive member is formed by attaching a heat conductive sheet to the back surface of the first semiconductor chip and the conductive post.
11. The method for manufacturing a semiconductor device according to any one of claims 7 to 10,
the heat-conducting member is connected to a terminal which transmits a ground potential among the plurality of conductive terminals.
CN201910626207.2A 2018-07-12 2019-07-11 Semiconductor device and method for manufacturing semiconductor device Pending CN110718529A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-132564 2018-07-12
JP2018132564A JP7044653B2 (en) 2018-07-12 2018-07-12 Semiconductor devices and methods for manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
CN110718529A true CN110718529A (en) 2020-01-21

Family

ID=69152394

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910626207.2A Pending CN110718529A (en) 2018-07-12 2019-07-11 Semiconductor device and method for manufacturing semiconductor device

Country Status (3)

Country Link
JP (1) JP7044653B2 (en)
CN (1) CN110718529A (en)
TW (1) TWI825118B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802761A (en) * 2021-01-07 2021-05-14 山东傲天环保科技有限公司 Integrated circuit packaging structure and method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7556275B2 (en) 2020-02-20 2024-09-26 住友電気工業株式会社 Semiconductor device and its manufacturing method
JP7478336B1 (en) 2023-02-09 2024-05-07 株式会社Flosfia Composite Module Unit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343904A (en) * 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd Semiconductor device
US20100237495A1 (en) * 2009-03-17 2010-09-23 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
US20130154078A1 (en) * 2011-12-14 2013-06-20 Daesik Choi Integrated circuit packaging system with heat slug and method of manufacture thereof
JP2013182974A (en) * 2012-03-01 2013-09-12 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
CN104966702A (en) * 2014-03-28 2015-10-07 株式会社吉帝伟士 Semiconductor package

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100688501B1 (en) 2004-09-10 2007-03-02 삼성전자주식회사 Dual-Inline-Memory-Module mounted stack Board-On-Chip packages with mirroring structure
JP2009070882A (en) 2007-09-11 2009-04-02 Kyushu Institute Of Technology Semiconductor chip package and manufacturing method thereof
JP5218230B2 (en) 2009-04-06 2013-06-26 日本電気株式会社 Semiconductor device
US20140225248A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
KR101983185B1 (en) * 2016-08-19 2019-05-29 삼성전기주식회사 Fan-out semiconductor package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343904A (en) * 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd Semiconductor device
US20100237495A1 (en) * 2009-03-17 2010-09-23 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
US20130154078A1 (en) * 2011-12-14 2013-06-20 Daesik Choi Integrated circuit packaging system with heat slug and method of manufacture thereof
JP2013182974A (en) * 2012-03-01 2013-09-12 Fujitsu Semiconductor Ltd Semiconductor device and manufacturing method of the same
CN104966702A (en) * 2014-03-28 2015-10-07 株式会社吉帝伟士 Semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112802761A (en) * 2021-01-07 2021-05-14 山东傲天环保科技有限公司 Integrated circuit packaging structure and method
CN112802761B (en) * 2021-01-07 2022-07-08 深圳市慧邦电子科技有限公司 Integrated circuit packaging structure and method

Also Published As

Publication number Publication date
JP7044653B2 (en) 2022-03-30
TW202006909A (en) 2020-02-01
TWI825118B (en) 2023-12-11
JP2020010002A (en) 2020-01-16

Similar Documents

Publication Publication Date Title
US8410614B2 (en) Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same
US7364944B2 (en) Method for fabricating thermally enhanced semiconductor package
JP6669586B2 (en) Semiconductor device and method of manufacturing semiconductor device
US8294253B2 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure
TW201630147A (en) Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US20090321930A1 (en) Semiconductor with bottom-side wrap-around flange contact
CN109427658A (en) Mask assembly and method for manufacturing chip packaging piece
CN110718529A (en) Semiconductor device and method for manufacturing semiconductor device
JP7025948B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
JP2020136507A (en) Semiconductor device and manufacturing method of the same
JP2009516369A (en) Chip assembly and method of manufacturing the chip assembly
CN111613586B (en) Electronic device and method for manufacturing electronic device
US20040124516A1 (en) Circuit device, circuit module, and method for manufacturing circuit device
JP2004079716A (en) Chip size package type package for semiconductor and its manufacturing method
JP2019140145A (en) Semiconductor device and manufacturing method thereof
US20090194888A1 (en) Semiconductor device including wiring and manufacturing method thereof
TWI605556B (en) Smd, ipd, and/or wire mount in a package
US9935030B2 (en) Resin-encapsulated semiconductor device
JP4084737B2 (en) Semiconductor device
US7495345B2 (en) Semiconductor device-composing substrate and semiconductor device
JP2004006670A (en) Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
TWI472272B (en) Semiconductor package whose a dielectric layer formed from a photo-sensitive material and manufacturing method thereof
KR100239387B1 (en) Ball grid array semiconductor package and the manufacture method
US20230260883A1 (en) Interposer, circuit device, method of manufacturing interposer, and method of manufacturing circuit device
CN110707012A (en) Semiconductor device and method for manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination