KR101983185B1 - Fan-out semiconductor package - Google Patents

Abstract

In this disclosure, a semiconductor chip is disposed in a through hole of a first connection member having a through hole, a second connection member is disposed on an active surface of the semiconductor chip, and a plurality of dummy vias To a fan-out semiconductor package.

Description

[0001] FAN-OUT SEMICONDUCTOR PACKAGE [0002]

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package capable of extending a connection terminal to an area outside the area where the semiconductor chip is disposed.

One of the main trends of technology development related to semiconductor chips in recent years is to reduce the size of components. Accordingly, in the field of packages, it is required to implement a large number of pins with a small size in response to a surge in demand of small semiconductor chips and the like .

One of the proposed package technologies to meet this is the fan-out package. The fan-out package rewires the connection terminal to the area outside the area where the semiconductor chip is disposed, thereby enabling a small number of pins to be realized while having a small size.

SUMMARY OF THE INVENTION One of the objects of the present disclosure is to provide a fan-out semiconductor package having a structure capable of effectively implementing EMI (Electro Magnetic Interference) shielding.

One of the solutions proposed through the present disclosure is to introduce a connecting member having a through hole in which a semiconductor chip is disposed, and to form a dummy via, which can be EMI shielded separately from the signal via in the connecting member.

For example, a fan-out semiconductor package according to the present disclosure may include a first connection member having a through hole, an active surface disposed in the through hole of the first connection member and having a connection pad disposed thereon, A sealing member for sealing at least a part of the inactive surfaces of the first connecting member and the semiconductor chip and a second connecting member disposed on the active surface of the first connecting member and the semiconductor chip, Wherein the first connection member and the second connection member each include a re-wiring layer electrically connected to a connection pad of the semiconductor chip, the re-wiring layer of the first connection member includes a signal pattern and a ground pattern, The first connection member may include a plurality of dummy vias connected to the ground pattern and arranged to surround the semiconductor chip.

Alternatively, the fan-out semiconductor package according to the present disclosure may include a first connecting member having a through hole, an active surface disposed in the through hole of the first connecting member and having a connection pad disposed thereon, And a second connection member which is disposed on the active surface of the first connection member and the semiconductor chip and includes a re-wiring layer electrically connected to the connection pad of the semiconductor chip, The plurality of signal vias may include a plurality of signal vias and dummy vias that surround the plurality of signal vias or the plurality of dummy vias may be surrounded by the plurality of signal vias.

It is possible to provide a fan-out semiconductor package which can effectively perform electromagnetic shielding as one of various effects of the present disclosure and which further has a heat radiation effect.

1 is a block diagram schematically showing an example of an electronic equipment system.
2 is a perspective view schematically showing an example of an electronic apparatus.
3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.
4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.
6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.
7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.
8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.
9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.
FIG. 10 is a schematic top view of the fan-out semiconductor package of FIG. 9; FIG.
FIG. 11 is another schematic top view of the fan-out semiconductor package of FIG. 9; FIG.
FIG. 12 is another schematic top view of the fan-out semiconductor package of FIG. 9; FIG.
Fig. 13 schematically shows a modification of the fan-out semiconductor package of Fig.
Fig. 14 schematically shows another modification of the fan-out semiconductor package of Fig.
15 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
16 is a schematic elevational view II-II 'plan view of the fan-out semiconductor package of FIG.
FIG. 17 is another schematic II-II 'plan view of the fan-out semiconductor package of FIG. 15; FIG.
Figure 18 is another schematic II-II 'plan view of the fan-out semiconductor package of Figure 15;
19 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
20 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
21 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
22 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronics

1 is a block diagram schematically showing an example of an electronic equipment system.

Referring to the drawings, an electronic device 1000 accommodates a main board 1010. The main board 1010 is physically and / or electrically connected to the chip-related components 1020, the network-related components 1030, and other components 1040. They are also combined with other components to be described later to form various signal lines 1090.

Chip related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; An application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, Analog-to-digital converters, and logic chips such as application-specific integrated circuits (ICs), and the like, but it is needless to say that other types of chip-related components may be included. It goes without saying that these components 1020 can be combined with each other.

IEEE 802.11 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, as well as any other wireless or wired Any of the standards or protocols may be included. It goes without saying that the network-related component 1030 may be combined with the chip-related component 1020, as well.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser) But is not limited to, passive components used for various other purposes, and the like. It is also understood that other components 1040 may be combined with each other with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. Other components include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (Not shown), a CD (compact disk) (not shown), and a DVD (not shown), an accelerometer (not shown), a gyroscope a digital versatile disk (not shown), and the like. However, the present invention is not limited thereto, and other components used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is needless to say that the present invention is not limited thereto and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic apparatus.

Referring to the drawings, a semiconductor package is applied to various electronic apparatuses as described above for various purposes. For example, a main board 1110 is accommodated in the body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. Other parts, such as the camera 1130, which are physically and / or electrically connected to the main board 1110 or not, are contained within the body 1101. Some of the components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor, but is not limited thereto. It is needless to say that the electronic device is not necessarily limited to the smartphone 1100, but may be another electronic device as described above.

Semiconductor package

In general, a semiconductor chip has many microelectronic circuits integrated therein, but itself can not serve as a finished product of a semiconductor, and there is a possibility of being damaged by external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, and the semiconductor chip is packaged and used as electronic devices in a package state.

The reason for the necessity of semiconductor packaging is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small. On the other hand, in the case of the main board used in electronic equipment, the size of the component mounting pad and the interval between the component mounting pads are much larger than the scale of the semiconductor chip . Therefore, there is a need for a packaging technique which makes it difficult to directly mount a semiconductor chip on such a main board and can buffer the difference in circuit width between the semiconductor chips.

The semiconductor package manufactured by such a packaging technique can be classified into a fan-in semiconductor package and a fan-out semiconductor package depending on the structure and use.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)

3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.

4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

The semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; A connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222. [ May be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a medium-level printed circuit board (PCB) as well as a main board of an electronic apparatus.

A connection member 2240 is formed on the semiconductor chip 2220 in accordance with the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. [ The connecting member 2240 is formed by forming an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220 and forming a via hole 2243h for opening the connecting pad 2222, The wiring pattern 2242 and the via 2243 can be formed. Thereafter, a passivation layer 2250 for protecting the connecting member 2240 is formed, and an under-bump metal layer 2260 or the like is formed after the opening 2251 is formed. That is, through a series of processes, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260, do.

As described above, the fan-in semiconductor package is a package in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are disposed inside the element, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost have. Accordingly, many devices incorporated in a smart phone are manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in order to implement a small-sized and fast signal transmission.

However, in the fan-in semiconductor package, all of the I / O terminals must be disposed inside the semiconductor chip, so that there are many space limitations. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package can not be directly mounted on the main board of the electronic device. This is because even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have a size and a gap enough to be directly mounted on the electronic device main board.

5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.

6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.

Referring to the drawing, the fan-in semiconductor package 2200 is again rewired with the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals through the interposer substrate 2301, May be mounted on the main board 2500 of the electronic device with the fan-in semiconductor package 2200 mounted on the interposer substrate 2301. At this time, the solder ball 2270 and the like can be fixed with the underfill resin 2280 and the outside can be covered with the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the interposer substrate 2302 may be embedded in the connection pads 2220 of the semiconductor chip 2220, The I / O terminals 2222, i.e., the I / O terminals, may be re-routed again and finally mounted on the main board 2500 of the electronic device.

Since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic apparatus, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, And is mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.

In the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member 2120. [ The semiconductor chip 2120 is rewound to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connecting member 2140, and an under bump metal layer 2160 may be further formed on the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 may include an insulating layer 2141, a re-wiring layer 2142 formed on the insulating layer 2241, a via 2143 connecting the connecting pad 2122 and the re-wiring layer 2142, .

As described above, the fan-out semiconductor package is formed by rewiring the I / O terminals to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip. If the element size is reduced, the ball size and pitch must be reduced. On the other hand, in the fan-out semiconductor package, the I / O terminals are rewired to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip so that the size of the semiconductor chip is reduced. And can be mounted on a main board of an electronic device without a separate interposer substrate as will be described later.

8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes a connection member 2120 that can rewire the connection pad 2122 to the fan-out area beyond the size of the semiconductor chip 2120 on the semiconductor chip 2120, The standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of the electronic apparatus without a separate interposer substrate or the like.

Since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the thickness of the fan-out semiconductor package can be reduced compared to a fan-in semiconductor package using the interposer substrate. Do. In addition, it has excellent thermal characteristics and electrical characteristics and is particularly suitable for mobile products. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and it is possible to solve a problem caused by a bending phenomenon.

On the other hand, the fan-out semiconductor package means a package technology for mounting the semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from an external impact, and the scale, (PCB) such as an interposer substrate having a built-in fan-in semiconductor package.

Hereinafter, a fan-out semiconductor package capable of effectively shielding electromagnetic waves and further having a heat radiation effect will be described with reference to the drawings.

9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

FIG. 10 is a schematic top view of the fan-out semiconductor package of FIG. 9; FIG.

FIG. 11 is another schematic top view of the fan-out semiconductor package of FIG. 9; FIG.

FIG. 12 is another schematic top view of the fan-out semiconductor package of FIG. 9; FIG.

Referring to FIG. 1, a fan-out semiconductor package 100A according to an exemplary embodiment includes a first connection member 110 having a through hole 110H, a through hole 110H of the first connection member 110, The first connecting member 110 and the semiconductor chip 120 having the active surface on which the semiconductor chip 120 is disposed and the inactive surface disposed on the opposite side of the active surface, A first connection member 130 and a second connection member 140 disposed on the active surface of the semiconductor chip 120. The first connection member 110 includes re-wiring layers 122a, 122b, 122c, 114a, 114b, and 114c electrically connected to the connection pads 122 of the semiconductor chip 120. [ The second connection member 140 includes a re-wiring layer 142 electrically connected to the connection pad 122 of the semiconductor chip 120. The redistribution layers 122a, 122b, 122c, 114a, 114b, and 114c of the first connection member 110 include a signal pattern and a ground pattern. The first connection member 110 includes a plurality of dummy vias 115a and 115b connected to the ground pattern and arranged to surround the semiconductor chip 120. [ The first connection member 110 includes a plurality of signal vias 113a and 113b which are connected to the signal pattern and are surrounded by a plurality of dummy vias 115a and 115b. Meanwhile. The dummy of the dummy vias 115a, 115b means not for signal connection, i.e. for other ancillary functions. That is, the dummy vias 115a and 115b are electrically connected to the ground pattern, but may be insulated from the signal pattern.

Conventional semiconductor packages have limited EMI shielding. Therefore, shielding EMI was shielded by attaching a shield can to a semiconductor package having a large amount of EMI radiation. However, since EMI is shielded due to mounting of a shield can, reduction of mounting area and additional cost, noise between individual items in a shield can, EMI shielding, such as concentration of stress on the main board depending on the shield can mounting method, may cause the occurrence of incidental expenses and technical difficulties. In addition, despite increasing the number of high-speed signal transmission despite the installation of the shield can, EMI emission quantity of single product is continuously increased. Therefore, in order to meet the reception sensitivity required by actual communication companies, It was necessary to perform the above-mentioned operation. Accordingly, there is a demand for a structure and a method capable of effectively performing EMI shielding at a single product level of a semiconductor package.

The fan-out semiconductor package 100A according to the exemplary embodiment includes the EMI shielding dummy vias 115a and 115b on the first connection member 110 in the form of a wall along the outer rim of the first connection member 110 Is formed on the outer side (a) so as to surround the components of the inside (a) of the package 100A such as the semiconductor chip 120 and the signal vias 113a and 113b. This structure effectively shields EMI from shielding noise emissions at individual isolation levels without any additional process. In addition, the existing shield canning method can be eliminated or minimized, and the noise reduction method for improving the reception sensitivity at the set level can be performed at a single product level, thereby reducing the burden on the set design and verification. Particularly, since the dummy vias 115a and 115b are formed along the outer rim, EMI shielding generated in the re-wiring layers 112a, 112b, 112c, 114a, 114b, and 114c and the like can be efficiently performed. In this structure, the dummy vias 115a and 115b can perform the heat dissipation function, and the heat dissipation effect can also be improved. The dummy vias 115a and 115b can be connected to the ground patterns of the first connection member 110 and / or the second connection member 140, thereby further improving the design efficiency. Each of the plurality of dummy vias 115a and 115b may be spaced apart from each other by a predetermined distance or may be connected to each other through a plurality of line vias 116b. Alternatively, each of the plurality of dummy vias 115a and 115b may be overlapped with each other such that no voids are formed.

The exemplary fan-out semiconductor package 100A further includes a metal layer 132 disposed on the sealing material 130 and covering at least a portion of the non-active surface side of the semiconductor chip 120. Metal layer 132 is connected via via 133 to dummy vias 115a and 115b. In this structure, most of the surface of the semiconductor chip 120 is surrounded by the metal material. Therefore, it is possible to more effectively shield the EMI and to have a better heat radiation effect. The metal layer 132 may be formed by coating or plating a known metal material. If desired, the metal layer 132 may be utilized as a ground pattern. Therefore, the dummy vias 115a and 115b can be connected to the ground of the entire package 100A. The sealing material 130 has an opening 131 exposing a pad pattern connected to the signal vias 113a and 113b and the metal layer 132 exposes the opening 131. [ Thus, the metal layer 132 may not be connected to the signal vias 113a and 113b.

Hereinafter, each configuration included in the fan-out semiconductor package 100A according to the example will be described in more detail.

The first connection member 110 can maintain the rigidity of the package 100A according to a specific material and can play a role of ensuring uniformity of the thickness of the sealing material 130. [ The package 100A may be used as a part of a package on package (POP) by the first connecting member 110. [ The first connection member 110 includes rewiring layers 112a, 112b, 112c, 114a, 114b and 114c and can rewire the connection pads 122 of the semiconductor chip 120, It is possible to reduce the number of layers. In the through hole 110H, the semiconductor chip 120 is disposed to be spaced apart from the first connection member 110 by a predetermined distance. The periphery of the side surface of the semiconductor chip 120 may be surrounded by the first connection member 110. However, this is only an example, and the through hole 110H of the first connection member 110 may be modified in various forms, and other functions may be performed according to the shape thereof.

The first connecting member 110 includes a first insulating layer 111a, a second insulating layer 111b, a signal portion 110a, and a dummy portion 110b. The signal portion 110a is disposed on the inner side (a) of the first connection member 110. The dummy portion 110b is disposed on the outer side (b) of the first connecting member 110. [ The signal portion 110a includes a first signal via 113a passing through the first insulating layer 111a and a second signal via 113b passing through the second insulating layer 111b. The dummy portion 110b includes a first dummy via 115a penetrating the first insulation layer 111a and a second dummy via 115b penetrating the second insulation layer 111b. The signal portion 110a includes a first redistribution layer 112a, a second redistribution layer 112b, and a third redistribution layer 112c including a signal pattern, a signal via pad pattern, and the like. Which may be electrically connected through the first signal via 113a and the second signal via 113b. The dummy portion 110b includes a first redistribution layer 114a, a second redistribution layer 114b including a dummy pattern, a dummy via pad pattern, and the like, and a third redistribution layer 114c. These may be electrically connected through the first dummy via 115a and the second dummy via 115b. A power pattern, a pad pattern for a power via, and the like may be disposed on the inner side (a) of the first connection member 110 in addition to a signal pattern, a signal via pad pattern, and the like. . The ground pattern is not necessarily disposed only on the outer side b of the first connecting member 110 on which the dummy vias 115a and 115b are disposed and is formed on the inner side a of the dummy vias 115a and 115b .

The first rewiring layers 112a and 114a contact the second connection member 140 and are embedded in the first insulation layer 111a. The second rewiring layers 112b and 114b are disposed on the opposite side of the first insulating layer 111a on the side where the first redistribution layers 112a and 114a are embedded. The second insulating layer 111b is disposed on the first insulating layer 111a and covers the second redistribution layers 112b and 114b. The third redistribution layers 112c and 114c are disposed on the second insulating layer 111b. The first to third rewiring layers 112a, 112b, 112c, 113a, 113b, and 113c may be electrically connected to the connection pad 122. The insulation distance of the insulating layer 141 of the second connection member 140 can be substantially constant since the first rewiring layers 112a and 114a are buried. The first connection member 110 includes a large number of rewiring layers 112a, 112b, 112c, 114a, 114b, and 114c, and the second connection member 140 can be further simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the second linking member 140. The first rewiring layers 112a and 114a are recessed into the first insulation layer so that the lower surface of the first insulation layer 111a and the lower surfaces of the first rewiring layers 112a and 114a have step differences. As a result, it is possible to prevent the material for forming the sealing material 130 from being contaminated by contamination of the first rewiring layers 112a and 114a when the sealing material 130 is formed. The lower surfaces of the first rewiring layers 112a and 114a of the first connection member 110 may be located above the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the redistribution layer 142 of the second connection member 140 and the first redistribution layers 112a and 114a of the first connection member 110 is larger than the distance between the redistribution layer 142 of the second connection member 140 May be greater than the distance between the connection pads 122 of the semiconductor chip 120. The second rewiring layers 112b and 114b formed in the first connection member 110 may be disposed between the active surface and the inactive surface of the semiconductor chip 120. [

The thickness of the redistribution layers 112a, 112b, 112c, 114a, 114b, and 114c of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. [ The first connection member 110 may have a thickness equal to or greater than the thickness of the semiconductor chip 120 for uniformity of the thickness of the sealing material 130. The rewiring layers 112a, 112b, 112c, 114a, 114b, It can be formed in a larger size according to the scale. On the other hand, the redistribution layer 142 of the second connection member 140 can be formed in a relatively small size for the purpose of thinning.

As the material of the insulating layers 111a and 111b, for example, a material containing an inorganic filler and an insulating resin can be used. For example, thermosetting resins such as epoxy resins, resins containing reinforcing materials such as inorganic fillers such as silica and alumina together with thermoplastic water such as polyimide, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric Resin), BT, etc. may be used. If desired, a thermosetting resin or a thermoplastic resin may be used as a material impregnated with a core material such as glass fiber (glass fiber, glass cloth, glass fabric) together with an inorganic filler, for example, a prepreg.

The redistribution layers 112a, 112b, 112c, 114a, 114b, and 114c are formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni) , Titanium (Ti), or alloys thereof. The redistribution layers 112a, 112b, 112c, 114a, 114b, and 114c may perform various functions according to the design design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It may also include a via pad pattern, a connection terminal pad pattern, and the like. A surface treatment layer may be formed on the surface of the pad pattern exposed through the opening 131 as needed. The surface treatment layer may be formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / replacement gold plating, DIG plating, HASL and the like.

As the material for forming the vias 113a, 113b, 115a, and 115b, a conductive material may be used. The vias 113a, 113b, 115a, and 115b may be completely filled with a conductive material, or a conductive material may be formed along the wall surface of the via hole. Some of the pad patterns of the first rewiring layers 112a and 114a and the second rewiring layers 112b and 114b may serve as stoppers when holes for the vias 113a, 113b, 115a, and 115b are formed. The bars 113a, 113b, 115a, and 115b may be advantageous in terms of the process, in which the width of the upper surface is larger than the width of the lower surface. In this case, the vias 113a, 113b, 115a, and 115b may be integrated with a part of the second redistribution layers 112b and 114b and the third redistribution layers 112c and 114c. The signal vias 113a and 113b may be disposed on the inner side (a) of the first connection member 110. [ The dummy vias 115a and 115b may be disposed on the outer side (b) of the first connection member 110 in the form of a wall. Dummy vias 115a and 115b may surround signal vias 113a and 113b. Through this structure, it is possible to effectively shield EMI generated in the semiconductor chip 120 and the like. Also, the heat radiation effect can be improved. The dummy vias 115a and 115b can be connected to the ground patterns of the first connection member 110 and / or the second connection member 140, thereby further improving the design efficiency. Each of the plurality of dummy vias 115a and 115b may be spaced apart from each other by a predetermined distance or may be connected to each other through a plurality of line vias 116b. Alternatively, each of the plurality of dummy vias 115a and 115b may be overlapped with each other such that no voids are formed.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit may, for example, be but is not limited to an application processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, . The semiconductor chip 120 may be formed on the basis of an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of the body 121. The body 121 may have various circuits. The connection pad 122 electrically connects the semiconductor chip 120 to other components. As the forming material, a conductive material such as aluminum (Al) may be used without any particular limitation. A passivation film 123 exposing the connection pad 122 may be formed on the body 121. The passivation film 123 may be an oxide film or a nitride film or may be a double layer of an oxide film and a nitride film. The lower surface of the connection pad 122 may have a step with the lower surface of the sealing material 130 through the passivation film 123 so that the sealing material 130 can be prevented from bleeding to the lower surface of the connection pad 122 to some extent have. An insulating film (not shown) or the like may be further disposed at a necessary position.

The sealing material 130 can protect the semiconductor chip 120. [ The sealing shape is not particularly limited and may be a shape that covers at least a part of the semiconductor chip 120. For example, the sealing member 130 may cover at least a part of the inactive surface of the first connection member 110 and the semiconductor chip 120, and may be formed between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120 At least a portion of the space of the second housing. The sealing member 130 may fill at least a part of the space between the passivation film 123 of the semiconductor chip 120 and the second connecting member 140. [ As the insulating material, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler such as polyimide may be used as the insulating material. For example, ABF, FR-4, BT, PID resin, or the like may be used. It is needless to say that a known molding material such as EMC may be used. If necessary, a thermosetting resin or a resin impregnated with a core material such as glass fiber (glass fiber, glass cloth, glass fabric) together with an inorganic filler as a thermoplastic resin may be used.

Metal layer 132 is connected via via 133 to dummy vias 115a and 115b. In this structure, most of the surface of the semiconductor chip 120 is surrounded by the metal material. Therefore, it is possible to more effectively shield the EMI and to have a better heat radiation effect. The metal layer 132 may be formed by coating or plating a known metal material such as copper (Cu). If desired, the metal layer 132 may be utilized as a ground pattern. Therefore, the dummy vias 115a and 115b can be connected to the ground of the entire package 100A. The sealing material 130 has an opening 131 exposing a pad pattern connected to the signal vias 113a and 113b and the metal layer 132 exposes the opening 131. [ Thus, the metal layer 132 may not be connected to the signal vias 113a and 113b.

The second connection member 140 is a structure for rewiring the connection pad 122 of the semiconductor chip 120. Hundreds of hundreds of connection pads 122 having various functions can be rewired through the second connection member 140 and physically and / or electrically connected to the outside through the connection terminal 170 to be described later . The second connection member 140 includes an insulating layer 141, a rewiring layer 142 disposed on the insulating layer 141, and a via 143 connected to the rewiring layer 142 through the insulating layer 141 . In the fan-out semiconductor package 100A according to the exemplary embodiment, the second connection member 140 is formed as a single layer, but may be a plurality of layers.

As the material of the insulating layer 141, an insulating material may be used. In addition to the above-described insulating material, a photosensitive insulating material such as a PID resin may be used as the insulating material. When the insulating layer 141 has multiple layers, these materials may be the same as each other and may be different from each other as needed. If the insulating layers 141 are multilayered, they may be unified according to the process, and the boundaries may be unclear.

The rewiring layer 142 substantially rewires the connection pad 122 and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) , Nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The re-distribution layer 142 may perform various functions according to the design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, various types of pad patterns and the like can be included.

The vias 143 electrically connect the connection pads 122 and the rewiring layer 142 formed in different layers, thereby forming an electrical path in the package 100A. The via 143 may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium A conductive material such as an alloy thereof may be used. The vias 143 can be fully filled with a conductive material, or a conductive material can be formed along the walls of the vias. In addition, any shape known in the art, such as a tapered shape, a cylindrical shape, etc., can be applied.

The passivation layer 150 is an additional structure for protecting the second connection member 140 from external physical chemical damage or the like. The passivation layer 150 may have an opening 151 that exposes at least a portion of the redistribution layer 142 of the second connection member 140. Such openings may exist in the tens to thousands. The material of the passivation layer 150 is not particularly limited, and for example, a photosensitive insulating material such as a photosensitive insulating resin can be used. Alternatively, a solder resist may be used. Alternatively, an insulating resin including a core material but not including a filler, for example, ABF including an inorganic filler and an epoxy resin may be used. The insulating layer 141 of the second connection member 140 may also include an inorganic filler and an insulating resin when using an insulating material including an inorganic filler and an insulating resin such as ABF or the like as the passivation layer 150 The weight percentage of the inorganic filler included in the passivation layer 150 may be greater than the weight percentage of the inorganic filler included in the insulating layer 141 of the second connection member 140. [ In this case, the coefficient of thermal expansion (CTE) of the passivation layer 150 may be relatively low and utilized for warp control.

The under bump metal layer 160 is an additional structure for improving the connection reliability of the connection terminal 170 and improving the board level reliability of the package 100A. The underbump metal layer 160 may be connected to the rewiring layer 142 of the second connection member 140 that is opened through the opening 151 of the passivation layer 150. The under bump metal layer 160 may be formed on the opening 151 of the passivation layer 150 using a known conductive material, that is, a metal, by a known metallization method, but the present invention is not limited thereto.

The connection terminal 170 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device via the connection terminal 170. [ The connection terminal 170 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The connection terminal 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed as a multilayer or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. .

The number, spacing, arrangement type, etc. of the connection terminals 170 are not particularly limited and can be sufficiently modified according to the design specifications of the ordinary artisan. For example, the number of the connection terminals 170 may be several tens to several thousands depending on the number of the connection pads 122 of the semiconductor chip 120, and may have more or less numbers. When the connection terminal 170 is a solder ball, the connection terminal 170 may cover the side surface formed on the one side of the passivation layer 150 of the under-bump metal layer 160, and the connection reliability may be further improved.

At least one of the connection terminals 170 is disposed in the fan-out area. The fan-out area means an area outside the area where the semiconductor chip 120 is disposed. That is, the exemplary fan-out semiconductor package 100A is a fan-out package. The fan-out package is more reliable than the fan-in package, has many I / O terminals, and facilitates 3D interconnection. In addition, compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to manufacture a thin bar package that can be mounted on electronic devices without a separate substrate, and is excellent in price competitiveness.

Although not shown in the drawings, a metal layer may be further disposed on the wall surface of the through hole 110H, if necessary. The metal layer may serve to effectively dissipate heat generated from the semiconductor chip 120. It can also serve as electromagnetic shielding. Further, another passive component such as a capacitor or an inductor may be disposed in the through hole 110H. Also, a plurality of semiconductor chips 120 may be disposed in the through holes 110U. Also, the number of the through holes 110H may be plural, and each of the semiconductor chips 120 and the passive components may be disposed in the respective through holes 110H. Needless to say, well-known structures well known in the art can also be applied.

Fig. 13 schematically shows a modification of the fan-out semiconductor package of Fig.

Referring to the drawings, the fan-out semiconductor package 100B according to the modification has a package-on-package (POP) type structure. The interposer substrate 210 and the interposer substrate 210 which are disposed on the sealing member 130 and are electrically connected to the signal vias 113a and 113b through the connection terminals 180 formed in the opening 131, Further comprising a deployed memory package. The memory package includes a memory 240 electrically connected to the wiring board 230 and the wiring board 230 by wire bonding or the like, a sealing material 250 disposed on the wiring board 230 to seal the memory 240 And a connection terminal 220 for connecting the wiring board 230 to the interposer substrate 210. At this time, the metal layer 261 surrounding the sealing material 250 may be formed for EMI shielding of the memory package. It is also possible to form the metal layer 262 in addition to the area where the connection terminal 220 of the lower surface of the wiring board 230 is disposed. Other configurations are substantially the same as those described above.

Fig. 14 schematically shows another modification of the fan-out semiconductor package of Fig.

Referring to the drawings, the fan-out semiconductor package 100C according to another modification has another type of package-on-package (POP) type structure. That is, the memory package is directly disposed on the sealing material 130, and the memory package is electrically connected to the signal vias 113a and 113b through the connection terminal 180. [ The additional wiring design required by omitting the interposer substrate can be solved by, for example, forming a backside re-wiring layer or the like on the sealing material 130. [ The memory package is similarly mounted on the wiring board 230 and the wiring board 230 and includes a memory 240 electrically connected by wire bonding or the like, a sealing material (not shown) disposed on the wiring board 230 to seal the memory 240 250 and a connection terminal 220 connecting the wiring board 230 to the interposer substrate 210. A metal layer 261 surrounding the sealing material 250 may be formed for the purpose of EMI shielding of the memory package. The metal layer 262 may be formed in addition to the area where the connection terminals 180 are disposed on the lower surface of the wiring board 230. [ Other configurations are substantially the same as those described above.

15 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

16 is a schematic elevational view II-II 'plan view of the fan-out semiconductor package of FIG.

FIG. 17 is another schematic II-II 'plan view of the fan-out semiconductor package of FIG. 15; FIG.

Figure 18 is another schematic II-II 'plan view of the fan-out semiconductor package of Figure 15;

Referring to the drawings, a fan-out semiconductor package 100D according to another example includes a plurality of dummy vias 115a and 115b, which are surrounded by a plurality of signal vias 113a and 113b, Respectively. For example, a dummy portion 110b including a plurality of dummy vias 115a and 115b may be disposed on the inner side (b), and a signal portion 110a including a plurality of signal vias 113a and 113b Can be disposed on the outer side (a). In this case, even though the metal layer 132 is formed only on the inner side (b) of the first connection member 110, the dummy vias 115a and 115b can be connected to the via 133 via the dummy vias 115a and 115b. In addition, the distance from the semiconductor chip 120 is shortened, so that EMI shielding and heat dissipation effects generated in the semiconductor chip 120 can be more excellent. Even when the plurality of dummy vias 115a and 115b are disposed on the inner side b, the respective dummy vias 115a and 115b may be disposed apart from each other and they may be connected through the line via 116b. Further, the dummy vias 115a and 115b may be overlapped. Other configurations are substantially the same as those described above. If necessary, the contents of the fan-out semiconductor packages 100B and 100C according to the modification may be applied to the fan-out semiconductor package 100D according to another example.

19 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, in another exemplary fan-out semiconductor package 100E, the first connecting member 110 includes only a single-layer insulating layer 111. [ Accordingly, the plurality of signal vias 113 and the plurality of dummy vias 115 may also be a single layer that passes through only the insulating layer 111, respectively. The signal portion 110a including the plurality of signal vias 113 can be disposed on the inner side (a) of the first connection member 110 and the dummy portion 115 including the plurality of dummy vias 115 115b may be disposed on the outer side (b) along the outer rim of the first connecting member (110). In other words, even when only a single layer is formed as described above, it can have an EMI shielding effect and a heat radiation effect. Other configurations are substantially the same as those described above. If necessary, the contents of the fan-out semiconductor packages 100B and 100C according to the modification may be applied to the fan-out semiconductor package 100E according to another example.

20 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, in another exemplary fan-out semiconductor package 100F, the first connection member 110 includes only a single-layer insulating layer 111. [ Accordingly, the plurality of signal vias 113 and the plurality of dummy vias 115 may also be a single layer that passes through only the insulating layer 111, respectively. The signal portion 110a including the plurality of signal vias 113 may be disposed on the outer side a of the first connection member 110 and may include a dummy portion including a plurality of dummy vias 115 115b may be disposed on the inner side (b) along the inner edge of the first connecting member (110). In other words, even when only a single layer is formed as described above, it can have an EMI shielding effect and a heat radiation effect. Other configurations are substantially the same as those described above. If necessary, the content of the fan-out semiconductor packages 100B and 100C according to the modification may be applied to the fan-out semiconductor package 100F according to another example.

21 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to FIG. 1, a fan-out semiconductor package 100G according to another exemplary embodiment includes a first connection member 110, a second insulation layer 111b, a third insulation layer 111c, A signal portion 110a, and a dummy portion 110b. The first rewiring layers 112a and 114a and the second rewiring layers 112b and 114b are disposed on both sides of the first insulating layer 111a. The second insulating layer 111b is disposed on the first insulating layer 112a and covers the first redistribution layers 112a and 114a. The third insulating layer 111c is disposed on the second insulating layer 111b and covers the second redistribution layers 112b and 114b. The fourth rewiring layers 112d and 114d are disposed on the third insulating layer 111c. The first to fourth rewiring layers 112a, 112b, 112c, 112d, 114a, 114b, 114c, and 114d may be electrically connected to the connection pad 122. [ The first connecting member 110 includes a greater number of redistribution layers 112a, 112b, 112c, 112d, 114a, 114b, 114c and 114d so as to simplify the second connecting member 140, It is possible to improve the yield reduction due to defects generated in the process of forming the two connection members 140. [ The first to fourth rewiring layers 112a, 112b, 112c, 112d, 114a, 114b, 114c and 114d are connected to the first to third signal via holes 111a, 111b and 111c, 113a, 113b, and 113c and the first to third dummy vias 115a, 115b, and 115c.

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick for maintaining rigidity and the second insulating layer 111b and the third insulating layer 111c may include a larger number of redistribution layers 112c, 112d, 14c, and 114d ). ≪ / RTI > The first insulating layer 111a may include an insulating material different from the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111c and the third insulating layer 111c may be, And an insulating resin, or an ABF film or a photosensitive insulating film. The diameter of the first signal via 113a may be greater than the diameter of the second signal via 113b and the third signal via 113c and the diameter of the first dummy via 115a may be greater than the diameter of the second dummy via 113a, The third dummy vias 115b, and the third dummy vias 115c.

The lower surfaces of the third redistribution layers 112c and 114c of the first connection member 110 can be located below the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the redistribution layer 142 of the second connection member 140 and the third redistribution layers 112c and 114c of the first connection member 110 is larger than the distance between the redistribution layer 142 of the second connection member 140 May be smaller than the distance between the connection pads 122 of the semiconductor chip 120. This is because the third rewiring layers 112c and 114c can be disposed on the second insulating layer 111b so as to be in contact with the second connection member 140. [ The first rewiring layers 112a and 114a and the second rewiring layers 112b and 114b of the first connection member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first connecting member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor chip 120 so that the first and second rewiring layers 112a and 114a formed in the first connecting member 110, The semiconductor chips 112b and 114b may be disposed at a level between the active surface and the inactive surface of the semiconductor chip 120. [

The thickness of the redistribution layers 112a, 112b, 112c, 112d, 114a, 114b, 114c and 114d of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. [ The first connection member 110 may have a thickness greater than that of the semiconductor chip 120. The rewiring layers 112a, 112b, 112c, 112d, 114a, 114b, 114c, and 114d may also be formed in a larger size. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed to be relatively small for thinning. Also in this case, the signal portion 110a including the plurality of signal vias 113a, 113b, and 113c can be disposed on the inner side (a) of the first connection member 110, and the plurality of dummy vias 115a, 115b, 115c may be disposed on the outer side b along the outer rim of the first connecting member 110. [ Therefore, it can have an EMI shielding effect and a heat radiation effect. Other configurations are substantially the same as those described above. If necessary, the contents of the fan-out semiconductor packages 100B and 100C according to the modification may be applied to the fan-out semiconductor package 100G according to another example

22 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, in a fan-out semiconductor package 100H according to another example, a first connecting member 110 includes a first insulating layer 111a, a second insulating layer 111b, a third insulating layer 111c, A signal portion 110a, and a dummy portion 110b. The first rewiring layers 112a and 114a and the second rewiring layers 112b and 114b are disposed on both sides of the first insulating layer 111a. The second insulating layer 111b is disposed on the first insulating layer 112a and covers the first redistribution layers 112a and 114a. The third insulating layer 111c is disposed on the second insulating layer 111b and covers the second redistribution layers 112b and 114b. The fourth rewiring layers 112d and 114d are disposed on the third insulating layer 111c. The first to fourth rewiring layers 112a, 112b, 112c, 112d, 114a, 114b, 114c, and 114d may be electrically connected to the connection pad 122. [ The first to fourth rewiring layers 112a, 112b, 112c, 112d, 114a, 114b, 114c and 114d are connected to the first to third signal via holes 111a, 111b and 111c, 113a, 113b, and 113c and the first to third dummy vias 115a, 115b, and 115c.

Also in this case, the signal portion 110a including the plurality of signal vias 113a, 113b, and 113c may be disposed on the outer side (a) of the first connection member 110 and the plurality of dummy vias 115a, 115b, The dummy portion 110b may be disposed on the inner side b along the inner edge of the first connecting member 110. [ Therefore, it can have an EMI shielding effect and a heat radiation effect. Other configurations are substantially the same as those described above. If necessary, the contents of the fan-out semiconductor packages 100B and 100C according to the modification may be applied to the fan-out semiconductor package 100H according to another example.

The terms "an example" and "modifications" used in the present disclosure are not intended to be construed to limit the same embodiments, but are provided to emphasize and describe different features. However, it should be understood that the above-described examples and modifications do not exclude that they are implemented in combination with the features of other examples or modifications. For example, although the description in the specific example is not described in another example, it can be understood as an explanation related to another example, unless otherwise described or contradicted by the other example.

In the present disclosure, the meaning of being connected is not a direct connection but a concept including an indirect connection. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection. Also, the first, second, etc. expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

In the present disclosure, upper, lower, upper, lower, upper, lower, and the like are determined based on the attached drawings. For example, the first connecting member is located above the re-wiring layer. However, the claims are not limited thereto. In addition, the vertical direction means the above-mentioned upper and lower direction, and the horizontal direction means the direction perpendicular thereto. In this case, the vertical cross-section means a case of cutting into a plane in the vertical direction, and the cross-sectional view shown in the figure is an example. In addition, the horizontal cross-section means a case where the horizontal cross-section is cut into a plane in the horizontal direction, for example, the plan view shown in the drawing.

The terms used in this disclosure are used only to illustrate an example and are not intended to limit the present disclosure. Wherein the singular expressions include plural expressions unless the context clearly dictates otherwise.

1000: electronic device 1010: main board
1020: Chip related parts 1030: Network related parts
1040: Other parts 1050: Camera
1060: antenna 1070: display
1080: Battery 1090: Signal line
1100: Smartphone 1101: Smartphone body
1110: Smartphone mainboard 1111: mainboard insulation layer
1112: main board wiring 1120: parts
1130: Smartphone camera 2200: Fan-in semiconductor package
2220: semiconductor chip 2221: body
2222: connection pad 2223: passivation film
2240: connecting member 2241: insulating layer
2242: re-wiring layer 2243: via
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: Interposer substrate 2302: Interposer substrate
2100: Fan-out semiconductor package 2120: Semiconductor chip
2121: Body 2122: Connection pad
2140: connecting member 2141: insulating layer
2142: re-wiring layer 2143: via
2150: passivation layer 2160: under bump metal layer
2170: solder ball 100: semiconductor package
100A to 100H: Fan-out semiconductor package
110: connecting member 111, 111a to 111c: insulating layer
112a to 112d, 114a to 114d: rewiring layers 113, 113a to 113c: signal vias
115, 115a to 115c: dummy vias 120: semiconductor chips
121: Body 122: Connection pad
123: Passivation film 130: Seal material
131: opening 132: metal layer
133: via 140: connecting member
141: insulating layer 142: rewiring layer
143: Vias 150: Passivation layer
151: opening 160: under bump metal layer
170: connection terminal 180: connection terminal
210: interposer substrate 220: connection terminal
230: wiring board 240: memory
250: sealing material 261, 262: metal layer

Claims (16)

A first connecting member having a through hole;
A semiconductor chip disposed in the through hole of the first connection member and having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface;
A sealing member for sealing at least a part of a space between the one surface of the first connecting member, the inactive surface of the semiconductor chip, and the inner wall of the through hole and the semiconductor chip; And
A second connecting member disposed on the other surface of the first connecting member and the active surface of the semiconductor chip; / RTI >
Wherein the first connecting member and the second connecting member each include a re-wiring layer electrically connected to a connection pad of the semiconductor chip,
The rewiring layer of the first connection member includes a signal pattern and a ground pattern,
Wherein the first connection member is connected to the ground pattern and includes a plurality of dummy vias arranged to surround the semiconductor chip,
Wherein at least a part of the active surface of the semiconductor chip and the other surface of the first connecting member are in physical contact with the second connecting member,
A fan-out semiconductor package.
The method according to claim 1,
A metal layer disposed on the sealing material and covering at least a part of the non-active surface side of the semiconductor chip; Further comprising:
Said metal layer being connected to said plurality of dummy vias,
A fan-out semiconductor package.
The method according to claim 1,
Wherein the first connection member comprises a plurality of signal vias connected to the signal pattern,
A fan-out semiconductor package.
The method of claim 3,
Wherein the plurality of dummy vias are arranged along an outer rim of the first connection member so as to surround the plurality of signal vias,
A fan-out semiconductor package.
The method of claim 3,
The plurality of dummy vias being arranged along an inner rim of the first connection member so as to be surrounded by the plurality of signal vias,
A fan-out semiconductor package.
The method according to claim 1,
Each of the plurality of dummy vias being spaced apart from each other by a predetermined distance,
A fan-out semiconductor package.
The method according to claim 6,
Wherein the plurality of dummy vias are connected to each other through a plurality of line vias,
A fan-out semiconductor package.
The method according to claim 1,
Wherein each of the plurality of dummy vias includes a plurality of dummy vias,
A fan-out semiconductor package.
The method of claim 3,
A memory package disposed on the seam and electrically connected to the plurality of signal vias; ≪ / RTI >
A fan-out semiconductor package.
The method according to claim 1,
Wherein the first connecting member comprises a first insulating layer, a first rewiring layer in contact with the second connecting member and embedded in the first insulating layer, and a second rewiring layer on the opposite side of the first rewiring layer, And a second rewiring layer disposed on the first rewiring layer,
Each of said plurality of dummy vias including a first dummy via penetrating said first insulating layer,
A fan-out semiconductor package.
11. The method of claim 10,
The first connecting member further includes a second insulating layer disposed on the first insulating layer and covering the second rewiring layer and a third rewiring layer disposed on the second insulating layer,
Each of the plurality of dummy vias including first and second dummy vias that pass through the first and second insulation layers, respectively,
A fan-out semiconductor package.
11. The method of claim 10,
The distance between the re-wiring layer of the second connecting member and the first re-wiring layer is larger than the distance between the re-wiring layer of the second connecting member and the connection pad of the semiconductor chip,
A fan-out semiconductor package.
The method according to claim 1,
The first connecting member includes a first insulating layer, a first rewiring layer and a second rewiring layer disposed on both surfaces of the first insulating layer, a second rewiring layer disposed on the first insulating layer, An insulating layer, and a third rewiring layer disposed on the second insulating layer,
Each of the plurality of dummy vias including first and second dummy vias that pass through the first and second insulation layers, respectively,
A fan-out semiconductor package.
14. The method of claim 13,
The first connecting member further includes a third insulating layer disposed on the first insulating layer and covering the second rewiring layer and a fourth rewiring layer disposed on the third insulating layer,
Wherein each of the plurality of dummy vias includes first through third dummy vias respectively passing through the first through third insulation layers,
A fan-out semiconductor package.
14. The method of claim 13,
Wherein the first insulating layer is thicker than the second insulating layer,
A fan-out semiconductor package.
A first connecting member having a through hole;
A semiconductor chip disposed in the through hole of the first connection member and having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface; And
A second connecting member disposed on the active surface of the first connecting member and the semiconductor chip and including a re-wiring layer electrically connected to a connection pad of the semiconductor chip; / RTI >
The first connection member includes a plurality of signal vias and a plurality of dummy vias,
The plurality of dummy vias surrounding the plurality of signal vias,
The plurality of dummy vias being surrounded by the plurality of signal vias,
Wherein the second connecting member is in physical contact with at least a portion of the active surface of the semiconductor chip and the first connecting member.
A fan-out semiconductor package.

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