TWI605556B - Smd, ipd, and/or wire mount in a package - Google Patents

Description

Surface mount devices, integrated passive devices and/or wire mounting in packages

This disclosure relates to SMD, IPD, and/or wire bonding in packages.

Semiconductor devices are used in many electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by successively depositing an insulating or dielectric layer, a conductive layer, and a layer of semiconductor material over a semiconductor substrate, and patterning different layers of material using lithography to form circuit components and components thereon. Dozens or hundreds of integrated circuits are typically fabricated on a semiconductor wafer. The integrated circuit is cut along the cutting line to be granulated by individual crystal grains. Then, for example, individual dies are packaged in a multi-wafer module or other form of package, respectively.

The semiconductor industry continues to improve the bulk density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated in a given area. . Smaller electronic components, such as integrated circuit dies, may also require smaller packages, which in some applications use a smaller area than conventional packages.

Some embodiments of the present disclosure provide a structure that includes a first package that includes a device attached to a first pad and a second pad, the device being a surface mount device (SMD), an integrated passive device (integrated passive device, IPD), or a combination thereof, the device being attached to the first pad via a dielectric layer The second spacer, the first spacer material is laterally located between the first pad and the second pad and between the device and the dielectric layer, the package surrounds the device and the first spacer material And a package assembly attached to the first package by an external connector.

Some embodiments of the present disclosure provide a structure including a first package including an integrated circuit die that is at least laterally encapsulated by a first package; a redistribution structure that is located in the integrated circuit die and On the first package, the redistribution structure includes a first pad, a second pad, and a dielectric layer; and a device is attached to the first pad and the second pad via the dielectric layer, The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof, the recess being in the dielectric layer between the first pad and the second pad.

Some embodiments of the present disclosure provide a method comprising patterning an opening through a dielectric layer to expose a first pad and a second pad, the dielectric layer being located in a redistribution structure in the first package; forming a first spacer material on the dielectric layer between the first pad and the second pad; and after forming the first spacer material, attaching the device to the first pad and the second pad, The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof, the first spacer material being between the device and the dielectric layer.

40A, 40B‧‧‧ package

42‧‧‧Integrated circuit die

74‧‧‧Surface Mounting Device (SMD)/Integrated Passive Device (IPD)

46‧‧‧Dielectric materials

44‧‧‧Packaged die attach

50‧‧‧ Front redistribution structure

48‧‧‧Adhesive

54‧‧‧Dielectric layer

52‧‧‧metallized pattern

56‧‧‧Package

58‧‧‧through path

62‧‧‧metallized pattern

64‧‧‧Dielectric layer

66, 68, 70, 72‧‧‧ pads

60‧‧‧Backrest structure

76‧‧‧Under metal

78‧‧‧External connectors

82‧‧‧External connectors

80‧‧‧solder resistance layer

100, 120‧‧‧ package

102, 104, 106‧‧‧ pads

108, 110, 112‧‧‧ pads

114, 116, 300‧‧‧SMD/IPD

302, 304‧‧‧ pads

306, 308‧‧‧ dielectric layer

310‧‧‧ spacer material

314‧‧‧ gap

316‧‧‧ spacer material

322‧‧‧Package components

328‧‧‧ spacer material

330‧‧‧Under material

122, 124, 126, 150‧‧‧ wire bonding

140, 142, 144, 146, 148‧‧‧ pads

150‧‧‧SMD/IPD

200‧‧‧ Carrier

202‧‧‧ release layer

204‧‧‧Dielectric layer

206‧‧‧ seed layer

208‧‧‧Light resistance

210‧‧‧Electrical materials

212‧‧‧Metalized materials

214‧‧‧ dielectric layer

216‧‧ ‧ seed layer

218‧‧‧Light resistance

220‧‧‧Electrical materials

222‧‧‧through path

224‧‧‧Integrated circuit die

226‧‧‧SMD/IPD

228‧‧‧Grain connectors

230‧‧‧ dielectric materials

232‧‧‧Adhesive

234‧‧‧Package

236‧‧‧ dielectric layer

238‧‧‧ seed layer

240‧‧‧Light resistance

242‧‧‧Electrical materials

244‧‧‧metallized pattern

246, 250‧‧‧ dielectric layer

248, 252‧‧‧ metallized patterns

254‧‧‧Under metal

256, 258‧‧‧ pads

251‧‧‧ dielectric layer

260‧‧‧SMD/IPD

262‧‧‧External connectors

264‧‧‧ Tape

270, 272, 274‧‧ ‧ pads

276, 278, 280 ‧ ‧ mat

282‧‧‧SMD/IPD

400, 401‧‧‧ package

402‧‧‧Substrate

404‧‧‧ grain

406‧‧‧Package

408‧‧‧Under material

410‧‧‧Substrate

412‧‧‧Under material

500, 506‧‧‧ dielectric layer

502, 504‧‧‧ pads

508‧‧‧ spacer material

510‧‧‧ solder

512‧‧‧SMD/IPD

514‧‧‧Package

516‧‧‧Substrate

518‧‧‧ spacer material

520‧‧‧Under material

540‧‧‧ gap

542‧‧‧ spacer material

In order to assist the reader to achieve the best understanding, it is recommended to refer to the attached figure and its detailed text description when reading this disclosure. Please note that in order to comply with industry standards, the drawings in this patent specification are not necessarily drawn to the correct scale. In some drawings, the dimensions may be deliberately enlarged or reduced to assist the reader in understanding the discussion.

FIG. 1A illustrates a cross-sectional view of a package in accordance with some embodiments.

FIG. 1B illustrates a cross-sectional view of the package modification of FIG. 1A in accordance with some embodiments.

2 is a cross-sectional view of another package in accordance with some embodiments.

3 is a cross-sectional view of a portion of a package in accordance with some embodiments.

4A and 4B illustrate cross-sectional views and layouts of a portion of a package, respectively, in accordance with some embodiments.

5 through 7 illustrate cross-sectional views of a portion of a package in accordance with some embodiments.

Figure 8 illustrates a cross-sectional view of another package in accordance with some embodiments.

9A and 9B illustrate a layout of an outer surface of a redistribution structure in accordance with some embodiments.

10 through 29 are cross-sectional views illustrating intermediate steps in the process of forming a package on a package in accordance with some embodiments.

30A through 30D are cross-sectional views illustrating intermediate steps during a surface mount (SMD) (hereinafter referred to as SMD/IPD) process for attaching an integrated passive device (IPD), in accordance with some embodiments.

31, 32A and 32B are cross-sectional views illustrating intermediate steps in a packaged SMD/IPD process, in accordance with some embodiments.

33A through 33D are cross-sectional views illustrating intermediate steps in an attachment SMD/IPD process, in accordance with some embodiments.

Figures 34, 35A and 35B illustrate cross-sectional views of intermediate steps in a packaged SMD/IPD process, in accordance with some embodiments.

36A through 36C are cross-sectional views illustrating intermediate steps in the process of attaching an SMD/IPD process, in accordance with some embodiments.

37, 38A and 38B are cross-sectional views illustrating intermediate steps in a packaged SMD/IPD process, in accordance with some embodiments.

The disclosure provides several different implementations or embodiments that can be used to implement different features of the invention. For simplicity of explanation, the present disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for demonstration purposes only and are not intended to be limiting. For example, in the following description of how the first feature is on or above the second feature, certain embodiments may be included, where the first feature and the second feature The sign is a direct contact, and other different embodiments may be included in the description, with other features in between the first feature and the second feature such that the first feature is not in direct contact with the second feature. In addition, various examples in the disclosure may use repeated reference numerals and/or text annotations to make the document more simplistic and clear, and such repeated reference numerals and annotations do not represent an association between different embodiments and configurations.

In addition, the disclosure uses spatially related narrative vocabulary such as "under", "low", "lower", "above", "above", "down", "top", "bottom" For the sake of brevity, the use of one element or feature in the illustration is to be described in the <RTIgt; In addition to the angular orientations shown in the figures, these spatial relative terms are also used to describe the possible angles and directions of the device in use and during operation. The angular orientation of the device may vary (rotating 90 degrees or other orientations), and the spatially related descriptions used in this disclosure may be interpreted in the same manner.

The embodiments described herein are described in specific content, referred to as surface mount devices (SMDs), integrated passive devices (IPDs), and/or wiring, which can be used as anti-fuse, Fan out, or fan into the wafer level package. Some embodiments implement this package as a package-on-package (PoP) structure. Other embodiments implement other applications, such as different package formats or different architectures, which are readily understood by those of ordinary skill in the art after reading the disclosure. It should be noted that the embodiments of the present disclosure are not required to illustrate every component or feature in the structure. For example, when a component is sufficient to convey the content of the embodiments, duplicate components may be omitted from the drawings. Furthermore, the method embodiments disclosed herein are performed in a particular order; however, other method embodiments can be performed in any logical order.

1 illustrates a cross-sectional view of a package 40A, such as a fan-out or fan-in wafer level package, including one or more integrated circuit dies 42 disposed in package 40A or package 40A, in accordance with some embodiments. One or more surface mount devices (SMD) or integrated Passive device (IPD) (hereinafter referred to as SMD/IPD) 74. The integrated circuit dies 42 each comprise a semiconductor substrate, such as germanium, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may comprise another elemental semiconductor such as germanium; a compound semiconductor comprising tantalum carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; including SiGe, GaAsP, AlInAs, AlGaAs An alloy semiconductor of GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, can also be used. Devices such as transistors, diodes, capacitors, resistors, and the like may be formed on the semiconductor substrate and/or on the semiconductor substrate, and may be formed by a metallization pattern in one or more dielectric layers on the semiconductor substrate. The interconnect structures are interconnected to form an integrated circuit.

A grain interconnect 44, such as a conductive pillar or via (including, for example, a metal such as copper), is external to the integrated circuit die 42, and is mechanically coupled and electrically coupled to the corresponding integrated circuit die 42, which may be referred to as It is the corresponding active side of the integrated circuit die 42. The die attach 44 is a corresponding integrated circuit that electrically couples the integrated circuit die 42.

Dielectric material 46 is on the active side of integrated circuit die 42. The dielectric material 46 is a laterally packaged die attach 44 having an upper surface that is flush with the upper surface of the dielectric material 46 and the dielectric material 46 is laterally aligned with the corresponding integrated circuit die 42. level. The dielectric material 46 can be a polymer such as polybenzoxazole (PBO), polyamidamine (PI), benzocyclobutene (BCB), or the like; a nitride such as nitriding Ruthenium or the like; an oxide such as ruthenium oxide, phosphonium silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; analog, Or a combination thereof.

Adhesive 48 is located on the back side of integrated circuit die 42 and adheres integrated circuit die 42 to front redistribution structure 50. Adhesive 48 can be any suitable adhesive, epoxy compound, glue, or the like.

The front redistribution structure 50 includes one or more of the one or more dielectric layers 54 Metallization pattern 52. The one or more metallization patterns 52 can comprise any wire, via, pad, the like, or a combination thereof, and can include a conductive material, such as a metal, such as copper, titanium, tungsten, aluminum, or the like. The one or more dielectric layers 54 can be a polymer such as PBO, polyamidoamine, BCB, or the like; a nitride such as tantalum nitride or the like; an oxide such as yttrium oxide, PSG, BSG, BPSG, or an analog; an analog; or a combination thereof.

The package 56 at least laterally encapsulates the integrated circuit die 42. The package 56 has a first surface that abuts the redistribution structure 50 and has a second surface that is flush with the upper surface of the dielectric material 46 and the die attach 44. The package 56 can be a molding compound, an epoxy compound, or the like.

The through via 58 extends through the package, such as from a first surface of the package 56 to a second surface of the package 56. The through via 58 electrically couples the front redistribution structure 50, such as at least a portion of the one or more metallization patterns 52, to the backside redistribution structure 60, such as at least a portion of the one or more metallization patterns 62. The through via 58 can comprise a conductive material such as a metal such as copper, titanium, tungsten, aluminum, or the like.

Backside redistribution structure 60 includes one or more metallization patterns 62 in one or more dielectric layers 64. At least a portion of the one or more metallization patterns 62 are electrically coupled to corresponding integrated circuits on the integrated circuit die 42 via corresponding die connections 44. The one or more metallization patterns 62 can comprise any of wires, vias, pads, the like, or combinations thereof, and can include a conductive material such as a metal such as copper, titanium, tungsten, aluminum, or the like. The one or more dielectric layers 64 can be a polymer such as PBO, polyamidoamine, BCB, or the like; a nitride such as tantalum nitride or the like; an oxide such as yttrium oxide, PSG, BSG, BPSG, or an analog; an analog; or a combination thereof.

The one or more metallization patterns 62 include pads 66, 68, 70 and 72 that are exposed on the backside relief structure 60. Pads 66, 68, 70 and 72 can be locations where antifuse are formed. For example, SMD/IPD 74, such as a resistor or any acceptable connector (jumper) is bonded to pads 66 and 68 to form an electrical connection between pads 66 and 68. In this example, SMD/IPD is not engaged between pads 70 and 72, and thus no closed loop circuit is formed between pads 70 and 72. Thus, the SMD/IPD 74 can be an anti-fuse for creating a closed loop circuit that electrically connects, for example, a portion of the integrated circuitry on the integrated circuit die 42 and/or various metallization patterns 52 in the redistribution structures 50 and 60. And / or 62. In some embodiments, the SMD/IPD 74 is a low resistance resistor, for example having a resistance of less than about 0.1 ohms, and more specifically less than about 0.05 ohms. In other embodiments, other components, such as wire bonding or other acceptable connectors, may be used as antifuse, for example, as described below.

The one or more metallization patterns 62 further include an under-metal 76 exposed on the backside relief structure 60. External connectors 78, such as solder balls, such as ball grid array (BGA) balls, are located on the lower metal 76. In some embodiments, the external connector 78 includes solder, such as a Sn-Ag alloy, a Sn-Ag-Cu alloy, or the like, and may be lead-free or lead-containing.

In FIG. 1A, dielectric layer 64 is located on metallization pattern 62, which includes pads 66, 67, 70 and 72 and a lower metal 76. This metallization pattern 62 can be formed, and the subsequent deposition and patterning of the dielectric layer 64 on the metallization pattern 62 can be understood by the process described with reference to FIGS. 10-29. Patterning of dielectric layer 64 may expose pads 66, 68, 70 and 72 and lower metal 76. Figure 1B illustrates the modification. After forming the metallization pattern 62 including the pads 66, 68, 70, and 72 and the lower metal 76, the dielectric layer is no longer deposited on the metallization pattern 62. Although the continuation diagram illustrates the backside redistribution structure 60 as shown in package 40A of FIG. 1A, the modification of the backside relief structure 60 in package 40B of FIG. 1B can be incorporated into the structure of any subsequent pattern.

Referring to FIG. 1A, the pads of one or more metallization patterns 52 of the front redistribution structure 50 are also exposed. External connectors 82, such as solder bumps, solder balls, metal posts, the like, or a combination of metal posts and solder thereon, are placed on the pads of one or more metallization patterns 52. In some embodiments, the external connector 82 includes solder, such as a Sn-Ag alloy, a Sn-Ag-Cu alloy, or the like, and may be lead-free or lead-containing. Solder resist layer 80 is also located in front The surface is overlaid on the structure 50.

2 illustrates a package 100 that includes one or more integrated circuit dies 42 that are disposed on package 100 or in package 100 by one or more SMD/IPDs, in accordance with some embodiments. The package 100 is generally similar to the packages 40A and 40B shown in FIGS. 1A and 1B, and thus the features discussed in FIGS. 1A, 1B and 2 are omitted.

The one or more metallization patterns 52 include pads 102, 104, 106, 108, 110, and 112. Pads 102, 104, 106, 108, 110, and 112 can be locations where antifuse are formed. For example, SMD/IPD 114, such as a resistor or any acceptable jumper, is bonded to pads 102 and 104 to form an electrical connection between pads 102 and 104. The SMD/IPD 114 is located on the exterior surface of the package 100. Again, in this example, SMD/IPD 116, such as a resistor or any acceptable jumper, is bonded to pads 110 and 112 to form an electrical connection between pads 110 and 112. SMD/IPD 116 cells are embedded in the enclosure 56. Thus, the SMD/IPD 116 is located opposite the SMD/IPD 114 on the opposite side of the front redistribution structure 50. In this example, no SMD/IPD is bonded between pads 106 and 108, and thus no closed loop circuitry is formed between pads 106 and 108. Thus, SMD/IPD 114 and 116 can be anti-fuse, creating a closed loop circuit to electrically couple portions of the integrated circuit on, for example, integrated circuit die 42 and/or various metallizations in redistribution structures 50 and 60. Patterns 52 and/or 62. In some embodiments, SMD/IPD 114 and 116 are low resistance resistors, for example having a resistance of less than about 0.1 ohms, and more specifically less than about 0.05 ohms. In other embodiments, other components such as wire bonding or other acceptable connectors may be used as the anti-fuse as described below. This described embodiment illustrates a plurality of locations in the package 100 where the antifuse can be placed.

FIG. 3 illustrates SMD/IPD 300 on pads 302 and 304 in accordance with some embodiments. The SMD/IPD 300 can be any of the SMD/IPDs 74, 114, and 116 shown in FIGS. 1A and 2, and thus the modifications shown in FIG. 3 can be applied to the packages shown in FIGS. 1A and 2. Furthermore, for any application, SMD/IPD 300 can be any SMD/IPD, such as capacitors, electricity Resistor, or the like. FIG. 3 illustrates dielectric layers 306 and 308. Pads 302 and 304 are on dielectric layer 306, and dielectric layer 308 is on dielectric layer 306 and pads 302 and 304 with openings through dielectric layer 308 to pads 302 and 304. Dielectric layers 306 and 308 can each be a polymer, such as PBO, polyamidoamine, BCB, or the like; a nitride such as tantalum nitride or the like; an oxide such as yttrium oxide, PSG, BSG, BPSG, Or an analog; an analog; or a combination thereof, as described above. Pads 302 and 304 can be partially metallized and can include a conductive material such as a metal such as copper, titanium, tungsten, aluminum, or the like. Spacer material 310 is on the outer surface of dielectric layer 308 between pads 302 and 304. The spacer material 310 may be an underfill material, a spacer paste, or a spacer tape, which may further be an epoxy compound, an organic material, or the like. SMD/IPD 300 is attached between pads 302 and 304 using solder 312. Since solder 312 is formed at the edge of SMD/IPD 300 and contacts pad 302 and pad 304, spacer material 310 does not extend beyond the edge of SMD/IPD 300. The SMD/IPD 300 can contact the spacer material 310 between the dielectric layer 308 and between the pads 302 and 304.

4A and 4B illustrate the modification of Fig. 3. In the cross-sectional view of FIG. 4A, a gap 314 is formed through dielectric layer 308 between pads 302 and 304. The gap 314 can be an opening that passes through the dielectric layer 308 to the dielectric layer 306. In some embodiments, the depth of the gap 314 can range from about 5 microns to about 10 microns. Spacer material 316 is located in gap 314 and is located on the outer surface of dielectric layer 308 between pads 302 and 304. The spacer material 316 can be a primer material, a spacer glue, or a spacer tape, which can be further an epoxy compound, an organic material, or the like. The SMD/IPD 300 can contact the spacer material 316 located in the gap 314 and on the dielectric layer 308 between the pads 302 and 304.

Figure 4B illustrates the layout of the components of Figure 4A. A gap 314 in the dielectric layer 308 is between the pads 302 and 304. In some embodiments, the first dimension D1 of the pads 302 and 304 is in the range of about 0.45 mm to about 0.55 mm, and the second dimension D2 of the pads 302 and 304 is in the range of about 0.40 mm to about 0.50 mm. . Pad 302 to pad 304 The spacing S can range from about 0.45 mm to about 0.55 mm. The length L of the gap 314 is greater than the first dimension D1 of the pads 302 and 304, and in some embodiments, may range from about 0.50 mm to about 0.60 mm. The width W of the gap 314 is less than the spacing S between the pads 302 and 304, which in some embodiments may range from about 0.1 mm to about 0.5 mm.

Figures 5 and 6 illustrate other portions of some embodiments. One of ordinary skill in the art will appreciate that the package illustrated in Figures 1A and 2 can be attached to one or more other package components, such as another package or substrate, such as a printed circuit board (PCB). Figures 5 and 6 illustrate portions of the package that are attached to the package assembly 322, respectively, including the portions illustrated in Figures 3 and 4A. The package to which the SMD/IPD 300 is attached further includes a lower metal 320 that can be on the dielectric layer 306 and exposed via the opening through the dielectric layer 308 in the same metallization pattern as pads 302 and 304. The package is attached to the package assembly 322 using an external connector 326, such as an external connector 78 or 82. When the package is attached to the package assembly 322, the spacer material 328 is located on the package assembly 322, which corresponds to the location of the SMD/IPD 300. Thus, when the package is attached to the package assembly 322, the spacer material 328 is located between the SMD/IPD 300 and the package assembly 322. The SMD/IPD 300 can contact the spacer material 328. The spacer material 328 can be a primer material, a spacer glue, or a spacer tape, which can be further an epoxy compound, an organic material, or the like. The primer material 330 separated from the spacer materials 310, 316 and 328 is located between the package and package assembly 322 and surrounds the different components between the package and the package assembly, including the external connectors 326 and the SMD/IPD 300. In some embodiments, for example, when the spacing between SMD/IPD 300 and package assembly 322 is large enough to cause primer material 330 to flow between SMD/IPD 330 and the package group and fill in SMD/IPD 330 and package groups The spacer material 328 may be omitted from the structure shown in FIGS. 5 and 6 when there is a space between.

Figure 7 illustrates the modification of Figure 6. In the configuration shown in Figure 7, the primer material 330 acts as a spacer material at the spacer materials 316 and 328. The presence of the gap 314 allows the primer material 330 to move more freely between the SMD/IPD 300 and the package. Furthermore, The space between the SMD/IPD 300 and the package assembly 322 is large enough to cause the primer material 330 to flow between the SMD/IPD 300 and the package assembly 322 and fill the space between the SMD/IPD 300 and the package assembly 322. Thus, after the package is attached to the package assembly 322, the applied primer material 330 can flow between the SMD/IPD 300 and the package and between the SMD/IPD 300 and the package assembly 322 as a spacer material. In some embodiments, the structure shown in FIG. 7 can include the spacer material 328 shown in FIG.

Although generally described between package and package assembly 322, the content of Figure 7 can be applied to other situations. For example, a gap 314 can be formed in the dielectric layer 54 for the SMD/IPD 116 shown in FIG. The encapsulant 56 can then serve as the primer material 330 of FIG. 7 and can flow into the gap 314 between the SMD/IPD 116 and the front redistribution structure 50 as a spacer material.

8 illustrates a package 120 that includes one or more integrated circuit dies 42 that are configured by one or more wire bonds on package 120 or package 120, in accordance with some embodiments. The packages 120 are typically similar to the packages 40A, 40B, and 100 of FIGS. 1A, 1B, and 2, respectively, and thus the above-described features discussed with respect to FIGS. IA, 1B, and 2 and FIG. 8 are omitted herein.

In FIG. 8, wire bonds 122, 124, and 126 are used as anti-fuse in SMD/IPD 74, 114, and 116. Wire bonding 122, 124, and 126 can comprise any acceptable wire, such as copper, gold, aluminum, silver, platinum, palladium, tin, the like, or combinations thereof. This described implementation illustrates that another adapter, such as wire bonding, can be used as the antifuse in package 120.

9A and 9B illustrate a layout of the outer surface of the backside relief structure 60 in accordance with some embodiments. A similar layout can also be used as the outer surface of the front redistribution structure 50. The content of these layouts can also be applied to any location where the anti-fuse is located.

The outer surface includes pads 140, 142, 144, 146 and 148. Pad 140 can be electrically coupled and mechanically coupled to external electrical connections, such as connectors 78 and/or 82, as described above. For example, pad 140 can be used for BGA balls. In these embodiments, the pad 140 surrounds the configuration pad The anti-fuse regions of 142, 144, 146 and 148. Pads 142, 144, 146 and 148 are used to connect or not connect a connector, such as SMD/IPD 150 or wire bond 152, to arrange the integrated circuit on the integrated circuit die. In FIG. 9A, an SMD/IPD 150, such as a resistor, is connected between the corresponding pads 142 and 146, and no anti-fuse is connected between the corresponding pads 144 and 148. In FIG. 9B, wire bonding 152 is coupled between corresponding pads 142 and 146, and no anti-fuse is coupled between corresponding pads 144 and 148. By connecting SMD/IPD 150 or wire bond 152 between pads 142 and 146, a closed circuit is formed, and since no antifuse is connected between pads 144 and 148, the circuit between pads 144 and 148 remains open ( Open). Therefore, SMD/IPD 150, wire bonding 152, or other connectors can be used as the antifuse.

The layout of Figures 9A and 9B illustrates that the pad for the antifuse can have any number of pad pairs for attaching the antifuse. Moreover, on any surface, such as an outer surface or an embedded, inner surface, the package can have any number of pad regions for the antifuse. In addition, any combination of SMD, IPD, wire bond or splice can be used as the antifuse.

10 through 29 are cross-sectional views illustrating intermediate steps in forming a package structure on a package in accordance with some embodiments. FIG. 10 illustrates the carrier 200 and the release layer 202 formed on the carrier 200. The carrier 200 can be a glass carrier, a ceramic carrier, or the like. Carrier 200 can be a wafer. The release layer can be formed from a polymer-based material that can be removed from the carrier 200 along the upper structure formed by subsequent steps. In some embodiments, the release layer 202 is an epoxy compound that is a heat release material for the substrate that loses its viscosity when heated. In other embodiments, the release layer 202 can be an ultraviolet (UV) glue that loses its viscosity when exposed to UV light. The release layer 202 may be applied as a liquid and hardened, may be laminated to the carrier 200 as a laminate film, or may be an analog. The top surface of the release layer 202 can be flush and can have a high degree of coplanarity.

A dielectric layer 204 is formed on the release layer 202. Bottom surface of dielectric layer 204 The top surface of the release layer 202 can be contacted. In some embodiments, the dielectric layer 204 is formed from a polymer, such as PBO, polyamidoamine, BCB, or the like. In other embodiments, dielectric layer 204 is formed of a nitride such as tantalum nitride; an oxide such as hafnium oxide, PSG, BSG, BPSG, or the like; or the like. Dielectric layer 204 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, similar methods, or combinations thereof.

Referring to FIG. 11, a seed layer 206 is formed over the dielectric layer 204. In some embodiments, the seed layer 206 is a metal layer that can be a single layer or a composite layer comprising a plurality of sub-layers of different materials. In some embodiments, the seed layer 206 includes a layer of titanium and a layer of copper over the layer of titanium. For example, the seed layer 206 can be formed using physical vapor deposition (PVD) or the like.

On the seed layer 206, a photoresist 208 is formed and patterned. The photoresist 208 can be formed by spin coating or the like and can be exposed for patterning. The pattern of photoresist 208 corresponds to the metallization pattern. Patterning is formed through the opening of the photoresist 208 to expose the seed layer 206.

A conductive material 210 is formed in the opening of the photoresist 208 and on the exposed portion of the seed layer 206. The conductive material 210 can be formed by a plating process such as electroplating or electroless plating, or the like. Conductive material 210 can comprise a conductive material such as a metal such as copper, titanium, tungsten, aluminum, or the like.

In FIG. 12, the photoresist 208 and the portion of the seed layer 206 on which the conductive material 210 is not formed are removed. The photoresist 208 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist 208 is removed, the exposed portions of the seed layer 206 are removed using an acceptable etching process, such as wet or dry etching. The remaining portion of the seed layer 206 forms a metallization pattern 212 with the conductive material 210.

In FIG. 13, a dielectric layer 214 is formed over the metallization pattern 212 and the dielectric layer 204. In some embodiments, the dielectric layer 214 is formed of a polymer that can be photosensitive Sensitive materials, such as PBO, polyamidoamine, BCB, or the like, can be easily patterned using a photolithographic etch mask. In other embodiments, the dielectric layer 214 is formed of, for example, a nitride of tantalum nitride; an oxide such as hafnium oxide, PSG, BSG, BPSG, or the like. Dielectric layer 214 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 214 is then patterned to form openings to expose portions of the metallization pattern 212. The patterning is an acceptable process, such as exposing the dielectric layer 214 when the dielectric layer is a light sensitive material, or etching using an anisotropic etch.

Referring to FIG. 14, a seed layer 216 is formed over the exposed portions of the dielectric layer 214 and the metallization pattern 212. In some embodiments, the seed layer 216 is a metal layer that can be a single layer or a composite layer comprising a plurality of sub-layers of different materials. In some embodiments, the seed layer 216 includes a layer of titanium and a layer of copper over the layer of titanium. For example, the seed layer 216 is formed by PVD or the like.

On the seed layer 216, a photoresist 218 is formed and patterned. The photoresist 218 can be formed by spin coating or the like, and can be exposed for patterning. The pattern of photoresist 218 corresponds to the through via. Patterning is formed through the opening of photoresist 218 to expose seed layer 216.

A conductive material 220 is formed in the opening of the photoresist 218 and on the exposed portion of the seed layer 216. The conductive material 220 can be formed by a plating process such as electroplating or electroless plating, or the like. Conductive material 220 can comprise a conductive material such as a metal such as copper, titanium, tungsten, aluminum, or the like.

In FIG. 15, the photoresist 218 and the portion of the seed layer 216 on which the conductive material 220 is not formed are removed. The photoresist 218 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist 218 is removed, the exposed portions of the seed layer 216 are removed using an acceptable etching process, such as wet or dry etching. The remaining portion of the seed layer 216 forms a through via 222 with the conductive material 220.

In FIG. 16, the integrated circuit die 224 is adhered to the dielectric layer 214 to And the SMD/IPD 226 is bonded to the exposed portion of the metallization pattern 212. Prior to bonding to the dielectric layer 214, the integrated circuit die 224 can be processed to form an integrated circuit in the integrated circuit die 224 in accordance with an applicable process. For example, a device such as a transistor, a diode, a capacitor, a resistor, or the like may be formed on the semiconductor substrate and/or the semiconductor substrate, such as a semiconductor wafer, and may be on the semiconductor substrate or The interconnect structures formed by the metallization patterns in the plurality of dielectric layers are interconnected to form an integrated circuit. For example, by means of a plating process, a die attach 228, such as a conductive pillar or via (eg, including a metal such as copper), is formed externally of the integrated circuit die 224 to be mechanically coupled and electrically coupled to the corresponding integrated circuit crystal. The particles 224, which are referred to as the corresponding active sides of the integrated circuit die 224. Dielectric material 230 may be formed over integrated circuit die 224 and die attach 228 by spin coating, lamination, CVD, or the like. Adhesive 232 may be applied to the back side of integrated circuit die 224, such as to the back side of the semiconductor wafer. Adhesive 232 can be any suitable adhesive, epoxy compound, glue, or the like. The integrated circuit die 224 can be singulated by sawing or cutting and adhered to the dielectric layer 214 by an adhesive 232 using, for example, a pick and place tool.

SMD/IPD 226 is attached between exposed portions of metallization pattern 212, such as pads. The SMD/IPD 226 can be attached to the exposed portion of the metallization pattern 212 using, for example, a pick and place tool, and the SMD/IPD 226 can be bonded to the exposed portion by metal to metal bonding, solder reflow, or the like. In some embodiments, SMD/IPD 226 is a low resistance resistor, for example having a resistance of less than about 0.1 ohms, and more particularly less than about 0.05 ohms. In other embodiments, other components, such as wire bonds or other acceptable connectors, may be used as the antifuse between the exposed portions of the metallization pattern 212, such as pads. When wire bonding is used, any acceptable wire bonding technique can be used to form a wire bond on the exposed portion of the metallization pattern. Other suitable techniques for forming other connections may be understood by those of ordinary skill in the art.

In Figure 17, package 234 is formed on different components. The package 234 may be a molding compound, an epoxy compound, or the like, and may be used by compression molding, transfer molding, or the like. In FIG. 18, after hardening, the package 234 is subjected to a polishing process to expose the through via 222 to the die connection 228. After the polishing process, the top surfaces of the through via 222, the die attach 228, and the package 234 are flush. The SMD/IPD 226 can remain embedded in the package 234.

In FIG. 19, a dielectric layer 236 is formed over the package 234, the vias 222, and the die attach 228. In some embodiments, the dielectric layer 236 is formed of a polymer, which may be a light sensitive material such as PBO, polyamidoamine, BCB, or the like, which can be easily patterned using a lithographic etch mask. . In other embodiments, dielectric layer 236 is formed of, for example, a nitride of tantalum nitride; an oxide such as hafnium oxide, PSG, BSG, BPSG, or the like. Dielectric layer 236 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. Dielectric layer 236 is then patterned to form openings to expose through via 222 and die attach 228. Patterning is an acceptable process, such as exposing dielectric layer 236 when the dielectric layer is a light sensitive material, or etching using anisotropic etching.

In FIG. 20, a seed layer 238 is formed over the dielectric layer 236 and in the opening of the dielectric layer 236. In some embodiments, the seed layer 238 is a metal layer that can be a single layer or a composite layer comprising a plurality of sub-layers of different materials. In some embodiments, the seed layer 238 includes a titanium layer and a copper layer over the titanium layer. For example, the seed layer 238 can be formed using PVD or a similar method.

On the seed layer 238, a photoresist 240 is formed and patterned. The photoresist 240 can be formed using spin coating or the like, and can be exposed for patterning. The pattern of the photoresist 240 corresponds to the metallization pattern. Patterning is formed through the opening of the photoresist 240 to expose the seed layer 238.

In the opening of the photoresist 240 and on the exposed portion of the seed layer 238, A conductive material 242 is formed. The conductive material 242 can be formed by a plating process such as electroplating or electroless plating, or the like. Conductive material 242 can comprise a conductive material such as a metal such as copper, titanium, tungsten, aluminum, or the like.

In FIG. 21, the photoresist 240 and a portion of the seed layer 238 on which the conductive material 242 is not formed are removed. The photoresist 240 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist 240 is removed, the exposed portions of the seed layer 238 are removed using an acceptable etching process, such as wet or dry etching. The remaining portion of the seed layer 238 forms a metallization pattern 244 with the conductive material 242.

In FIG. 22, the processes described above with respect to FIGS. 19 through 21 are repeated to form dielectric layers 246 and 450 and metallization patterns 248 and 252. In some embodiments, these dielectric layers and metallization patterns are omitted, while in other embodiments, more or less dielectric layers and metallization patterns may be formed. As shown in FIG. 22, the metallization pattern 252 includes a lower metal 254 and pads 256 and 258. Moreover, similar to the process of FIG. 19, a dielectric layer 251 is formed on the metallization pattern 252 and the dielectric layer 250. Dielectric layer 251 is patterned to expose lower metal 254 and pads 256 and 258 in metallization pattern 252.

In FIG. 23, SMD/IPD 260 is coupled between pads 256 and 258 of metallization pattern 252. The SMD/IPD 260 can be attached to the pads 256 and 258 of the metallization pattern 252 using a pick and place tool, and the SMD/IPD 260 can be bonded to the pads 256 and 258 by metal to metal bonding, solder reflow, or the like. In some embodiments, SMD/IPD 260 is a low resistance resistor, for example having a resistance of less than about 0.1 ohms, and more specifically less than about 0.05 ohms. In other embodiments, other components may be used, such as wire bonding or other acceptable connectors as the antifuse between pads 256 and 258 of metallization pattern 252. When wire bonding is used, any acceptable wire bonding technique can be used for forming a wire bond on the exposed portion of the metallization pattern. Other suitable techniques for use in forming other adapters will be understood by those of ordinary skill in the art.

For example, using a suitable ball placement process, forming on the lower metal 254 External connectors 262, such as solder balls, such as ball grid array (BGA) balls. In some embodiments, the external connector 262 includes solder, such as a Sn-Ag alloy, a Sn-Ag-Cu alloy, or the like, and may be lead-free or lead-containing.

In Fig. 24, carrier delamination is performed to detach (delamination) the carrier 200 from the upper structure. According to some embodiments, delamination comprises projecting light, such as laser light or UV light, onto the surface of the release layer 202 such that the release layer 202 decomposes under photothermal conditions and the carrier 200 can be removed. The structure is then flipped over and placed on the dicing tape 264.

In FIG. 25, an opening through dielectric layer 204 is formed to expose portions of metallization pattern 212. The exposed portions of the metallization pattern 212 form pads 270, 272, 274, 276, 278, and 280. For example, openings can be formed using laser drilling, etching, or the like.

In FIG. 26, SMD/IPD 282 is coupled between pads 272 and 274 of metallization pattern 212. For example, SMD/IPD 282 can be attached between pads 272 and 274 of metallization pattern 212 using a pick and place tool, and SMD/IPD 282 can be bonded to the pad by metal to metal bonding, solder reflow, or the like. 272 and 274. In some embodiments, SMD/IPD 282 is a low resistance resistor, for example having a resistance of less than about 0.1 ohms, and more specifically less than about 0.05 ohms. In other embodiments, other components may be used, such as wire bonding or other acceptable connectors as the antifuse between pads 272 and 274 of metallization pattern 212. When wire bonding is used, any acceptable wire bonding technique can be used for forming a wire bond on the exposed portion of the metallization pattern. Other suitable techniques for use in forming other adapters will be understood by those of ordinary skill in the art.

For example, external connectors, such as solder bumps, metal posts, the like, or, for example, metal, are formed on pads 278 and 280 of metallization pattern 212 using a suitable bump process, plating process, the like, or a combination thereof. The combination with the solder on it. In some embodiments, the external connector 284 includes solder, such as a Sn-Ag alloy, a Sn-Ag-Cu alloy, or the like, and may be lead-free or lead-containing.

The foregoing process illustrated in Figures 10 through 26 illustrates various placements of SMD/IPD 226, 260 and 282 in a non-singulated package. In other embodiments, SMD/IPD 226, 260, and 282 can be placed in fewer or more locations within the package. The foregoing figures only illustrate the example locations where the SMD/IPD is located. Furthermore, other adapters can be used, such as wire bonding or the like, in combination with SMD/IPD or at SMD/IPD. Those modifications will be understood by those of ordinary skill in the art.

In Figure 27, package 400 is attached to a corresponding unsingulated package formed in Figures 10-26. Package 400 can be any package, and as previously described, typically each includes a substrate 402 that can be an insert to which die 404 is adhered. The die 404 is electrically coupled to the substrate 402 by wire bonding. The die 404 is further packaged on the substrate 402 by an encapsulant 406, which may be a molding compound, an epoxy compound, or the like. For example, the package 400 can be attached to a non-singulated package using a pick and place tool and reflowing the external connectors 284. Thereafter, a primer material 408 is applied between the package 400 and the unsingulated package to surround components between the package 400 and the unsingulated package, such as the SMD/IPD 282 and the external connectors 284. Thereafter, the primer material 408 is hardened.

Figure 28 illustrates a package-on-package structure after singulation by cutting or sawing. The package on package includes a package 401, which is typically formed by the process illustrated in FIGS. 10-26, and includes a package 400. In FIG. 29, the package-on-package structure is attached to a substrate 410, such as a PCB, by an external connector 262 that can be reflowed to attach the substrate 410. Then, a primer material 412 is applied between the package 401 and the substrate 410 to surround the components formed between the package 401 and the substrate 410, such as the SMD/IPD 260 and the external connector 262. Thereafter, the primer material 412 is hardened.

30A through 30D illustrate the contents of an embodiment in which an SMD/IPD is attached. One of ordinary skill in the art will understand how these contents can be applied to the processes illustrated in Figures 10-29. In FIG. 30A, pads 502 and 504 are formed on dielectric layer 500, which may be portions of a metallization pattern. Then, a dielectric layer 506 is formed over the dielectric layer 500 and the pads 502 and 504. The dielectric layer 506 is then patterned to form openings that expose portions of the pads 502 and 504. Patterning can be an acceptable process, such as exposing dielectric layer 214 to light, etching using anisotropic etching, using laser drilling, or the like, when the dielectric layer is a light sensitive material. In FIG. 30B, spacer material 508, such as spacer material 310 of FIG. 3, may be formed on dielectric layer 506 between pads 502 and 504 by printing, jetting, or the like. In FIG. 30C, solder 510 can be formed on pads 502 and 504 by any acceptable process, such as printing, electroplating, or the like. In FIG. 30D, SMD/IPD 512 is in contact with solder 510, and solder 510 is reflowed to attach SMD/IPD 512. SMD/IPD 512 can contact spacer material 508.

In some embodiments, as shown in FIG. 31, SMD/IPD 512 is encapsulated in an encapsulant 514, which may be a primer material, a molding compound, an epoxy compound, or the like. The encapsulant 514 can be a different material composition than the spacer material 508. In other embodiments, as shown in Figures 32A and 32B, another spacer material 518 can be formed on substrate 516 that is opposite SMD/IPD 512. In FIG. 32A, spacer material 518, such as spacer material 328 of FIG. 5, may be formed over the area of substrate 516 by printing, spraying, or the like. In FIG. 32B, substrate 516 is attached to the package to which SMD/IPD 512 is attached by reflowing an external connector (not shown). Then, the primer material 520 is applied and hardened between the substrate 516 and the dielectric layer 506 and in the vicinity of the SMD/IPD 512. Spacer material 518 can contact SMD/IPD 512. The primer material 520 can be a material composition that is different from one or both of the spacer material 508 and the spacer material 518.

The processes shown in Figs. 30A to 30D and 31 can be applied to the above SMD/IPD 226. In this case, dielectric layer 500 corresponds to dielectric layer 204; pads 502 and 504 are located in metallization pattern 212; and dielectric layer 506 corresponds to dielectric layer 214. The patterned and patterned dielectric layer 506 shown in FIG. 30A corresponds to the patterned and patterned dielectric layer 214 shown in FIG. The processing in Figs. 30B to 30D corresponds to the processing occurring in Fig. 16. The package 514 in FIG. 31 corresponds to the package 234 formed in FIG.

The processing in FIGS. 30A to 30D, 31 and 32A to 32B can be applied to the above-described SMD/IPD 260. In this case, dielectric layer 500 corresponds to dielectric layer 250; pads 502 and 504 correspond to pads 256 and 258 in metallization pattern 252; and dielectric layer 506 corresponds to dielectric layer 251. The formed and patterned dielectric layer 506 shown in FIG. 30A corresponds to the patterned and patterned dielectric layer 251 of FIG. The processing in Figs. 30B to 30D corresponds to the processing occurring in Fig. 23. The package 514 of Figure 31 corresponds to the primer material 412 formed in Figure 29. The spacer material 518 of FIG. 32A is formed on the substrate 410 before the substrate 410 is attached to the package 401, and the attachment substrate 516 described in FIG. 32B corresponds to the attachment substrate 410 to the package 401 described in FIG. .

The processing in FIGS. 30A to 30D, 31 and 32A to 32B can be applied to the above-described SMD/IPD 282. In this case, dielectric layer 500 corresponds to dielectric layer 214; pads 502 and 504 correspond to pads 272 and 274 in the metallization pattern; and dielectric layer 506 corresponds to dielectric layer 204. The formation of the dielectric layer 506 described in FIG. 30A corresponds to the formation of the dielectric layer 204 described in FIG. 10, and the patterning of the dielectric layer described in FIG. 30A corresponds to that described in FIG. Patterning of dielectric layer 204. The processing in Figs. 30B to 30D corresponds to the processing occurring in Fig. 26. The package 514 of Figure 31 corresponds to the primer material 408 formed in Figure 27. The spacer material 518 of FIG. 32A may be formed on the substrate 402 before the package 400 is attached to the substrate 401, and the attachment substrate 516 described in FIG. 32B corresponds to the attachment package 400 to FIG. Granulated package.

Figures 33A through 33D illustrate the contents of an embodiment similar to the attachment of SMD/IPD of Figures 30A through 30D. It will be understood by those of ordinary skill in the art how these contents can be applied to the processes described above with respect to Figures 10-29. For a brief description, a description of the description of the same components in FIGS. 30A through 30D is omitted here. In FIG. 33A, dielectric layer 506 is further patterned to form a gap 540 between pads 502 and 504. In FIG. 33B, spacer material 542, such as spacer 316 in FIG. 4A, may be formed in gap 540 and on dielectric layer 506 between pads 502 and 504 by printing, spraying, or the like. In Figure 30C Solder 510 is formed on pads 502 and 504. In FIG. 30D, SMD/IPD 512 is in contact with solder 510 and solder 510 is reflowed to attach SMD/IPD 512. SMD/IPD 512 can contact spacer material 542.

In some embodiments, as shown in FIG. 34, the SMD/IPD 512 is then packaged with an encapsulant 514, which may be a primer material, a molding compound, or the like. The encapsulant 514 can be a different material composition than the spacer material 542. In other embodiments, as shown in FIGS. 35A and 35B, another spacer material 518 can be formed on substrate 516 that can be opposed to SMD/IPD 512. In FIG. 35, a spacer material 518, such as spacer material 328 of FIG. 6, may be formed over the area of substrate 516 by printing, spraying, or the like. In FIG. 35B, substrate 516 is attached to the package to which SMD/IPD 512 is attached, such as by reflowing an external connector (not shown). Thereafter, the primer material 520 can be applied and hardened between the substrate 516 and the dielectric layer 506 and in the vicinity of the SMD/IPD 512. Spacer material 518 can contact SMD/IPD 512. The primer material 520 can be a material composition that is different from one or both of the spacer material 542 and the spacer material 518.

Similar to the discussion of FIGS. 30A through 30D, 31 and 32A through 32B, the processes in FIGS. 33A through 33D, 34 and 35A through 35B are applicable to SMD/IPD 226, 260 and 282. It will be apparent to those skilled in the art that the corresponding dielectric layers 214, 251 and 204 and the gap 540 can be patterned during the patterning of the dielectric layers 214, 251 and 204 described in Figures 13, 22 and 25, respectively. The spacer material 542 may be formed in the gap 540 during the formation of the spacer material 508 described above.

36A to 36C illustrate the contents of an embodiment in which an SMD/IPD is attached. Those of ordinary skill in the art will understand how to apply these to the processes described in Figures 10-29. For the sake of brevity, the discussion of the same components of Figures 30A through 30D is omitted herein. In FIG. 36A, dielectric layer 506 is further patterned to form a gap 540 between pads 502 and 504. In FIG. 36B, on pads 502 and 504, solder 510 is formed. In FIG. 36C, SMD/IPD 512 is in contact with solder 510, and solder 510 is reflowed to attach SMD/IPD. 512.

In some embodiments, as shown in FIG. 37, the SMD/IPD 512 is then encapsulated with an encapsulant 514 that can be left in the gap 540, which can be a primer material, a molding compound, or the like, among others. In an embodiment, as shown in FIGS. 38A and 38B, another spacer material 518 can be formed on substrate 516 that can be opposed to SMD/IPD 512. In FIG. 38A, spacer material 518, such as spacer material 328 of FIG. 6, may be formed over regions of substrate 516 by printing, spraying, or the like. In FIG. 38B, substrate 516 is attached to the package to which SMD/IPD 512 is attached, such as by reflowing an external connector (not shown). Thereafter, the primer material 520 can be applied and hardened between the substrate 516 and the dielectric layer 506 and adjacent to the SMD/IPD 512. The primer material 520 can flow into the gap 540.

The processes in Figures 36A through 36C, 37 and 38A through 38B can be applied to SMD/IPD 226, 260 and 282, similar to Figures 30A through 30D, 31 and 32A through 32B. It will be understood by those skilled in the art that the corresponding dielectric layers 214, 251 and 204 and the gap can be patterned during the patterning of the dielectric layers 214, 251 and 204 described in Figures 13, 22 and 25, respectively. 540. The package 514 may correspond to the package 234 of FIG. 17, the primer material 408 of FIG. 27, or the primer material 412 of FIG.

Embodiments may have advantages. The use of antifuse outside the integrated circuit die simplifies the circuit and makes it more reliable. In some prior applications, fuses may be present in the integrated circuit die and the fuses are arranged using either electrical or laser cutting. In those applications, the fuse portion of the fuse has a large thickness, which makes electro-burning or laser-cutting difficult and causes the fuse to not be blown after the electric or laser cutting. In some embodiments, the antifuse is disposed in the package outside of the integrated circuit die to arrange the circuit. This is to avoid the need to blow the fuse. Moreover, in some embodiments, the flexibility to configure the antifuse can be increased.

Some embodiments may achieve other advantages. In some examples, fixing the SMD/IPD to the structure can cause a gap between the SMD/IPD and the structure. For example, if the bottom The glue material is formed in the vicinity of the SMD/IPD, so that the primer material does not flow into the gap, and an air gap can be formed in the gap. During thermal cycling, gas expansion can cause structural failure, much like a popcorn kernel burst. By having spacer material between the SMD/IPD and the structure and/or by spacing the gap between the SMD/IPD and the structure, air gaps can be reduced or avoided, so little or no air is present during thermal cycling Caused a malfunction.

An embodiment of the present disclosure provides a package structure. The package structure includes integrated circuit dies, redistribution structures, antifuse, and external connections. The integrated circuit die is embedded in the package. The redistribution structure is on the package and is electrically coupled to the integrated circuit die. The anti-fuse is external to the integrated circuit die and redistribution structure. The antifuse is mechanically coupled and electrically coupled to the redistribution structure. The external linker is on the redistribution structure and the redistribution structure is between the outer linker and the package.

Another embodiment of the present disclosure provides a package structure. The package structure includes a die, a package, a redistribution structure, and an antifuse. The die includes an integrated circuit, and the die attach is on the active side of the die and is electrically coupled to the integrated circuit. The package encapsulates the die at least laterally. The redistribution structure is on the package and is adjacent to the package. At least a portion of the redistribution structure is directly coupled to the die attach. The antifuse is mechanically coupled and electrically coupled to the outside of the redistribution structure.

Another embodiment of the present disclosure provides a method. The method includes packaging an integrated circuit die in a package; forming a redistribution structure adjacent the package, the redistribution structure including a pad; and mechanically attaching an antifuse to the pad.

Another embodiment of the present disclosure provides a structure. The structure includes a first package and a package assembly attached to the first package by an external connector. The first package includes means attached to the first pad and the second pad. The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof. The device is attached to the first pad and the second pad via a dielectric layer. The first spacer material is laterally located between the first pad and the second pad and is between the device and the dielectric layer. The package surrounds the device and the spacer material.

Another embodiment of the present disclosure provides a structure. The structure includes a first package. The first package includes an integrated circuit die, and the integrated package is at least laterally packaged with the first package, a redistribution structure on the integrated circuit die and the first package, and a device. The redistribution structure includes a first pad, a second pad, and a dielectric layer. The device is attached to the first pad and the second pad via a dielectric layer. The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof. The recess is in the dielectric layer between the first pad and the second pad.

Another embodiment of the present disclosure provides a method. The method includes patterning an opening through a dielectric layer to expose the first pad and the second pad. The dielectric layer is located in a redistribution structure in the first package. The method also includes forming a first spacer material on the dielectric layer between the first pad and the second pad, and attaching the device to the first pad and the second pad after forming the first spacer material. The device is a surface mount device (SMD), an integrated passive device (IPD), or a combination thereof. The first spacer material is between the device and the dielectric layer.

The foregoing is a summary of the features of the embodiments, and those skilled in the art can understand the various aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages as the embodiments described herein. A person skilled in the art should understand that the present invention is not limited to the spirit and scope of the disclosure, and those skilled in the art can make various changes, substitutions and substitutions without departing from the spirit and scope of the disclosure.

40B‧‧‧Package

42‧‧‧Integrated circuit die

74‧‧‧SMD/IPD

46‧‧‧Dielectric materials

44‧‧‧Packaged die attach

50‧‧‧ Front redistribution structure

48‧‧‧Adhesive

54‧‧‧Dielectric layer

52‧‧‧metallized pattern

56‧‧‧Package

58‧‧‧through path

62‧‧‧metallized pattern

64‧‧‧Dielectric layer

66, 68, 70, 72‧‧‧ pads

60‧‧‧Backrest structure

76‧‧‧Under metal

78‧‧‧External connectors

82‧‧‧External connectors

80‧‧‧solder resistance layer

Claims (10)

A semiconductor package structure includes: a first package including a device attached to a first pad and a second pad, the device being a surface mount device (SMD), an integrated passive device, IPD), or a combination thereof, the device is attached to the first pad and the second pad via a dielectric layer, the first spacer material being laterally located between the first pad and the second pad and located Between the device and the dielectric layer, the first spacer material does not extend beyond the edge of the device, the package surrounds the device and the first spacer material; and the package assembly is attached by an external connector To the first package. The semiconductor package structure of claim 1, wherein the package component is a substrate, and the external connectors are attached to a corresponding under-metal via the dielectric layer, the package system a primer material that further surrounds the outer connectors. The semiconductor package structure of claim 2, further comprising a second spacer material between the device and the substrate, the package further surrounding the second spacer material. The semiconductor package structure of claim 2, wherein the package component is a second package, the external connectors are attached to a corresponding connection pad via the dielectric layer, the package being a primer material, It further surrounds the external connectors. The semiconductor package structure of claim 4, further comprising a second spacer material between the device and the second package, the package further surrounding the second spacer material. The semiconductor package structure of claim 1, wherein the package further surrounds the integrated circuit die, the dielectric layer is located in the redistribution structure, and the redistribution A structure is located on the package and between the package and the package assembly. The semiconductor package structure of claim 1, wherein the composition of the package is different from the composition of the first spacer material. The semiconductor package structure of claim 1, wherein the dielectric layer has a recess between the first pad and the second pad, the first spacer material being at least partially located in the recess In the slot. A semiconductor package structure comprising: a first package comprising: an integrated circuit die that is at least laterally encapsulated by a first package; and a redistribution structure that is located in the integrated circuit die and the first package Optionally, the redistribution structure includes a first pad, a second pad, and a dielectric layer; and a device attached to the first pad and the second pad via the dielectric layer, the device being surface mounted a device (SMD), an integrated passive device (IPD), or a combination thereof, wherein the recess is located in the dielectric layer between the first pad and the second pad, wherein the first pad and the second pad have a dimension measured along a plane parallel to a major surface of the dielectric layer, and the dimension is measured along a first direction, the first direction being perpendicular to the second direction, the second direction being directed by the first pad The second pad, and the groove has a length greater than the size on the plane. A method of forming a semiconductor package, comprising: patterning an opening through a dielectric layer to expose a first pad and a second pad, the dielectric layer being located in a redistribution structure in the first package; forming a first spacer Material on the dielectric layer between the first pad and the second pad; and after forming the first spacer material, attaching the device to the first pad and the second pad, the device surface A mounting device (SMD), an integrated passive device (IPD), or a combination thereof, the first spacer material being between the device and the dielectric layer.