JP2009070882A - Semiconductor chip package and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily take out an electrode to the side opposite to a substrate without the need for a through wiring technique for boring a through hole in the semiconductor substrate and charging a metal material in a semiconductor package in which it is necessary to take out the electrode lead to the side opposite to the substrate. <P>SOLUTION: The present invention relates to integral packaging of a glass substrate or high-heat-dissipation substrate provided on one surface, an external electrode provided on a surface opposite thereto, and a semiconductor chip connected to the external electrode. The semiconductor chip package includes a post electrode component with wiring having a top-surface wiring pattern provided by forming a post electrode supported on the glass substrate or high-heat-dissipation substrate and the wiring connected to the post electrode. The semiconductor chip is mounted on the post electrode component with the wiring and sealed with a resin. On the resin-sealed surface, the external electrode is formed a top of the post electrode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor chip package optimal for an image sensor having a glass substrate or a high heat dissipation substrate on one side and taking out external electrodes from the opposite side, or a package for LSI with high power, and a method for manufacturing the same.

  In recent years, a camera has been mounted on a mobile phone, and with the demand for downsizing and thinning of digital cameras, the demand for downsizing of an image capturing unit and a processing unit has become very strong. Advances in IC design / manufacturing technology enable highly integrated circuits and low power consumption, and image sensor packages in which an image capturing unit and a processing unit are integrated and packaged are used.

  In such an image sensor package, it is necessary to take out an electrode opposite to the image sensor surface. Conventionally, such an electrode take-out is performed by providing a through hole in a semiconductor substrate and filling the through hole with a metal material. It is done using wiring technology. FIG. 26 is a diagram for explaining a conventional penetration technique disclosed in Patent Document 1. In FIG. The silicon substrate shown in FIG. 26 is the original semiconductor substrate. A wiring / electrode pad layer is provided on the upper surface via an insulating layer. The inner peripheral surface and the back surface of the opening of the silicon substrate are covered with an insulating film. The thickness of this silicon substrate is reduced and is relatively thin. Since the thickness of the silicon substrate can be reduced, etching is facilitated and the formation of the insulating film is facilitated. A glass support is provided on the upper portion of the silicon substrate. Another substrate is attached to the back side of the silicon substrate. Another substrate forms a through-hole at a position corresponding to the opening corresponding to the opening, and a through-wiring is formed in the opening and the hole, and is connected to an external electrode through the through-wiring.

  As described above, the silicon substrate secures the strength as a semiconductor chip by attaching another substrate, thereby making it possible to reduce the thickness of the original silicon substrate. By thinning the silicon substrate, the time required for the silicon etching process for forming the through wiring, the insulating film forming process, the insulating film etching process, the metal material filling process, etc. is shortened, and the manufacturing cost of the semiconductor device is reduced. Can be reduced.

  However, although the exemplary image sensor package has thinned the silicon substrate, there is still a need for a through wiring technique in which an opening is formed in the silicon substrate and a metal material is filled therein.

Similarly to an image sensor package, a technology that facilitates wiring to an external electrode provided on the opposite side of the heat sink is also required in a package in which a high-power LSI chip and a heat sink therefor are integrated.
Japanese Patent Laid-Open No. 2007-158078

  If you are going to take out the electrode on the opposite side of the lighting surface with the current image sensor package, or on the opposite side of the heat sink in the package with the integrated heat sink, you must use a through electrode (through wiring), so the manufacturing process Is complicated and expensive.

  The present invention solves such a problem, and in a semiconductor chip package where an electrode needs to be taken out on the opposite side of the substrate, such as an image sensor package or a heat sink integrated package, a metal material is formed by opening a through hole in the semiconductor substrate. The object is to easily take out the electrode on the opposite side of the semiconductor substrate without the need for filling through wiring technology. As a result, an image sensor or a high heat dissipation package can be manufactured without preparing new expensive equipment.

  A semiconductor chip package and a manufacturing method thereof according to the present invention include a substrate provided on one side, a semiconductor chip mounted on the substrate, and an external electrode connected to the semiconductor chip located on the opposite side of the substrate. Package together. A post electrode part with wiring in which a post electrode supported by the substrate and a wiring connected to the post electrode are formed and an upper surface wiring pattern is formed is provided. A semiconductor chip is mounted on the post electrode part with wiring and resin-sealed. The tip of the post electrode is used as an external electrode on the resin-sealed surface, or an external electrode is formed.

  Further, in the method of manufacturing a semiconductor chip package of the present invention, the post electrode supported by the support plate and the wiring connected to the post electrode are formed, and the post electrode component with wiring in which the upper surface wiring pattern is formed is formed. Then, a semiconductor chip is mounted on the post electrode part with wiring and resin-sealed. Thereafter, the support plate is peeled off, and the substrate can be attached to the position.

  The semiconductor chip is an image sensor chip or a large power LSI chip that requires high heat dissipation, and the substrate is a glass substrate or a high heat dissipation substrate. The external electrode can be aligned with the external electrode of another double-sided electrode package so that the connection portion overlaps, and can be laminated and bonded to the other double-sided electrode package.

  Post electrode parts with wiring pattern a metal seed layer to be a wiring pattern with a lithography process or nano metal particles on a glass substrate or an insulating layer formed on a high heat dissipation substrate, A wiring layer is grown by plating to form a wiring layer pattern, and a post electrode is formed thereon in the same manner as the wiring layer.

  According to the present invention, a semiconductor package in which an electrode needs to be taken out on the side opposite to the substrate, such as an image sensor or a high heat dissipation package, can be manufactured by a simple method. There is no need for through-wiring technology that fills a semiconductor material by opening a through hole in a semiconductor substrate, electrodes can be easily taken out on the opposite side of the semiconductor substrate, and the manufacturing process can be performed without preparing new expensive equipment. Can be built.

  Hereinafter, the present invention will be described based on examples. First, as a first embodiment, an example in which the present invention is embodied in an image sensor chip package will be described with reference to FIGS. 1A and 1B are diagrams showing post electrode parts with wiring shown in a state where a large number of them are integrally connected. FIG. 1A is a perspective view thereof, and FIG. 1B is a sectional view taken along line XX ′ in FIG. Show. In the illustrated post electrode part with wiring, the upper surface wiring pattern is formed by forming not only the post electrode (internal connection electrode) supported by the support portion but also the wiring connected thereto. This post electrode component with wiring is configured by integrally connecting a plurality of post electrodes and wiring by a support portion on the back surface. The post electrode is not limited to the cylindrical shape as illustrated, and may be a columnar (bar-shaped) shape including a rectangular shape, a polygonal shape, and the like.

  In the example of FIG. 1, a transparent glass substrate is used as the support portion. A metal seed layer to be a wiring pattern is formed on the entire surface of the transparent glass substrate (for example, a sputter layer or a nano metal material is coated). As the seed layer, for example, gold, silver, copper, or palladium foil that enables copper plating can be used. The wiring layer pattern is completed by applying a resist on the seed layer, exposing and developing the pattern, further etching, removing the resist. A wiring layer is grown on the seed layer by plating. Further thereon, resist application and development are performed to form a post electrode portion, and the post portion is plated and grown. Alternatively, the lithography process can be omitted by patterning the seed layer directly with nano metal particles. This direct patterning is a method in which nano metal particles such as copper are contained in an organic solvent and a desired pattern is drawn by an ink jet method which is practically used in a printer. In the same manner as described above, a resist is applied and developed to form a post electrode portion, and the post portion is plated and grown. Thus, the post electrode part with wiring is completed.

  FIG. 2 shows an example in which an image sensor (semiconductor LSI chip) is mounted on a post electrode part with wiring. An image sensor (semiconductor LSI chip) is fixed and electrically connected using the wiring layer formed on the post electrode part with wiring as a bonding pad region. This fixing and connection can be performed by flip chip bonding. Further, a microlens can be mounted between the light condensing surface side of the image sensor and the glass substrate. In this way, the image sensor is mounted on the back side of the transparent glass substrate.

  FIG. 3 is a view showing a state in which a semiconductor LSI chip is connected and fixed to a post electrode part with wiring and then is sealed with resin. Although the figure shows only one part, in reality, a large number of parts are connected and placed in a mold and filled with resin. Thus, transfer molding is performed so as to fill a space from the tip of the electrode post to the lower surface of the transparent glass substrate, or resin sealing is performed using a liquid resin (a material is, for example, an epoxy system). When the tip of the post electrode is slightly covered with resin when sealed, a step of lightly grinding the surface to expose the metal surface at the tip may be added.

  FIG. 4 is a diagram showing a state in which bump electrodes for external connection are formed. The tip of the post electrode exposed from the resin sealing portion can be used as an external electrode. However, as shown in FIG. 4, a bump electrode connected to the post electrode can be formed and used as the external electrode. In actual manufacturing, after this, the product is completed after being cut into individual chips and separated into pieces. This completes an image sensor chip package in which bump electrodes are formed as external electrodes on the opposite side of the transparent glass substrate without the need for through electrodes as in the prior art. The image sensor chip package thus completed can be easily connected to another package such as a signal processing LSI chip package before being singulated.

  5 and 6 are schematic cross-sectional views showing a mounting state in which the image sensor chip package illustrated in FIG. 3 before the bump electrode formation is laminated and bonded to the signal processing LSI chip package. FIG. 5 shows a state before connection, and FIG. 6 shows a state after connection. The signal processing LSI chip package is configured as a double-sided electrode package (PKG). As shown in the figure, the image sensor chip package located on the upper surface is aligned with the signal processing LSI chip package located on the lower surface so that the connection portion overlaps, and the protruding electrode (post electrode) of the connection portion passes through the furnace body. Are temporarily melted by heating.

  The manufacture of the image sensor chip package shown in FIGS. 5 and 6 is as described above with reference to FIGS. Hereinafter, the manufacture of a double-sided electrode package such as a signal processing LSI (logic LSI) chip package will be described step by step with reference to FIGS.

  FIG. 7 is a diagram showing an LSI chip (signal processing LSI chip) bonded and connected to a multilayer organic substrate. The LSI chip is illustrated as being bonded to a multilayer organic substrate with a die bond material and connected to the uppermost wiring pattern of the organic substrate by a bonding wire. In the uppermost wiring pattern of the multilayer or single layer organic substrate, a bonding metal pad portion to be a bonding wire connection electrode is formed and a wiring to the pad portion is formed. The metal pad portion on the front surface of the multilayer or single layer organic substrate and the LSI chip are connected by an Au bonding wire. Alternatively, the LSI chip can be flip-chip bonded to the organic substrate (not shown). In this case, the LSI chip is flip-chip bonded to the uppermost wiring pattern of the multilayer or single-layer organic substrate using a normal technique.

  Multi-layer or single-layer organic substrates are used to form a wiring pattern on each layer of a single-layer two-layer wiring structure or a substrate composed of a plurality of layers, and then bond these substrates together to connect the wiring patterns of each layer as necessary. Through-holes are formed. A conductor layer is formed inside the through hole, and this conductor layer is connected to a land which is an end face electrode portion formed on the back surface side. Such a multi-layer or single-layer organic substrate is known as a collective sealing organic substrate (BGA: Ball Grid Array) in which a small solder material called “solder ball” (bump) is mounted on the back surface (BGA: Ball Grid Array). Yes.

  FIG. 8 is a diagram showing the post electrode fixed and connected. Post electrode structures integrally connected by a support portion are fixed together and electrically connected to predetermined positions of the wiring pattern of the organic substrate. As a method for fixing and connecting the post electrode, (1) ultrasonic bonding, (2) connection using a conductive paste such as silver paste, (3) solder connection, (4) connection electrode provided on the organic substrate side While the metal pad portion is provided with a concave portion, the post electrode structure side can be formed by a method of providing a convex portion and inserting / crimping or inserting and crimping.

  At the stage where the post electrodes are fixed to the connection electrode metal pad portion (see FIG. 7) arranged at a predetermined position on the wiring pattern of the organic substrate, all the post electrodes are integrally connected by the plate-like support portion. ing.

  FIG. 9 is a diagram showing details of the post electrode structure integrally connected by a plate-like support, and FIGS. 9A and 9B show a single pattern for one double-sided electrode package. A side sectional view and a perspective view are shown, respectively, and FIG. 9C shows a perspective view of a pattern in which four single patterns for four double-sided electrode packages are connected to one. This post electrode structure has the same configuration as that of the post electrode part with wiring described above with reference to FIG. 1, but there is no wiring pattern in FIG. 9 (the configuration having the wiring pattern is shown in FIG. 13). 9) and the support member quality is different, and the support part of FIG. 9 is different in that it is peeled off in a later step.

  The post electrode structure of FIG. 9 is configured by integrally connecting a plurality of post electrodes by a support portion. The integrally connected post electrode structure is manufactured by electroforming.

  The electroforming method itself is a well-known processing method. Electroforming is a method of manufacturing, repairing, or replicating metal products by electroplating, which is basically the same as electroplating, but the plating thickness and plating film are separated. Different from plating. Also, when the plating film is peeled off from the matrix, it is important to control and manage the physical properties of the plating film. As the plating metal of the conductive material grown by electroforming, nickel or copper, a nickel alloy, or a material containing a copper alloy can be used. As the matrix material, stainless steel, which is a general conductive material, can be used. In addition, for example, a silicon substrate is used for the base, and the plating pattern is easily peeled off from the surface so that the plating pattern can be easily peeled off. What is covered with a material such as an oxide film that is thin enough to pass through can be used. It is necessary to select a plating bath composition and plating conditions that do not cause internal stress. In the case of nickel plating, a nickel sulfamate bath is used as the plating bath.

  FIG. 27 is a process diagram showing a method for manufacturing an electroformed part using a photoresist. Hereinafter, although the electroforming method will be described, the manufacturing steps shown in this process diagram can also be applied to the case of plating. In the case of plating (electroless plating), an insulator (transparent glass substrate in FIG. 1) is used instead of a conductor such as stainless steel as a matrix, so that it can function without being peeled off.

  In the electroforming method, as shown in FIG. 27A, a photoresist (non-conductive coating) is applied to the upper surface of a mother die such as stainless steel. Next, an electroforming original plate in which the non-plated portion is covered with a photoresist pattern is formed by pattern printing exposed through a pattern film and subsequent development (FIG. 27B). The thickness of the photoresist pattern of the electroforming master is equal to or greater than the thickness of the product (post electrode or wiring pattern). In the case of the post electrode, it is thicker than the chip thickness of the IC, for example, about 50 μm to 300 μm. To do. Subsequently, a plated metal is formed in the opening of the photoresist pattern (FIG. 27C). An electroformed metal to be electroformed on the anode side is placed in a plating bath (for example, nickel sulfamate solution) maintained at an appropriate temperature, and an electroforming mother mold such as stainless steel is disposed on the cathode side. On the surface of the electroforming mother mold on the cathode side, a photoresist pattern is formed in advance as shown in FIG. When a current is passed, the electroformed metal on the anode side melts and is plated on the opening of the photoresist pattern on the electroformed mother die.

  Next, as shown in FIG. 27D, planarization is performed. Next, when the resist is removed (FIG. 27E), the portion other than the resist portion becomes a wiring pattern or a post electrode as it is. Then, the plated metal is peeled off from the electroforming mother mold (FIG. 27 (f)). It is a feature of the electroforming method that the formed plated metal and the supporting part can be easily peeled off by heat or pressure.

  In order to manufacture the post electrode structure with wiring illustrated in FIG. 13 to be described later, the steps shown in FIGS. 27A to 27D are repeated twice, and a wiring pattern is formed on the support portion in the first step. After that, a post electrode connected to the wiring pattern is formed in the second step.

  Thus, the post electrode structure is formed by growing the post electrode (internal connection electrode) or the post electrode with wiring by using lithography and plating on the conductive material (electroforming mother mold) as the support portion. A post electrode pattern integrated with the support portion or a post electrode pattern with wiring is formed.

  Thereafter, the post electrode structure shown in FIG. 9 is connected and fixed on the multilayer organic substrate shown in FIG. 7 to have the configuration illustrated in FIG. 8 described above. FIG. 10 is a view showing a state in which the post electrode structure is connected and fixed on the multilayer organic substrate and then sealed with resin. After the integrally connected post electrode structure is fixed on the multilayer organic substrate, in this state, the front surface of the LSI chip extends to the lower surface of the support portion (the above-described electroformed mother die), that is, the LSI. Transfer molding is performed so as to fill a space between the chip and the support portion, or resin sealing is performed using a liquid resin (material is, for example, epoxy).

  FIG. 11 is a view showing the state after the support portion (electroformed mother die) has been peeled off. By peeling the support portion, the plurality of post electrodes are electrically separated from each other.

  FIG. 12 is a view showing a state where bump electrodes for external connection are formed on the back surface. On the front surface, the tip of the post electrode can be used as it is as an external electrode to be connected to the above-described image sensor chip package. However, as shown in FIG. From the arrangement of the electrodes, it can be arbitrarily taken to the position of the external electrode of the image sensor chip. Therefore, the image sensor chip package can be easily connected in three dimensions.

  This rewiring can be performed by an inkjet method or screen printing. Alternatively, for rewiring, electroless plating can be performed after the seed layer pattern is formed. Alternatively, rewiring can be performed using a post electrode structure with wiring as shown in FIG.

  FIG. 13 is a diagram showing an example of a post electrode structure with wiring, and (A) and (B) show a side sectional view and a perspective view of a single pattern, respectively. The illustrated post electrode structure with wiring has the same configuration as that of FIG. 9 described above, but differs only in that it has wiring. As described above with reference to FIG. 27, not only the post electrode supported by the support portion but also the wiring pattern connected thereto can be formed by electroforming. By such a method, the upper surface wiring pattern is formed in the post electrode structure with wiring shown in FIG. In addition, although illustrated as a single pattern, actually, it is manufactured as a connection pattern in which a plurality are connected in the same manner as in FIG. In the final stage of the manufacturing process, each chip is cut into individual pieces.

  On the multilayer organic substrate (see FIG. 7) to which the LSI chip is bonded and connected, the post electrode structure with wiring illustrated in FIG. 13 is fixed and electrically connected. The subsequent steps can be performed in the same manner as the steps described above with reference to FIGS.

  Next, as a second embodiment of the present invention, an example embodied in a high heat dissipation chip package will be described. 14A and 14B are diagrams showing post electrode parts with wiring shown in a state where a large number of them are integrally connected, FIG. 14A is a perspective view, and FIG. 14B is a cross section taken along line YY ′ in the figure. FIG. The post electrode part with wiring illustrated in FIG. 14 has the configuration illustrated in FIG. 1 only in that a high heat dissipation substrate that functions as a heat sink, a heat spreader, or the like is used instead of the transparent glass substrate illustrated in FIG. 1 described above. Is different.

  An example of manufacture of the post electrode part with wiring illustrated in FIG. 14 is as follows. First, a thin insulating layer is provided on a high heat dissipation substrate. After that, as in FIG. 1, a seed layer is formed on the entire surface (for example, a sputter layer or a nano metal material is coated), then a resist is applied, developed into a wiring pattern, plated and grown, and then a post portion is formed. For this purpose, resist coating and development are performed, and plating is grown. Thus, the plurality of post electrodes and wirings are integrally connected by the high heat dissipation substrate which is the support portion on the back surface.

  FIG. 15 shows an example in which a large power LSI chip is mounted on a post electrode part with wiring. A large power LSI chip that requires high heat dissipation is fixed and electrically connected to the post electrode part with wiring on the high heat dissipation substrate. As a result, a high heat dissipation type LSI chip is mounted on the back side of the high heat dissipation substrate functioning as a heat sink.

  FIG. 16 is a view showing a state in which a high power LSI chip is connected and fixed to a post electrode part with wiring and then is sealed with resin. Transfer molding is performed so as to fill a space from the tip of the electrode post to the lower surface of the high heat dissipation substrate, or resin sealing is performed using a liquid resin (a material is, for example, an epoxy system).

  FIG. 17 is a diagram showing a state in which bump electrodes for external connection are formed. The tip of the post electrode exposed from the resin sealing portion can be used as an external electrode, but a bump electrode connected to the post electrode can be formed as an external connection electrode.

  This completes a high heat dissipation type chip package in which external electrodes are formed on the opposite side of the high heat dissipation substrate functioning as a heat sink without the need for through electrodes as in the prior art. Such a high heat dissipation type chip package can be easily connected to another LSI chip package with relatively low heat dissipation.

  18 and 19 are schematic cross-sectional views showing a mounting state in which the LSI chip package with high power shown in FIG. 16 before bump electrode formation is laminated and joined with another LSI chip package with low power. FIG. 18 shows a state before connection, and FIG. 19 shows a state after connection. The small power LSI chip package is configured as a double-sided electrode package (PKG). This small power LSI chip package can be configured as described above with reference to FIGS. Similar to the above-described configuration, rewiring may be provided on the upper surface of the LSI package.

  As shown in FIG. 18, the large power LSI chip package located on the top surface is aligned with the small power LSI chip package located on the bottom surface so that the connection portion overlaps, and the protruding electrode of the connection portion is temporarily placed through the furnace body. To be joined by heating and melting. FIG. 19 is a diagram showing a state after being connected.

  FIG. 20 is a diagram showing a state in which another LSI chip package is stacked. Even in the case of three or more layers, the LSI with the largest power consumption is brought to the top layer. The illustrated first package corresponds to a large power LSI chip package having the high heat dissipation substrate illustrated in FIG. The illustrated second and third packages correspond to the small power LSI chip package described above. The size of the heat radiating portion is not necessarily limited to the size of the entire surface of the package, but may be any size.

  Next, another method for manufacturing the image sensor chip package having the configuration shown in FIG. 4 or the LSI chip package having the configuration shown in FIG. 17 will be described as a third embodiment of the present invention. FIGS. 21A and 21B are diagrams illustrating a state in which an image sensor (or a large power LSI chip package) is mounted on a post electrode part with wiring. FIG. 21A is a cross-sectional view, and FIG. 21B is a back side of the post electrode part with wiring. (C) is the perspective view seen from the back side in the state which attached the image sensor. FIG. 21 is a view corresponding to FIG. 2 or FIG. 15 described above, but only in that a peelable support plate (electroformed mother die) is used in place of the glass substrate or the high heat dissipation substrate described above. It is different. The post electrode part with wiring shown in FIG. 21 (B) can be manufactured in the same manner as the post electrode structure with wiring shown in FIG. 13, and the support plate shown in FIG. In the same manner as above, it will be peeled off in a later step.

  FIG. 22 is a view showing a state in which a semiconductor LSI chip is connected and fixed to a post electrode part with wiring and then is sealed with resin, as in FIG. 3 or FIG.

  FIG. 23 is a diagram showing the support plate in a peeled state. The support plate prepared by electroforming can be easily peeled off. By peeling the support portion, the plurality of post electrodes are electrically separated from each other.

  FIG. 24 is a view showing a state where a glass substrate or a transparent resin (acrylic, cycloolefin polymer, etc.) having a high light transmittance, or a high heat dissipation substrate is attached to the position where the support plate is peeled off. The substrate is attached using an adhesive such as a thermosetting resin, for example. The substrate may be attached after the following individualization.

  FIG. 25 is a diagram showing a state in which bump electrodes for external connection are formed. The tip of the post electrode exposed from the resin sealing portion can be used as an external electrode. However, as shown in FIG. 25, a bump electrode connected to the post electrode can be formed and used as the external electrode. In actual manufacturing, after this, the product is completed after being cut into individual chips and separated into pieces.

It is a figure which shows the post electrode components with wiring shown in the state connected in large numbers. It is a figure illustrated in the state which mounted | wore the post electrode part with wiring with the image sensor. FIG. 3 is a view showing a state in which an LSI chip is connected and fixed to a post electrode part with wiring and then is resin-sealed. It is a figure shown in the state in which the bump electrode for external connection was formed. FIG. 5 is a schematic cross-sectional view showing a state before the image sensor chip package is stacked and connected to the signal processing LSI chip package. FIG. 5 is a schematic cross-sectional view showing a state after the image sensor chip package is stacked and connected to the signal processing LSI chip package. It is a figure which shows the state which adhere | attached and connected the LSI chip on the multilayer organic substrate. It is a figure shown in the state which fixed and connected the post electrode. It is a figure which shows the detail of the post electrode structure integrally connected by the plate-shaped support part. It is a figure which shows the state which carried out resin sealing after connecting and fixing a post electrode structure on a multilayer organic substrate. It is a figure shown in the state after peeling a support part. It is a figure shown in the state which formed the bump electrode for external connection in the back surface. It is a figure which shows the example of the post electrode structure with wiring. It is a figure which shows the post electrode components with wiring shown in the state connected in large numbers. It is a figure illustrated in the state which mounted | wore the post electrode component with wiring with the large power LSI chip | tip. FIG. 2 is a view showing a state in which a high power LSI chip is connected and fixed to a post electrode part with wiring and then is sealed with resin. It is a figure shown in the state in which the bump electrode for external connection was formed. FIG. 5 is a schematic cross-sectional view showing a state before a high-power LSI chip package is stacked and connected to another low-power LSI chip package. FIG. 10 is a schematic cross-sectional view showing a state after a high-power LSI chip package is stacked and connected to another low-power LSI chip package. It is a figure shown in the state which laminated | stacked 3 steps | paragraphs of LSI chip packages. It is a figure illustrated in the state which mounted | wore the image sensor (or high power LSI chip package) with the post electrode component with wiring. FIG. 17 is a view showing a state in which a semiconductor LSI chip is connected and fixed to a post electrode part with wiring and then is resin-sealed, as in FIG. 3 or FIG. 16. It is a figure shown in the state which peeled the support plate. It is a figure shown in the state which affixed the glass substrate or the transparent resin with good light transmittance, or the high heat dissipation board | substrate in the position which peeled the support plate. It is a figure shown in the state in which the bump electrode for external connection was formed. It is a figure explaining the conventional penetration technique currently disclosed by patent document 1. FIG. It is process drawing which shows the manufacturing method of the electroformed part using a photoresist.

Claims (9)

In a semiconductor chip package in which a substrate provided on one side, a semiconductor chip mounted on the substrate, and an external electrode connected to the semiconductor chip located on the opposite side of the substrate are integrally packaged,
Forming a post electrode supported by the substrate and a wiring connected to the post electrode, and comprising a post electrode component with wiring in which an upper surface wiring pattern is formed;
A semiconductor chip is mounted on the post electrode part with wiring, resin-sealed,
Using the tip of the post electrode as the external electrode on the resin-sealed surface, or forming an external electrode,
A semiconductor chip package consisting of: The semiconductor chip package according to claim 1, wherein the semiconductor chip is an image sensor chip or a large power LSI chip that requires high heat dissipation, and the substrate is a glass substrate or a high heat dissipation substrate. 2. The semiconductor chip package according to claim 1, wherein the external electrode is aligned so that an external electrode of another double-sided electrode package overlaps with a connection portion, and is laminated and joined to the other double-sided electrode package. Manufacturing of a semiconductor chip package in which a substrate provided on one side, a semiconductor chip mounted on the substrate, and an external electrode connected to the semiconductor chip located on the opposite side of the substrate are integrally packaged In the method
Forming a post electrode supported by the substrate and a wiring connected to the post electrode to form a post electrode component with wiring in which a top surface wiring pattern is formed;
A semiconductor chip is mounted on the post electrode part with wiring, resin-sealed,
Using the tip of the post electrode as the external electrode on the resin-sealed surface, or forming an external electrode,
A method for manufacturing a semiconductor chip package. 5. The semiconductor chip package according to claim 4, wherein the semiconductor chip is an image sensor chip or a large power LSI chip that requires high heat dissipation, and the substrate is a glass substrate or a high heat dissipation substrate. The post electrode component with wiring is formed by patterning a metal seed layer to be a wiring pattern by a lithography process or nano metal particles on the insulating layer formed on the glass substrate or the high heat dissipation substrate. 6. The method of manufacturing a semiconductor chip package according to claim 5, wherein a wiring layer is grown by plating to form a wiring layer pattern, and a post electrode is further formed thereon in the same manner as the wiring layer. 5. The semiconductor chip package according to claim 4, wherein the external electrode is aligned so that a connection portion and an external electrode of another double-sided electrode package overlap each other, and is laminated and joined to the other double-sided electrode package. Manufacturing of a semiconductor chip package in which a substrate provided on one side, a semiconductor chip mounted on the substrate, and an external electrode connected to the semiconductor chip located on the opposite side of the substrate are integrally packaged In the method
Forming a post electrode supported by the support plate and wiring connected to the post electrode, forming a post electrode part with wiring in which a top surface wiring pattern is formed;
A semiconductor chip is mounted on the post electrode part with wiring, resin-sealed,
The support plate is peeled off, and the substrate is attached to the position,
Using the tip of the post electrode as the external electrode on the resin-sealed surface, or forming an external electrode,
A method for manufacturing a semiconductor chip package. 9. The semiconductor chip package according to claim 8, wherein the semiconductor chip is an image sensor chip or a large power LSI chip that requires high heat dissipation, and the substrate is a glass substrate, a light transmissive transparent resin, or a high heat dissipation substrate. Manufacturing method.

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