JP2010118614A - Semiconductor device package structure and manufacturing method thereof - Google Patents
Semiconductor device package structure and manufacturing method thereof Download PDFInfo
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- JP2010118614A JP2010118614A JP2008292360A JP2008292360A JP2010118614A JP 2010118614 A JP2010118614 A JP 2010118614A JP 2008292360 A JP2008292360 A JP 2008292360A JP 2008292360 A JP2008292360 A JP 2008292360A JP 2010118614 A JP2010118614 A JP 2010118614A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 28
- 239000010408 film Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 239000002923 metal particle Substances 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910001220 stainless steel Inorganic materials 0.000 claims description 2
- 239000010935 stainless steel Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 32
- 238000005323 electroforming Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000002788 crimping Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
本発明は、半導体LSIチップを含む回路素子を配置して樹脂封止すると共に、該回路素子に接続される外部接続用電極をおもて面に配置した半導体装置パッケージ構造及びその製造方法に関する。 The present invention relates to a semiconductor device package structure in which a circuit element including a semiconductor LSI chip is arranged and resin-sealed, and an external connection electrode connected to the circuit element is arranged on a front surface, and a manufacturing method thereof.
LSIチップの高集積化に伴い、パッケージサイズの縮小化も強く要求されており、様々な実装パッケージ構造が提案されている。近年、半導体ベアチップに貫通電極を形成して積層しようとする開発が盛んに行われている。一方、リアルサイズの両面電極パッケージもこれから製品化される可能性が高い。いずれの技術においても、従来の両面電極パッケージは常に貫通電極構造を必要としているが（特許文献１参照）、現在の貫通電極形成は低抵抗金属を充填するためには低温処理が要求され、半導体プロセスへの適用は難しく、一方、貫通孔の絶縁方法は、高温処理が必要なため半導体の実装プロセスへの適用は困難である。このように、半導体基板への貫通電極の形成とその絶縁方法にはまだ課題が残されていて、貫通電極を必要とせずに配線することが望まれる。 Along with the high integration of LSI chips, there is a strong demand for reducing the package size, and various mounting package structures have been proposed. 2. Description of the Related Art In recent years, developments for forming and stacking through electrodes on a semiconductor bare chip have been actively conducted. On the other hand, real size double-sided electrode packages are also likely to be commercialized. In either technique, the conventional double-sided electrode package always requires a through electrode structure (see Patent Document 1), but the current through electrode formation requires low-temperature processing to fill a low-resistance metal, and the semiconductor On the other hand, it is difficult to apply to a process. On the other hand, the method for insulating a through hole is difficult to apply to a semiconductor mounting process because high temperature treatment is required. As described above, there is still a problem in the formation of the through electrode on the semiconductor substrate and the insulating method thereof, and it is desired to perform wiring without requiring the through electrode.
このような課題を解決するために、特許文献２は、部品化した内部接続用電極構造体を半導体基板上の所定位置に接続することにより、貫通電極を必要とせずに配線する技術を開示する。図１１及び図１２は、特許文献２に開示の半導体装置パッケージを説明する図であり、図１１は、その製造途中の断面図であり、図１２は、完成した状態で示す断面図である。図１１に示すように、導電性材料の支持板に電鋳法により配線パターン及び内部接続用電極を成長させて、支持板と一体に連結した内部接続用電極構造体を形成する。そして、この内部接続用電極構造体を、半導体基板（多層有機基板）おもて面に形成した配線層上の所定位置に接続する。この後、図１２に示すように、回路素子（LSIチップ）を覆う樹脂を充填して樹脂封止した後、支持板を剥がすことにより個々の配線パターン及び内部接続用電極に分離して構成する。この配線パターンにより、複数の内部接続用電極先端とは異なる位置に外部接続用電極を設けることができる。裏面においては、有機基板内部の導体層を介して、外部接続用電極を基板おもて面の配線層に接続する。これによって、簡潔に、しかもコスト的にも安く半導体装置パッケージを製造することが可能となる。 In order to solve such a problem, Patent Document 2 discloses a technique for wiring without connecting a through electrode by connecting a parted internal connection electrode structure to a predetermined position on a semiconductor substrate. . 11 and 12 are diagrams for explaining a semiconductor device package disclosed in Patent Document 2, FIG. 11 is a cross-sectional view in the middle of its manufacture, and FIG. 12 is a cross-sectional view shown in a completed state. As shown in FIG. 11, a wiring pattern and internal connection electrodes are grown on a support plate made of a conductive material by electroforming to form an internal connection electrode structure integrally connected to the support plate. The internal connection electrode structure is connected to a predetermined position on the wiring layer formed on the front surface of the semiconductor substrate (multilayer organic substrate). After that, as shown in FIG. 12, after filling the resin covering the circuit element (LSI chip) and sealing with resin, the support plate is peeled off to separate the wiring patterns and the internal connection electrodes. . With this wiring pattern, external connection electrodes can be provided at positions different from the plurality of internal connection electrode tips. On the back surface, the external connection electrode is connected to the wiring layer on the front surface of the substrate through a conductor layer inside the organic substrate. As a result, it is possible to manufacture a semiconductor device package simply and at low cost.
しかし、このような半導体装置パッケージは、おもて面の配線パターンを保護するための保護膜を設ける場合、別途の工程として作成することが必要になる。また、例示の内部接続用電極構造体を製造するための電鋳法は非常に優れた方法ではあるものの、電鋳法自体にはノウハウが多く、現状では製造業者が限られているという問題がある。
本発明は、係る問題点を解決して、半導体装置パッケージのおもて面に形成した配線パターンを保護するための保護膜を、簡潔に、しかもコスト的にも安く製造し、供給することを目的としている。 The present invention solves such problems, and manufactures and supplies a protective film for protecting a wiring pattern formed on the front surface of a semiconductor device package in a simple and inexpensive manner. It is aimed.
また、本発明は、半導体装置パッケージに用いる内部接続用電極構造体を、電鋳法を用いることなく従来より用いられている通常の製造技術を用いて容易に作成可能にすることを目的としている。 Another object of the present invention is to make it possible to easily produce an internal connection electrode structure used for a semiconductor device package by using a normal manufacturing technique conventionally used without using an electroforming method. .
本発明の半導体装置パッケージ構造及びその製造方法は、半導体基板上の配線層に接続される回路素子を、半導体基板上に配置して樹脂封止すると共に、該配線層を介して該回路素子に接続される外部接続用電極をおもて面に配置する。支持板と該支持板に貼り付けたテープからなる２層構成の支持部に配線パターン及び該配線パターンに接続された内部接続用電極を複数個一体に結合した内部接続用電極構造体を構成する。該内部接続用電極構造体の内部接続用電極を、前記半導体基板上の配線層に接続して、該半導体基板上面を前記支持部のテープ下面まで樹脂封止する。前記支持部の支持板を剥離することにより露出したテープを、保護膜として用い、かつ、この保護膜に穴を空け、開口により露出した配線パターンと接続される外部接続用電極を形成する。 According to the semiconductor device package structure and the manufacturing method thereof of the present invention, a circuit element connected to a wiring layer on a semiconductor substrate is placed on the semiconductor substrate and sealed with resin, and the circuit element is connected to the circuit element via the wiring layer. An external connection electrode to be connected is arranged on the front surface. An internal connection electrode structure in which a wiring pattern and a plurality of internal connection electrodes connected to the wiring pattern are integrally coupled to a support portion having a two-layer structure composed of a support plate and a tape attached to the support plate is formed. . The internal connection electrode of the internal connection electrode structure is connected to the wiring layer on the semiconductor substrate, and the upper surface of the semiconductor substrate is resin-sealed to the lower surface of the tape of the support portion. A tape exposed by peeling off the support plate of the support portion is used as a protective film, and a hole is formed in the protective film to form an external connection electrode connected to the wiring pattern exposed by the opening.
半導体基板は多層有機基板であり、この多層有機基板を貫通するスルーホール内部の導体層を介して前記配線層に接続される裏面外部接続用電極を多層有機基板の裏面に形成することができる。支持板は、板状のシリコン基板、ガラス、又はステンレス板であり、テープは、薄膜フィルムの絶縁基材である。この絶縁基材テープは、所定の温度で剥離し易い材料、又は紫外線照射で剥離し易い材料の接着剤を用いて、前記支持板に貼り付けられる。 The semiconductor substrate is a multilayer organic substrate, and a back surface external connection electrode connected to the wiring layer via a conductor layer inside a through hole penetrating the multilayer organic substrate can be formed on the back surface of the multilayer organic substrate. The support plate is a plate-like silicon substrate, glass, or stainless steel plate, and the tape is an insulating base material for the thin film. The insulating base tape is affixed to the support plate using an adhesive that is easily peelable at a predetermined temperature or is easily peelable by ultraviolet irradiation.
支持部のテープ上に形成される配線パターンは、テープ上の全面に配線パターンとなるべき低抵抗の金属膜を蒸着あるいは貼り付け、或いはテープと薄い金属膜を一体化したものを用いて、リソグラフィにより形成される。或いは、支持部のテープ上に形成される配線パターンは、ナノ金属粒子を用いてインクジェット方式又はスクリーン印刷方式により、直接パターンニングして形成される。配線パターンに接続される内部接続用電極は、形成した配線パターンを含む全面に、内部接続用電極形成用のレジストを塗布し、開口した開口部にめっきを施して、充填した後に、レジストを除去することにより形成する。 The wiring pattern formed on the tape of the support portion is a lithography using a low resistance metal film to be a wiring pattern deposited or pasted on the entire surface of the tape, or an integrated tape and thin metal film. It is formed by. Alternatively, the wiring pattern formed on the tape of the support portion is formed by direct patterning using nano metal particles by an ink jet method or a screen printing method. For the internal connection electrode connected to the wiring pattern, apply the resist for forming the internal connection electrode on the entire surface including the formed wiring pattern, apply plating to the opening, and fill the opening, then remove the resist. To form.
本発明によれば、半導体装置パッケージのおもて面に形成した配線パターンを保護するための保護膜を、簡潔に、しかもコスト的にも安く製造し、供給することができる。また、半導体装置パッケージに用いる内部接続用電極構造体を、電鋳法を用いることなく、従来より用いられている通常の製造技術を用いて容易に作成することができる。 According to the present invention, a protective film for protecting a wiring pattern formed on the front surface of a semiconductor device package can be manufactured and supplied simply and at a low cost. In addition, the internal connection electrode structure used for the semiconductor device package can be easily formed by using a conventional manufacturing technique that has been used conventionally without using an electroforming method.
以下、例示に基づき、本発明の半導体装置パッケージ構造及びその製造方法を、順を追って説明する。図１は、本発明の半導体装置パッケージに用いることのできる内部接続用電極構造体を例示する斜視図である（その断面図は、図５に示す）。図１に例示の内部接続用電極構造体は、支持板とテープからなる２層構成の支持部に複数の配線付内部接続用電極を一体に備えたものである。図１は、１個の単体パターンを例示するが、実際の製造においては、多数個一体に連結された状態で作成され、個々のチップに切断して切り分ける個片化を経た後に、最終製品として完成する。 Hereinafter, based on an example, the semiconductor device package structure of the present invention and the manufacturing method thereof will be described in order. FIG. 1 is a perspective view illustrating an internal connection electrode structure that can be used in the semiconductor device package of the present invention (a cross-sectional view thereof is shown in FIG. 5). The internal connection electrode structure illustrated in FIG. 1 includes a plurality of internal connection electrodes with wirings integrally provided on a two-layered support portion composed of a support plate and a tape. FIG. 1 exemplifies a single unit pattern, but in actual manufacturing, it is created in a state where a large number of units are integrally connected, and after being cut into individual chips and cut into individual pieces, as a final product, Complete.
次に、このような内部接続用電極構造体の製造について、図２〜図５を参照して、順次説明する。まず、図２に示すように、支持板の上にテープを貼り付ける（以下、テープと支持板の２層構成を支持部と言う）。支持板としては、板状のシリコン基板とかガラスのような絶縁体或いは導電体のいずれも用いることができるが、例えば、ステンレス板を用いることにより、半導体装置の製造中に、より強い剛性を得ることができる。貼り付けるテープとしては、ポリイミドテープなどに代表される薄膜フィルムの絶縁基材が望ましい。このように、支持部は、絶縁基材テープと、この裏側（配線パターン形成面の反対側）に貼り付けた支持板（補強板）との２層構成となる。この支持板は、後の樹脂封止工程後に、剥離して除去する。 Next, manufacture of such an internal connection electrode structure will be sequentially described with reference to FIGS. First, as shown in FIG. 2, a tape is affixed on a support plate (hereinafter, a two-layer configuration of the tape and the support plate is referred to as a support portion). As the support plate, either a plate-like silicon substrate, an insulator such as glass, or a conductor can be used. For example, by using a stainless plate, stronger rigidity is obtained during the manufacture of a semiconductor device. be able to. As the tape to be attached, an insulating base material of a thin film represented by a polyimide tape or the like is desirable. In this way, the support portion has a two-layer configuration of the insulating base tape and the support plate (reinforcement plate) attached to the back side (opposite side of the wiring pattern forming surface). The support plate is peeled off and removed after the subsequent resin sealing step.
絶縁基材テープは、完成製品（半導体装置パッケージ）において配線パターンを覆う保護膜として機能する。このテープには、リフロー温度より高温（モールド温度以上）を加えると、支持板から剥離し易い処理を予め行っておく。このため、絶縁基材テープを貼り付ける接着剤は、所定の温度（例えば、高熱）で剥離し易い材料か、紫外線照射で剥離し易い材料を用いる。例えば、熱カプセル入り接着剤又は熱可塑性の接着剤、若しくは、光を透過する材料（耐熱低熱膨張ガラスなど）の支持板と、紫外線剥離型接着剤を用いる。 The insulating base tape functions as a protective film that covers the wiring pattern in the finished product (semiconductor device package). When a temperature higher than the reflow temperature (more than the mold temperature) is applied to the tape, a treatment that easily peels from the support plate is performed in advance. For this reason, the adhesive which affixes an insulating base tape uses the material which is easy to peel at predetermined | prescribed temperature (for example, high heat), or the material which is easy to peel by ultraviolet irradiation. For example, a heat-capsuled adhesive or a thermoplastic adhesive, or a support plate made of a material that transmits light (such as heat-resistant low-thermal expansion glass) and an ultraviolet peeling adhesive are used.
次に、図３に示すように、テープ上に配線パターンを形成する。このため、テープ上の全面に、配線パターンとなるべき低抵抗の金属膜を蒸着あるいは貼り付け、メタル付きテープを形成する。この金属膜としては、例えば、銅メッキを可能とする金、銀、銅、パラジューム箔を用いることができる。この金属層の上にレジストを塗布し、パターンを露光、現像してさらにエッチングを行い、レジストを除去して、配線パターンを完成させる。この金属層の上に、さらにメッキにより配線層を成長させても良い。または、金属膜を蒸着あるいは貼り付けることに代えて、テープと薄い金属膜（例えば銅箔）を一体化したものを用いても良い。この場合も、配線パターンは、リソグラフィで形成する。或いは、配線パターンは、ナノ金属粒子を用いてインクジェット方式とかスクリーン印刷方式により、直接パターンニングしてリソグラフィ工程を省略することもできる。ここで、インクジェット方式は、有機溶媒中にナノ金属粒子が含有されており、それをプリンターで実用されているインクジェット法で所望のパターンを描く方法である。また、スクリーン印刷方式の場合は、有機溶媒中にナノ金属粒子を含有させたナノペーストを、基板上にスクリーン印刷法で塗布する。 Next, as shown in FIG. 3, a wiring pattern is formed on the tape. For this reason, a low-resistance metal film to be a wiring pattern is deposited or pasted on the entire surface of the tape to form a metal-attached tape. As this metal film, for example, gold, silver, copper, or palladium foil that enables copper plating can be used. A resist is applied on the metal layer, the pattern is exposed and developed, and further etched, and the resist is removed to complete a wiring pattern. A wiring layer may be further grown on this metal layer by plating. Alternatively, instead of depositing or attaching a metal film, a tape and a thin metal film (for example, copper foil) integrated may be used. Also in this case, the wiring pattern is formed by lithography. Alternatively, the wiring pattern can be directly patterned using nano metal particles by an ink jet method or a screen printing method, and the lithography process can be omitted. Here, the ink jet method is a method in which nano metal particles are contained in an organic solvent, and a desired pattern is drawn by an ink jet method which is practically used in a printer. In the case of the screen printing method, a nano paste containing nano metal particles in an organic solvent is applied on a substrate by a screen printing method.
次に、図４に示すように、形成した配線パターンを含む全面に、内部接続用電極形成用のレジストを塗布し、現像で開口する。 Next, as shown in FIG. 4, a resist for forming an internal connection electrode is applied to the entire surface including the formed wiring pattern, and an opening is formed by development.
図５は、完成した内部接続用電極構造体を示す断面図である。図５に示すように、レジスト開口部にめっきを施して、充填した後に、レジストを除去する。これによって、支持板とテープからなる２層構成の支持部の上に、配線パターン及びそれに接続された内部接続用電極が形成される。 FIG. 5 is a cross-sectional view showing the completed internal connection electrode structure. As shown in FIG. 5, after the resist opening is plated and filled, the resist is removed. As a result, the wiring pattern and the internal connection electrodes connected to the wiring pattern are formed on the support portion having a two-layer structure including the support plate and the tape.
図６は、半導体基板としての多層有機基板上に、電子部品として半導体LSIチップを接着し、かつ接続した状態で示す図である。半導体LSIチップは、多層有機基板上にダイボンド材により接着して、有機基板の最上層の配線層とはボンディングワイヤにより接続するものとして例示している。多層または単層有機基板の最上層の配線層に、ボンディングワイヤ接続電極となるボンディング用金属パッド部が形成されると共に、該パッド部への配線が形成される。この多層または単層有機基板のおもて面の金属パッド部と、半導体チップは、Ａｕボンディングワイヤにより接続される。或いは、半導体チップは、有機基板に対してフリップチップボンド接続することもできる（図示省略）。この場合、半導体チップは、多層または単層有機基板の最上層の配線層に、通常の技術を用いて、フリップチップボンド接続される。 FIG. 6 is a view showing a state in which a semiconductor LSI chip as an electronic component is bonded and connected on a multilayer organic substrate as a semiconductor substrate. The semiconductor LSI chip is illustrated as being bonded to a multilayer organic substrate with a die bond material and connected to the uppermost wiring layer of the organic substrate with a bonding wire. In the uppermost wiring layer of the multi-layer or single-layer organic substrate, a bonding metal pad portion serving as a bonding wire connection electrode is formed, and wiring to the pad portion is formed. The metal pad portion on the front surface of the multilayer or single layer organic substrate and the semiconductor chip are connected by an Au bonding wire. Alternatively, the semiconductor chip can be flip-chip bonded to the organic substrate (not shown). In this case, the semiconductor chip is flip-chip bonded to the uppermost wiring layer of the multilayer or single-layer organic substrate using a normal technique.
多層有機基板は、単層２層配線構造や複数層から成る基板の各層に、それぞれ配線層を形成した後、これらの基板を貼り合わせ、必要に応じて各層の配線層を接続するためのスルーホールを形成したものである。このスルーホールの内部には導体層が形成され、この導体層が裏面側に形成された端面電極部であるランドと接続されている。このような多層または単層有機基板は、例えば、「ハンダボール」と呼ばれる小さいハンダ材料を丸めたもの（バンプ）を裏面に実装した（BGA：Ball Grid Array）一括封止有機基板として知られている。 A multilayer organic substrate is a through-layer for forming a wiring layer on each layer of a single-layer two-layer wiring structure or a substrate composed of a plurality of layers, and then bonding these substrates and connecting the wiring layers of each layer as necessary. A hole is formed. A conductor layer is formed inside the through hole, and the conductor layer is connected to a land which is an end face electrode portion formed on the back surface side. Such a multi-layer or single-layer organic substrate is known as, for example, a packaged organic substrate (BGA: Ball Grid Array) in which a small solder material called “solder ball” (bump) is mounted on the back surface (BGA: Ball Grid Array). Yes.
図７は、上述の内部接続用電極構造体（図１又は図５参照）を、半導体LSIチップを装着した半導体基板（図６参照）上に配置した状態で示す図である。なお、図示したように、半導体基板側を裏面として、その上に配置される内部接続用電極構造体側をおもて面と称する。有機基板おもて面に形成した配線層の所定の位置には、内部接続用電極が固定され、かつ電気的に接続される。内部接続用電極を固定及び接続する手法としては、（１）超音波による接合、（２）銀ペースト等の導電性ペーストによる接続、（３）半田接続、（４）有機基板側に設けた接続電極用金属パッド部に凹部を設ける一方、内部接続用電極構造体側は凸部を設けて挿入圧着あるいは挿入してカシメる方法、により行うことができる。 FIG. 7 is a view showing the above-described internal connection electrode structure (see FIG. 1 or FIG. 5) arranged on a semiconductor substrate (see FIG. 6) on which a semiconductor LSI chip is mounted. As shown in the figure, the semiconductor substrate side is referred to as the back surface, and the internal connection electrode structure side disposed thereon is referred to as the front surface. An internal connection electrode is fixed and electrically connected to a predetermined position of the wiring layer formed on the front surface of the organic substrate. The methods for fixing and connecting the internal connection electrodes include (1) ultrasonic bonding, (2) connection using a conductive paste such as silver paste, (3) solder connection, and (4) connection provided on the organic substrate side. While a concave portion is provided in the electrode metal pad portion, the internal connection electrode structure side can be formed by a method of providing a convex portion and inserting / crimping or inserting and crimping.
図８は、樹脂封止した状態で示す図である。一体に連結されている内部接続用電極が固定された後、この状態で、多層有機基板の上面は、支持部のテープ下面までトランスファーモールドされ、或いは液状樹脂（材質は、例えばエポキシ系）を用いて樹脂封止される。 FIG. 8 is a diagram showing the resin-sealed state. After the internal connection electrodes connected together are fixed, in this state, the upper surface of the multilayer organic substrate is transfer-molded up to the lower surface of the tape of the support part, or a liquid resin (the material is, for example, epoxy) is used. And sealed with resin.
図９は、支持板を剥離した後の状態で示す図である。例えば、所定の高温を加えることにより、支持板を剥離する。これにより図９の上側に露出した絶縁基材テープは、完成製品の保護膜として機能する。 FIG. 9 is a diagram showing the state after the support plate is peeled off. For example, the support plate is peeled off by applying a predetermined high temperature. Thus, the insulating base tape exposed on the upper side of FIG. 9 functions as a protective film for the finished product.
図１０は、完成した半導体装置パッケージを示す断面図である。図１０に示すように、おもて面側においては、絶縁基材テープに穴を空け、開口により露出した配線パターンと接続される外部接続用電極（バンプ電極）を形成する。この配線パターンにより、内部接続用電極先端とは異なる位置に外部接続用電極を設けることができる。裏面側においては、多層有機基板の裏面に形成されているランド（図６参照）と接続される外部接続用電極（バンプ電極）が形成される。 FIG. 10 is a cross-sectional view showing a completed semiconductor device package. As shown in FIG. 10, on the front surface side, holes are formed in the insulating base tape, and external connection electrodes (bump electrodes) connected to the wiring patterns exposed through the openings are formed. With this wiring pattern, the external connection electrode can be provided at a position different from the tip of the internal connection electrode. On the back side, external connection electrodes (bump electrodes) connected to lands (see FIG. 6) formed on the back side of the multilayer organic substrate are formed.
このように、本発明は、例示の内部接続用電極構造体を用いることにより、おもて面側に容易に保護膜により保護された配線パターン、及びこの配線パターンに接続された外部接続用電極を形成することが可能になる。さらに、図示のように、半導体基板として、多層有機基板を用いた際には、裏面側においても容易に外部接続用電極を形成することができるが、本発明は、必ずしも、多層有機基板を用いる必要はなく、半導体基板として、上面に配線層を形成したシリコン基板や、或いは、特許文献２に開示のようなリードフレームを用いることも可能である。 Thus, according to the present invention, by using the example internal connection electrode structure, the wiring pattern easily protected by the protective film on the front surface side, and the external connection electrode connected to the wiring pattern Can be formed. Furthermore, as shown in the figure, when a multilayer organic substrate is used as the semiconductor substrate, the external connection electrode can be easily formed on the back side, but the present invention does not necessarily use the multilayer organic substrate. It is not necessary, and a silicon substrate having a wiring layer formed on the upper surface or a lead frame as disclosed in Patent Document 2 can be used as the semiconductor substrate.
Claims (9)
支持板と該支持板に貼り付けたテープからなる２層構成の支持部に配線パターン及び該配線パターンに接続された内部接続用電極を複数個一体に結合した内部接続用電極構造体を備え、
該内部接続用電極構造体の内部接続用電極を、前記半導体基板上の配線層に接続して、該半導体基板上面を前記支持部のテープ下面まで樹脂封止し、
前記支持部の支持板を剥離することにより露出したテープを、保護膜として用い、かつ、この保護膜に穴を空け、開口により露出した配線パターンと接続される外部接続用電極を形成した半導体装置パッケージ構造。 A circuit element connected to the wiring layer on the semiconductor substrate is placed on the semiconductor substrate and sealed with resin, and an external connection electrode connected to the circuit element via the wiring layer is provided on the front surface. In the arranged semiconductor device package structure,
An internal connection electrode structure in which a wiring pattern and a plurality of internal connection electrodes connected to the wiring pattern are integrally coupled to a support portion having a two-layer structure composed of a support plate and a tape attached to the support plate;
The internal connection electrode of the internal connection electrode structure is connected to the wiring layer on the semiconductor substrate, and the semiconductor substrate upper surface is resin-sealed to the tape lower surface of the support portion,
A semiconductor device using a tape exposed by peeling the support plate of the support portion as a protective film, and forming a hole in the protective film and forming an external connection electrode connected to the wiring pattern exposed by the opening Package structure.
支持板と該支持板に貼り付けたテープからなる２層構成の支持部に配線パターン及び該配線パターンに接続された内部接続用電極を複数個一体に結合した内部接続用電極構造体を備え、
該内部接続用電極構造体の内部接続用電極を、前記半導体基板上の配線層に接続して、該半導体基板上面を前記支持部のテープ下面まで樹脂封止した後、前記支持部の支持板を剥離し、
支持板の剥離により露出したテープを、保護膜として用い、かつ、この保護膜に穴を空け、開口により露出した配線パターンと接続される外部接続用電極を形成した半導体装置パッケージ構造の製造方法。 A circuit element connected to the wiring layer on the semiconductor substrate is placed on the semiconductor substrate and sealed with resin, and an external connection electrode connected to the circuit element via the wiring layer is provided on the front surface. In the manufacturing method of the arranged semiconductor device package structure,
An internal connection electrode structure in which a wiring pattern and a plurality of internal connection electrodes connected to the wiring pattern are integrally coupled to a support portion having a two-layer structure composed of a support plate and a tape attached to the support plate;
The internal connection electrode of the internal connection electrode structure is connected to the wiring layer on the semiconductor substrate, the upper surface of the semiconductor substrate is resin-sealed to the lower surface of the tape of the support portion, and then the support plate of the support portion Peel off
A method of manufacturing a semiconductor device package structure in which a tape exposed by peeling of a support plate is used as a protective film, and a hole is formed in the protective film, and an external connection electrode connected to a wiring pattern exposed by the opening is formed.
The internal connection electrode connected to the wiring pattern is coated with a resist for forming the internal connection electrode on the entire surface including the formed wiring pattern, plated on the opening, and filled. 9. The method of manufacturing a semiconductor device package structure according to claim 7, wherein the semiconductor device package structure is formed by removing the semiconductor device package structure.
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