WO2023019684A1

WO2023019684A1 - Packaging mechanism and preparation method therefor

Info

Publication number: WO2023019684A1
Application number: PCT/CN2021/119973
Authority: WO
Inventors: 朱凯; 谷新; 缪桦
Original assignee: 深南电路股份有限公司
Priority date: 2021-08-16
Filing date: 2021-09-23
Publication date: 2023-02-23
Also published as: CN115706017A; TW202310092A; JP2023541730A; TWI790880B

Abstract

The present application discloses a packaging mechanism and a preparation method therefor. The preparation method for the packaging mechanism comprises: obtaining a separable support layer; performing electroplating on a first preset position of the separable support layer to form a conductive circuit at the first preset position; preparing a first solder mask layer on the side of the conductive circuit away from the separable support layer, and exposing part of the conductive circuit; electrically connecting a chip to the exposed part of the conductive circuit, and performing plastic packaging on the chip to form an insulating layer; and removing the separable support layer, and preparing a second solder mask layer at a second preset position on the side of the conductive circuit away from the first solder mask layer. By means of the method, the preparation method for the packaging mechanism of the present application can reduce the preparation steps and volume of the packaging mechanism, and improve the preparation efficiency of the packaging mechanism.

Description

A kind of encapsulation mechanism and preparation method thereof

【Technical field】

The present application relates to the technical field of packaging mechanisms, in particular to a packaging mechanism and a preparation method thereof.

【Background technique】

Packaging is an important link in the semiconductor manufacturing process. By making a packaging mechanism around the bare chip, it provides electrical interconnection, mechanical support, heat dissipation and environmental protection for the bare chip, which is one of the preconditions for the realization of electrical functions of integrated circuit components. Generally speaking, bare chip packaging is inseparable from the packaging substrate. The packaging substrate is the carrier of the bare chip, and the plastic packaging layer packages the bare chip on the packaging substrate to form the entire packaging mechanism.

In the packaging mechanism manufacturing technology, with the rapid development of science and technology, all walks of life have higher and higher requirements for packaging mechanisms. Among them, due to the continuous increase of high-density packaging and multiple devices, the preparation process of the packaging mechanism is getting longer and longer, the packaging mechanism is becoming more and more complex, and the preparation process and requirements of the packaging mechanism are higher, resulting in the traditional packaging mechanism containing independent packaging substrates. The production efficiency is low.

【Content of invention】

The present application provides a method for preparing a packaging mechanism, so as to simplify the preparation of the packaging mechanism, reduce the volume of the packaging mechanism, and improve the preparation efficiency.

In order to solve the above technical problems, the present application proposes a method for preparing a packaging mechanism, including: obtaining a detachable support layer; electroplating the first preset position of the detachable support layer to form a Conductive circuit; prepare the first solder resist layer on the side of the conductive circuit away from the detachable support layer, and expose part of the conductive circuit; electrically connect the chip to the exposed part of the conductive circuit, and plastic-encapsulate the chip to form an insulating layer; remove The support layer can be separated, and a second solder resist layer is prepared at a second preset position on the side of the conductive circuit away from the first solder resist layer.

Wherein, the detachable support layer includes a peelable copper layer and a carrier layer that are laminated and bonded; electroplating the first preset position of the detachable support layer to form a conductive circuit at the first preset position includes: Electroplating is performed on the first preset position of the peelable copper layer of the detachable support layer to form a conductive circuit at the first preset position; the step of removing the detachable support layer includes: removing the carrier layer; and removing the detachable copper layer by etching Strip the copper layer to expose the side of the conductive trace away from the first solder mask layer.

Wherein, electroplating the first preset position of the detachable support layer to form the conductive circuit at the first preset position comprises: preparing a photosensitive resist layer on the side of the peelable copper layer away from the carrier layer; The side of the strippable copper layer provided with the photosensitive resist layer is subjected to exposure and development treatment to prepare a groove pattern at the first preset position; pattern electroplating is performed on the groove pattern at the first preset position to obtain the groove pattern at the first preset position. forming conductive lines at preset positions; removing the photosensitive resist layer.

Wherein, the step of preparing the first solder resist layer on the side of the conductive circuit far away from the detachable support layer, and exposing part of the conductive circuit includes: preparing the entire board of the solder resist film to the The conductive circuit is away from the side of the detachable support layer; the solder resist film is subjected to window treatment to form the first solder resist layer.

Wherein, after the step of exposing part of the conductive circuit, it further includes: making a surface treatment layer on the exposed part of the conductive circuit.

Wherein, the step of electrically connecting the chip with the exposed part of the conductive circuit, and plastic packaging the chip to form an insulating layer includes: welding the pad bump on the chip with the exposed part of the conductive circuit by reflow soldering; The chip is plastic-encapsulated to form an insulating layer around the chip.

Wherein, the step of removing the separable support layer and preparing the second solder resist layer at the second preset position where the conductive circuit is far away from the first solder resist layer includes: removing the separable support layer so that the exposed conductive circuit is far away from the first solder resist layer One side of the solder mask; prepare the entire board of the solder mask to the side of the conductive line away from the first solder mask layer by attaching, dipping, spraying or spin coating; for the solder mask except the second preset position The position is windowed to form a second solder resist layer.

Wherein, after the step of removing the detachable support layer, before the step of preparing the second solder resist layer at the second preset position on the side of the conductive circuit far away from the first solder resist layer, it includes: Prepare at least one underlying circuit layer on one side of the solder resist layer; the step of preparing a second solder resist layer at a second preset position on the side of the conductive circuit away from the first solder resist layer includes: at least one underlying circuit layer away from A second solder resist layer is prepared on a second predetermined position on one side of the first solder resist layer.

Wherein, the preparation method of the packaging mechanism further includes: preparing at least one top layer circuit layer on the side of the insulating layer away from the conductive circuit by a build-up method; preparing a third solder resist layer on the side of at least one top layer circuit layer away from the insulating layer .

In order to solve the above-mentioned technical problems, the present application proposes a packaging mechanism, which is prepared by any one of the above-mentioned packaging mechanism manufacturing methods.

The beneficial effects of this application are: different from the situation of the prior art, this application uses a detachable support layer as a temporary carrier for preparing conductive lines, and after preparing conductive lines with arbitrary line widths on it, it is covered by the first solder resist layer Part of the conductive circuit, and after the exposed part of the conductive circuit is connected to the chip, the plastic chip is wrapped with an insulating layer, and then the conductive circuit is connected to the other side of the conductive circuit except the side of the detachable support layer by using the first solder resist layer and the insulating layer. It can be protected to reduce the possible impact on the conductive circuit when the detachable support layer is removed, thereby improving the fineness and reliability of the conductive circuit, and further improving the quality and reliability of the packaging mechanism. And this application directly wraps the conductive circuit through the first solder resist layer, and then performs plastic sealing of the insulating layer, eliminating the need for a dielectric layer, and then synchronously completes the plastic packaging of the chip and the interconnection circuit production of the packaging mechanism, reducing the production steps of the packaging mechanism, The preparation efficiency of the packaging mechanism is improved, and the insulating layer replaces the dielectric layer so that the thickness of the final finished packaging mechanism is thinner, the packaging volume is smaller, the structure is lighter, and the dielectric transmission loss is also smaller. On this basis, the packaging mechanism containing the chip can be further used as a core board to process laminated circuits on both sides, so as to obtain a finished packaging mechanism with higher wiring density.

【Description of drawings】

Fig. 1 is a schematic flow chart of an embodiment of the preparation method of the packaging mechanism provided by the present application;

Fig. 2 is a schematic flow chart of another embodiment of the method for preparing a packaging mechanism provided by the present application;

Fig. 3a is a schematic structural diagram of an embodiment of the detachable support layer obtained in step S21;

Fig. 3b is a schematic structural diagram of an embodiment after the formation of conductive lines in step S22;

Fig. 3c is a schematic structural diagram of an embodiment after windowing the solder mask in step S23;

Fig. 3d is a schematic structural view of an embodiment after plastic sealing in step S24;

Fig. 4 is a schematic structural view of an embodiment of the packaging mechanism of the present application;

Fig. 5 is a schematic structural diagram of another embodiment of the packaging mechanism of the present application;

Fig. 6 is a schematic structural diagram of another embodiment of the packaging mechanism of the present application.

【Detailed ways】

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Please refer to FIG. 1 further. FIG. 1 is a schematic flowchart of an embodiment of a method for manufacturing a packaging mechanism provided in the present application.

Step S11: Obtain a detachable support layer.

A detachable support layer is obtained. In this embodiment, the detachable support layer may include a detachable support layer prepared from a support material that has good thermal stability, high flatness, high mechanical strength, and is not brittle.

The detachable support layer can realize its detachable property by using a release material, a peelable copper foil or an adhesive material.

Step S12: performing electroplating on a first preset position of the detachable support layer, so as to form a conductive circuit at the first preset position.

Electroplating is performed on the first preset position of the detachable support layer to form the required conductive circuit at the first preset position. Wherein, the first preset position is the position where the conductive line needs to be prepared, and the specific line type can be set based on the actual situation.

In a specific application scenario, electroless copper plating can be performed on the first preset position of the detachable support layer, and then electroplating is performed at the first preset position after electroless copper plating, so that at the first preset position Form conductive lines. In another specific application scenario, a groove pattern can be prepared on the first preset position of the detachable support layer by means of exposure and development, and then electroplating is performed based on the groove pattern, thereby forming a Conductive lines. In another specific application scenario, it is also possible to paste a resist film on a position other than the first preset position of the detachable support layer, and then adjust the entire position of the first preset position on the detachable support layer. The sides are electroplated, thereby forming conductive lines and the like at a first predetermined position. This embodiment does not limit the way of forming the conductive circuit.

Wherein, since this step is to directly perform electroplating on the detachable support layer, and use the detachable support layer as a strong support to obtain a conductive circuit, the conductive circuit in this step can obtain a conductive circuit with any line width based on the preparation requirements.

Step S13: preparing a first solder resist layer on the side of the conductive circuit away from the detachable support layer, and exposing part of the conductive circuit.

A first solder resist layer is prepared on the side of the conductive circuit away from the detachable support layer, and part of the conductive circuit is exposed.

In a specific application scenario, the first solder resist layer can be covered on the side of the conductive circuit away from the detachable support layer, and then windows are opened at the corresponding positions of some conductive circuits that need to be exposed, thereby exposing part of the conductive circuit , and retain part of the first solder resist layer to cover the remaining conductive lines.

In another specific application scenario, windows can be opened on the first solder resist layer corresponding to some of the conductive lines that need to be exposed, and then pasted to the side of the conductive lines away from the detachable support layer, Therefore, a part of the conductive circuit is exposed, and the remaining conductive circuit is covered by the first solder resist layer.

Step S14: electrically connecting the chip to the exposed part of the conductive circuit, and plastic-encapsulating the chip to form an insulating layer.

In this embodiment, the exposed part of the conductive circuit needs to be electrically connected to the chip, so as to connect the chip with the conductive circuit.

After the chip is electrically connected to the exposed part of the conductive circuit, the chip is plastic-sealed to form an insulating layer, and the chip is wrapped and plastic-sealed through the insulating layer.

Among them, the plastic sealing in this step can be completed by making the chip plastic packaging and the interconnection circuit of the packaging mechanism together, which shortens the production chain of the packaging mechanism and improves the preparation efficiency of the packaging mechanism. Among them, the manufacturing packaging and chip packaging of the traditional packaging mechanism are two links in the production chain. Therefore, the packaging mechanism needs to have a certain mechanical support capacity when facing transportation and chip packaging. Therefore, it must have a certain thickness. Traditional And other packaging mechanisms ensure their supporting capacity through the dielectric layer, but the thickness of the packaging mechanism increases, and the preparation process increases. However, in this embodiment, the plastic packaging of the chip and the interconnection circuit of the packaging mechanism are completed together, which avoids the need for supporting capacity in the preparation process of the packaging mechanism, reduces the thickness of the board, simplifies the preparation process, and improves the preparation efficiency.

Step S15: removing the detachable support layer, and preparing a second solder resist layer at a second preset position on the side of the conductive circuit away from the first solder resist layer.

After wrapping the chip through the insulating layer and performing plastic sealing, the detachable support layer is removed, and the second preset position is prepared on the side of the conductive line away from the first solder resist layer, that is, the side where the detachable support layer is originally located. Two solder mask layers.

Wherein, when removing the detachable support layer, a corresponding removal method may be adopted based on the type of the detachable support layer. In a specific application scenario, when the detachable support layer is a peelable copper foil, the peelable copper foil can be removed by etching. Since the conductive circuit at this time is covered by the first solder resist layer and the insulating layer except the side in contact with the peelable copper foil, therefore, when the peelable copper foil is etched, the side of the conductive circuit will not be corroded by the etching solution , the line width of the conductive line will not be affected. Therefore, the conductive lines in the packaging mechanism of this embodiment can be of any line width, including ultra-fine lines.

In another specific application scenario, when the detachable support layer is an adhesive support layer, the adhesive support layer can be removed by tearing off. Since the other surfaces of the conductive circuit except the side in contact with the adhesive support layer are wrapped by the first solder resist layer and the insulating layer, when the adhesive support layer is torn off, the side of the conductive circuit will not be torn. , the line width of the conductive line will not be affected. Therefore, the conductive lines in the packaging mechanism of this embodiment can be of any line width, including ultra-fine lines.

In a specific application scenario, the second solder resist layer can be covered on the side of the conductive circuit far away from the first solder resist layer, and then windows are opened in all positions except the second preset position, thereby exposing part of the conductive circuit , and cover the conductive line at the second preset position through the second solder resist layer.

In another specific application scenario, windows can be opened on the second solder resist layer corresponding to all positions except the second preset position, and then pasted so that the conductive lines are far away from the first solder resist layer One side of the circuit, thereby exposing part of the conductive circuit, and covering the conductive circuit at the second preset position through the second solder resist layer.

Wherein, all positions except the second preset position on the side of the conductive line away from the first solder resist layer can be used for ball planting or soldering, by exposing all positions except the second preset position The conductive traces electrically connect the printed circuit board motherboard, other components, or other devices, thereby electrically connecting the packaging mechanism to the other devices.

A second solder resist layer is prepared at a second predetermined position on a side of the conductive circuit away from the first solder resist layer, so as to obtain a final packaging mechanism. Wherein, the packaging mechanism in this embodiment may include a fan-out packaging mechanism or other packaging mechanisms.

Through the above method, the preparation method of the packaging mechanism in this embodiment uses the detachable support layer as a temporary carrier for preparing conductive lines, and after preparing conductive lines with arbitrary line widths on it, cover a part of the conductive lines with the first solder resist layer , and after the exposed part of the conductive circuit is connected to the chip, the insulating layer is used to wrap the plastic packaged chip, and then the first solder resist layer and the insulating layer are used to protect the other side of the conductive circuit except the side contacting the detachable support layer, so that The possible impact on the conductive circuit is reduced when the detachable support layer is removed, thereby improving the fineness and reliability of the conductive circuit, and further improving the quality and reliability of the packaging mechanism. And this embodiment directly wraps the conductive circuit through the first solder resist layer, and then performs plastic sealing of the insulating layer, and then completes the plastic packaging of the chip and the interconnection circuit production of the packaging mechanism simultaneously, which reduces the production steps of the packaging mechanism and improves the efficiency of the packaging mechanism. Manufacturing efficiency, and replacing the dielectric layer with an insulating layer makes the thickness of the final product packaging mechanism thinner, the packaging volume is smaller, the structure is lighter, and the dielectric transmission loss is also smaller. On this basis, the packaging mechanism containing the chip can be further used as a core board to process laminated circuits on both sides, so as to obtain a finished packaging mechanism with higher wiring density.

Please refer to FIG. 2 further. FIG. 2 is a schematic flowchart of another embodiment of the manufacturing method of the packaging mechanism provided in the present application.

Step S21: Obtain a detachable support layer.

A detachable support layer is obtained. Wherein, the detachable support layer includes a peelable copper layer and a carrier layer that are stacked and attached together. The carrier layer also includes a copper foil layer and a dielectric layer. The carrier layer is used for strength support in the preparation of the packaging mechanism, the copper foil layer is used for the peelable copper layer for easy peeling, and the peelable copper layer is used as the seed layer for the preparation of the conductive circuit.

Wherein, the thickness range of the peelable copper layer is 1.0-3.0 microns, specifically 1.0 microns, 1.5 microns, 2.0 microns, 3.0 microns, etc., which can be set based on actual needs, and are not limited here. The thickness range of the carrier layer is 0.2-2.0 mm, specifically 0.2 mm, 0.5 mm, 0.8 mm, 1.0 mm, 1.6 mm, 1.9 mm, 2.0 mm, etc., which can also be set based on actual needs, and is not limited here .

In a specific application scenario, the two opposite sides of the strippable copper layer may be smooth to facilitate stripping.

When the peelable copper layer and the carrier layer are used as the detachable support layer to prepare the packaging mechanism, the production line of the packaging mechanism does not need to be rebuilt, and can be carried out in the conventional packaging mechanism manufacturing process, saving production resources.

Please refer to Fig. 3a, Fig. 3a is a schematic structural diagram of an embodiment of the detachable support layer obtained in step S21.

The detachable support layer 10 of this embodiment includes a peelable copper layer 11 and a carrier layer 12 that are laminated and attached. The carrier layer 12 may further include a copper foil layer (not shown in the figure) and a dielectric layer (not shown in the figure), so as to ensure the strength of the carrier layer 12 through the copper foil layer and reduce the impact of thermal expansion on the detachable support layer 10 , thereby improving the precision of the conductive lines prepared on the detachable support layer 10 .

Step S22: performing electroplating on a first predetermined position of the peelable copper layer of the detachable supporting layer, so as to form a conductive circuit at the first predetermined position.

After the detachable support layer is obtained, electroplating is performed on the first preset position of the peelable copper layer of the detachable support layer, so as to form a conductive circuit at the first preset position.

In a specific application scenario, the photosensitive resist layer can be prepared on the side of the strippable copper layer far away from the carrier layer, and then the side of the strippable copper layer provided with the photosensitive resist layer is sequentially exposed and developed. Groove pattern is prepared at the first preset position, and then pattern electroplating is performed on the groove pattern at the first preset position to form a conductive circuit at the first preset position, after the conductive circuit is prepared at the first preset position , remove the photoresist layer.

Wherein, the material type of the photosensitive resist layer in this embodiment may include photoresist type or photoinduced erosion type material, and the photosensitive resist layer may be coated by attaching a dry film, dipping, spraying or spin coating a wet film, etc. Prepared to the side of the strippable copper layer facing away from the carrier layer.

And when exposing and developing, this embodiment can adopt different mask schemes based on the material type of the photosensitive resist layer, and sequentially make groove patterns at the first preset position through exposure, photolithography, and development, and then make the groove pattern for the first preset position. Pattern electroplating is performed on the groove pattern at the predetermined position to form a conductive circuit at the first predetermined position.

Wherein, the line width of the conductive circuit in this embodiment can be any line width, including ultra-fine line width: 1-20 microns. The material of the conductive circuit includes one or more of copper, silver, gold, nickel, tin, palladium, cobalt, ruthenium, and molybdenum.

Please refer to FIG. 3 b , which is a schematic structural diagram of an embodiment after the conductive circuit is formed in step S22 .

In this step, a conductive circuit 13 is provided on a first predetermined position on a side of the peelable copper layer 11 away from the carrier layer 12 .

The conductive circuit 13 is attached to the side of the peelable copper layer 11 away from the carrier layer 12 .

Step S23: Prepare the entire board of the solder mask to the side of the conductive line away from the detachable support layer by means of attachment, dip coating, spray coating or spin coating, and perform window treatment on the solder mask to form the first solder mask layer .

After the conductive line is prepared on the side of the strippable copper layer, the solder resist film can be prepared to the side of the conductive line away from the detachable support layer by attaching, dipping, spraying or spin coating, and then the solder resist film Perform window treatment to expose part of the conductive lines and form the first solder resist layer. Wherein, the part of the conductive circuit exposed in this step is used for electrically connecting with the chip. In this embodiment, the exposed part of the conductive circuit can be used for subsequent chip mounting.

Wherein, before the window is opened on the solder resist film, the solder resist film covers the entire conductive circuit and fills up all gaps between the conductive circuit and the peelable copper layer of the detachable support layer. Then the solder resist film is subjected to window opening treatment to form at least one hole in the solder resist film to obtain the first solder resist layer, so as to expose part of the conductive circuit through the at least one hole. Wherein, the unexposed conductive lines are still covered and protected by the first solder resist layer.

The solder resist film in this embodiment may be any one of a solder resist dry film or a solder resist wet film, so that the first solder resist layers of different material types are prepared according to different solder resist films. The thickness of the first solder resist layer ranges from 5 to 50 microns, specifically 5 microns, 10 microns, 20 microns, 30 microns, 45 microns, 50 microns, etc., which can be set based on actual needs.

When windowing the solder mask, based on the material type of the solder mask, exposure and development, laser ablation or plasma erosion can be used to open the window of the solder mask to expose some conductive lines. . For example: when the first solder resist layer is prepared from a solder resist dry film, the solder resist film can be opened by laser ablation; when the first solder resist layer is prepared from a solder resist wet film, it can be Opening a window on the solder resist film by means of plasma erosion, which is not specifically limited here.

In a specific application scenario, when opening a window on the solder resist film, the window can be opened based on the size of the pad bump of the chip to be installed later, so that the size of at least one hole matches the size of the pad bump , so as to ensure that the pad bump can pass through the hole and be connected to the conductive line.

In a specific application scenario, by opening a window on the solder resist film to expose part of the conductive circuit, after obtaining the first solder resist layer, a surface treatment layer is made on the exposed part of the conductive circuit to improve the chip mounting quality . Specifically, the surface treatment layer in this embodiment includes one or more of silver layer, nickel layer, palladium layer, gold layer, tin layer, and organometallic compound layer, which can be selected based on chip type and mounting requirements.

Please refer to FIG. 3c. FIG. 3c is a schematic structural diagram of an embodiment after windowing the solder resist film in step S23.

The first solder resist layer 14 in this embodiment fills up all the gaps between the conductive lines 13 and the strippable copper layer 11 . At least one hole 141 is formed on the first solder resist layer 14 , and the conductive circuit 13 passes through the at least one hole 141 to expose part of the conductive circuit for subsequent electrical connection with other components.

Moreover, during the formation process of the first solder resist layer 14, the carrier layer 12 serves as a carrier to support its preparation.

Step S24: Solder the pad bumps on the chip with the exposed part of the conductive circuit by reflow soldering, and seal the chip with a plastic sealing material to form an insulating layer around the chip.

After the part of the conductive circuit is exposed, the pad bump on the chip can be soldered to the exposed part of the conductive circuit by means of reflow soldering, so as to realize the electrical connection between the chip and the conductive circuit. After the electrical connection, the chip is plastic-sealed with a plastic sealing material to form an insulating layer around the chip. Since the chip is electrically connected to the conductive circuit at this time, when the insulating layer is formed around the chip, the chip and the entire mechanism can be connected at the same time. Plastic. Wherein, the thickness of the insulating layer finally formed in this embodiment is greater than or equal to the height difference between the side of the chip away from the conductive circuit and the side of the first solder resist layer away from the conductive circuit, so as to package the entire chip in plastic.

In a specific application scenario, the placement between the chip and the conductive circuit can be completed by a placement machine first, and then the pad bumps of the chip are respectively welded through the holes on the first solder resist layer by reflow soldering on exposed conductive lines. After soldering, the pad bumps of the chip are buried in the first solder resist layer.

The chips in this embodiment include flip chips or other chips. The molding material in this embodiment may include epoxy molding compound or other insulating molding materials, and the molding material may be a liquid, powder, granular or sheet molding material. The molding method of this embodiment may include methods such as compression molding or vacuum lamination, which may be selected based on the type of molding material, which is not limited here.

Wherein, the material of the insulating layer in this embodiment may include organic resin and silica filler, and the weight ratio range of silica in the insulating layer is 1-95%, specifically 1%, 20%, 50%. , 62%, 75%, 80%, 90%, 95%, etc., which can be set based on actual conditions, and are not limited here.

In other embodiments, the soldering between the pad bumps of the chip and the conductive circuit can also be done by wave soldering, and the specific soldering method is not limited here.

Please refer to FIG. 3d. FIG. 3d is a schematic structural diagram of an embodiment after plastic sealing in step S24.

The chip 15 of this embodiment is provided with a plurality of pad bumps 151, wherein each pad bump 151 is electrically connected to the conductive circuit 13 through the hole on the first solder resist layer 14, and the surrounding of the chip 15 An insulating layer 16 is provided, and the insulating layer 16 wraps the chip 15 and fills the gaps among the chip 15 , the first solder resist layer 14 and the pad bumps 151 to complete the packaging and plastic sealing of the entire board.

Step S25: Remove the detachable support layer, and prepare the whole board of the solder resist film by attaching, dipping, spraying or spin coating on the side of the exposed conductive circuit away from the first solder resist layer until the conductive circuit is far away from the first solder resist layer. On one side of the soldering layer, window treatment is performed on positions other than the second preset position on the soldering resist to form a second soldering resisting layer.

After the plastic encapsulation is completed, firstly remove the carrier layer that is one layer away from the insulating layer from the conductive circuit. Specifically, the carrier layer of the detachable support layer can be peeled off by a plate separator. Subsequently, the remaining strippable copper layer is removed by etching to expose the side of the conductive circuit away from the first solder resist layer. At this time, the other surfaces of the conductive circuit except the side in contact with the peelable copper layer are covered by the first solder resist layer. Therefore, during etching, the etchant will not etch the side of the conductive circuit, thereby affecting the conductive circuit. line width. That is, the etching process does not cause undercutting of the conductive lines at all, so in this embodiment, conductive lines with arbitrary line widths, including ultra-fine conductive lines, can be prepared and obtained.

After the entire detachable support layer is removed, the side of the conductive circuit away from the first solder resist layer is exposed, and a second solder resist layer is prepared at a second preset position on the side of the conductive circuit away from the first solder resist layer.

In a specific application scenario, the solder resist film can be prepared on the whole board on the side where the conductive circuit is far away from the first solder mask layer, and then the solder mask film is opened, so that the conductive circuit is far away from the first solder mask layer. All positions on the side except the second predetermined position are exposed to obtain a second solder resist layer.

In another specific application scenario, it is also possible to open a window on the solder resist film corresponding to all positions except the second preset position, and then apply it to the conductive circuit far away from the first solder resist layer. One side, thereby exposing part of the conductive circuit, and covering the conductive circuit at the second preset position through the second solder resist layer.

Wherein, after the window is opened, the position where the side of the conductive line away from the first solder resist layer is not covered by the second solder resist layer is used for ball planting or for electrical connection with other devices.

In this step, the material, preparation method, window opening method, etc. of the second solder resist layer are the same as those of the first solder resist layer, please refer to the above, and will not repeat them here.

In a specific application scenario, after windowing the solder mask, a surface treatment layer can also be prepared at the position where the conductive circuit is not covered by the solder mask, so as to improve the quality of subsequent mounting, welding or electrical connection of the conductive circuit. Wherein, the material and preparation method of the surface treatment layer in this step are the same as the material and preparation method of the surface treatment layer in step S23, please refer to the above, and will not repeat them here.

Through the above steps, the preparation method of the packaging mechanism of this embodiment uses the strippable copper layer as a temporary carrier for the preparation of the conductive circuit, and utilizes the stability and mechanical strength of the strippable copper layer to improve the accuracy and reliability of the conductive circuit. After preparing a conductive line with any line width on the surface, cover a part of the conductive line with the first solder resist layer, and after the exposed part of the conductive line is connected to the chip, then wrap the plastic chip with the insulating layer, so that the first solder resist layer The insulating layer protects the other sides of the conductive circuit except the side that contacts the separable support layer, thereby reducing the possible impact on the conductive circuit when the separable support layer is removed, thereby improving the fineness and reliability of the conductive circuit, and further Improve the quality and reliability of the packaging mechanism. In addition, in this embodiment, the conductive circuit is directly wrapped by the first solder resist layer, and then the insulating layer is plastic-encapsulated, and the plastic sealing of the chip and the packaging mechanism are carried out synchronously, which shortens the production steps, omits the dielectric layer, and the thickness of the final product packaging mechanism Thinner, smaller packaging volume, lighter structure, and when the packaging mechanism is a fan-out packaging mechanism, because the board is thinner, the fan-out line of the chip is shorter, and its dielectric transmission loss is also smaller. Moreover, the manufacturing method of the packaging mechanism of this embodiment shortens the production and supply chain of the packaging mechanism, has relatively low cost, relatively high production efficiency, is fully compatible with conventional packaging mechanism manufacturing equipment, has wide applicability, and is highly scalable.

In other embodiments, after the detachable support layer is removed, at least one underlying circuit layer can be prepared on the side of the conductive circuit away from the first solder resist layer by a build-up method, and then the at least one underlying circuit layer is further away from the first solder resist layer. A second solder resist layer is prepared on a second predetermined position on one side of the first solder resist layer. The specific steps of preparing the second solder resist layer at the second preset position in this embodiment are the same as those in the foregoing embodiments, please refer to the above, and details will not be repeated here.

In a specific application scenario, the bottom insulating layer and the copper layer can be laminated on the side of the conductive line away from the first solder resist layer, and then the first layer of bottom conductive layer can be fabricated by the methods of film attachment, exposure, development, etching, and film removal. circuit, and then repeat the above steps, and finally obtain at least one bottom circuit layer. After making all the bottom circuit layers, prepare the second solder resist layer and surface treatment layer at the relevant position of the outermost bottom circuit layer to expose the position for ball planting or electrical connection with other components or devices . In another specific application scenario, all insulating layers and copper layers may also be overlapped and laminated at one time to form at least one underlying circuit layer.

Wherein, the specific number of bottom circuit layers may be determined based on actual requirements, for example: 3 layers, 8 layers, 10 layers, etc., which are not limited here. In a specific application scenario, the number of at least one bottom line layer may range from 1 to 20 layers.

In other embodiments, after the chip is plastic-encapsulated, at least one top circuit layer can be prepared on the side of the insulating layer away from the conductive circuit by a build-up method, and a second circuit layer can be prepared on the side of the at least one top circuit layer away from the insulating layer. Three solder mask layers.

In a specific application scenario, a layer of copper layer can be prepared on the side of the insulating layer away from the conductive line by lamination, electroless copper plating, sputtering titanium/copper or electroplating, and then film, exposure, development, etching 1. The method of withdrawing the film is manufactured on the copper layer to obtain the first top circuit layer, and then the top circuit layer is fabricated layer by layer above the first top circuit layer. In another specific application scenario, all the top insulating layers and the top copper layers may also be overlapped and placed on the insulating layer, and at least one top circuit layer may be formed by one-time lamination.

Wherein, the specific number of top circuit layers may be determined based on actual needs, for example: 3 layers, 8 layers, 10 layers, etc., which are not limited here. In a specific application scenario, the number of at least one top line layer may range from 1 to 20 layers.

Among them, when the packaging mechanism needs to prepare at least one bottom circuit layer and at least one top layer circuit layer and related structures, at least one bottom layer circuit layer and its related structures can be prepared first, and then at least one top layer circuit layer and its related structures can be prepared. structure; at least one top circuit layer and its related structure can also be prepared first, and then at least one bottom layer circuit layer and its related structure can be prepared; it can also be prepared at the same time. Among them, when at least one top circuit layer and its related structure are prepared first, and then at least one bottom circuit layer and its related structure are prepared, the risk of cracks in the insulating layer caused by the separation of the carrier layer of the peelable copper layer can be reduced. When preparing at least one bottom circuit layer and its related structure, and then preparing at least one top layer circuit layer and its related structure, a finer bottom circuit layer can be produced.

In other embodiments, metallized through holes and/or metallized blind holes may be prepared between at least one bottom layer of circuit layers and/or at least one top layer of circuit layers to achieve conduction between circuit layers.

In a specific application scenario, when preparing at least one bottom circuit layer, the bottom insulating layer and the copper layer can be pressed on the side of the conductive circuit away from the chip first, and then the bottom insulating layer and the copper layer can be bonded by laser or plasma methods. Make blind holes and/or through holes on the layer, and further use electroless copper plating and/or electroplating to realize the metallization of blind holes and/or through holes, so as to realize the interlayer interconnection of the underlying circuit layer, and then use film, exposure, and development The first layer of bottom wiring layer is made on the copper layer by the methods of etching, film stripping, and then the above steps are repeated, and at least one bottom wiring layer is finally obtained layer by layer. In another specific application scenario, when preparing at least one bottom circuit layer, the ABF material can be vacuum-coated on the side of the conductive circuit away from the first solder mask layer, so as to obtain the bottom insulating layer, and then use laser or plasma The method is to make blind holes and/or through holes in the bottom insulating layer, and then further adopt electroless copper plating or sputtering titanium/copper or electroplating to realize the metallization of blind holes and/or through holes, and form a hole on the bottom insulating layer. layer copper layer, and then use the methods of film sticking, exposure, development, pattern plating, film removal, and rapid etching to make the first layer of bottom conductive circuit on the copper layer, and then repeat the above steps to finally obtain at least one layer of bottom circuit. layer. In another specific application scenario, when preparing at least one underlying circuit layer, a photosensitive material can also be vacuum-attached on the side of the conductive circuit away from the first solder resist layer, and then the blind hole is made by exposure, and then the The photosensitive material is cured to obtain the bottom insulating layer, and the method of electroless copper plating or sputtering titanium/copper or electroplating is further used to realize the metallization of the blind hole, and a layer of copper layer is formed on the bottom insulating layer, and then film, exposure, development, The method of graphic electroplating, film stripping and rapid etching is to make the first layer of bottom conductive circuit on the copper layer, and then repeat the above steps, and finally obtain at least one layer of bottom circuit layer. In another specific application scenario, at least one bottom circuit layer can be sequentially produced layer by layer by using the above three methods comprehensively.

In a specific application scenario, when preparing at least one top circuit layer, laser or plasma methods can be used to prepare blind holes and/or through holes on the insulating layer, and then electroless copper plating or sputtering titanium/copper The method realizes the metallization of blind holes and/or through holes, and forms a copper layer on the side of the insulating layer away from the chip, and then fills the blind holes and/or through holes by electroplating copper, and thickens the copper of the insulating layer Layer, or thicken the copper layer of the insulating layer and the metallization layer of the blind hole and/or through hole wall by electroplating copper, and fill the blind hole and/or through hole with resin plug holes. Then, the first top layer circuit layer is produced by the method of sticking film, exposing, developing, etching, and stripping the film. Subsequently, the remaining top circuit layers are fabricated layer by layer above the first top layer circuit layer. Wherein, the method for producing the remaining top circuit layer layer by layer is similar to the method for producing the remaining bottom circuit layer layer by layer, please refer to the above, and will not repeat them here.

After all the top circuit layers are prepared, a third solder resist layer is prepared on the side of the topmost circuit layer away from the chip. In a specific application scenario, the third solder resist layer can be prepared on the entire board on the side of the topmost circuit layer away from the chip, and then a window is opened on the third solder resist layer of the entire board to expose parts for planting. The topmost wiring layer for balls, electrical connections to other components or devices, or for printing solder paste or flux.

Wherein, the material and preparation method of the third solder resist layer are the same as those of the second solder resist layer and the first solder resist layer in the foregoing embodiments, please refer to the above, and details will not be repeated here.

In the above embodiments, metallized blind holes and/or through holes are prepared for interlayer interconnection in the process of preparing circuit layers layer by layer. In other embodiments, conductive circuits or peelable copper foils can be used as the On the basis, the conductive copper pillars are made by pasting dry film, exposure, development, electroplating copper pillars, and stripping the film, and then the chip and the conductive copper pillars are plastic-sealed, and the insulating layer is polished to the specified thickness to make the conductive copper pillars The top of the column is exposed so as to facilitate the conduction of other circuit layers and realize the interlayer interconnection between the circuit layers.

In other embodiments, when preparing the first solder resist layer, in addition to opening the window based on the pad bumps of the chip, the window can also be opened based on the position of the metallized blind hole at the same time to obtain the preliminary solder resist layer on the first solder resist layer. Holes are provided to expose part of the conductive lines through the preset holes. Furthermore, after the insulating layer is prepared, the insulating layer is drilled based on the position of the preset hole of the first solder resist layer to obtain a through hole on the insulating layer, and then metallized to realize the connection between the electric circuit and the top circuit layer. Connected, and then connect the upper and lower circuit layers of the insulating layer.

In other embodiments, after the packaging mechanism prepares the top circuit layer and/or the bottom circuit layer, through holes can be prepared on the entire board, and then electroless copper plating and/or electroplated copper are used for metallization of the through holes , and then realize the interlayer interconnection of each line layer. Among them, this embodiment defines whether the through hole needs a resin plug hole, specifically, if the through hole will be used for inserting and installing components later, no resin plug hole is required; if there is no need to install components or one end of the through hole If metallization is required to mount components, resin plugging is required.

Please refer to FIG. 4 . FIG. 4 is a schematic structural view of an embodiment of the packaging mechanism of the present application.

The packaging mechanism 100 of this embodiment includes a conductive circuit 13 , a first solder resist layer 14 , a chip 15 , an insulating layer 16 and a second solder resist layer 17 . Wherein, the first solder resist layer 14 is attached to one side of the conductive circuit 13, and fills the gap between the conductive circuits 13, and the first solder resist layer 14 is provided with at least one hole 141, at least one hole 141 is used for In the exposed part of the conductive circuit 13. The chip 15 is arranged on the side of the first solder resist layer 14 away from the conductive circuit 13, and the chip 15 is electrically connected to the conductive circuit 13 through at least one hole 141; the insulating layer 16 is covered on the chip 15 and filled with the chip 15 and the The gap between the first solder resist layers 14 is used to plastic-encapsulate the chip 15 , and the second solder resist layer 17 is disposed on the side of the conductive circuit 13 away from the first solder resist layer 14 .

That is, the side of the conductive circuit 13 close to the second solder resist layer 17 is coplanar with the side of the second solder resist layer 17 close to the conductive circuit 13 . The first solder resist layer 14 is located on the side of the conductive circuit 13 away from the second solder resist layer 17, and wraps the conductive circuit 13 therein, and the first solder resist layer 14 is close to the side of the second solder resist layer 17 and the conductive circuit 13 The side close to the second solder resist layer 17 is coplanar.

The insulating layer 16 is located on the side of the chip 15 away from the conductive circuit 13, and wraps the chip 15 and the first solder resist layer 14 therein, and the side of the insulating layer 16 close to the first solder resist layer 14 is close to the first solder resist layer 14 One side of the insulating layer 16 is coplanar.

Through the above structure, the packaging mechanism of this embodiment can wrap the plastic-sealed chip through the insulating layer, and then use the first solder resist layer and the insulating layer to protect the other sides of the conductive circuit except the side contacting the second solder resist layer, thereby reducing the electrical conductivity. The circuit may be affected, thereby improving the fineness and reliability of the conductive circuit, thereby improving the quality and reliability of the packaging mechanism. In addition, in this embodiment, the conductive circuit is directly wrapped by the first solder resist layer, and then the insulating layer is plastic-encapsulated, and the dielectric layer is omitted. The thickness of the final product packaging mechanism is thinner, the packaging volume is smaller, and the structure is lighter. When the packaging mechanism is In the fan-out packaging mechanism, since the board is thinner, the fan-out line of the chip is shorter, and its dielectric transmission loss is also smaller.

In other embodiments, the insulating layer 16 is located on the side of the chip 15 away from the conductive circuit 13 and can only wrap the chip 15 therein. One side of the solder resist layer 17 is coplanar.

In other embodiments, the chip 15 includes a chip body 152 and at least one pad bump 151 . The chip body 152 is electrically connected to at least one pad bump 151 respectively. And at least one pad bump 151 respectively passes through at least one hole 141 on the first solder resist layer 14 to be soldered to the conductive circuit 13 , so as to connect the chip body 152 and the conductive circuit 13 .

Chip 15 may comprise a flip chip or other chip.

In other embodiments, the insulating layer 16 is covered on the chip 15, and fills the gap between the chip 15, the pad bump 151 and the first solder resist layer 14, thereby completing the connection between the chip 15 and the conductive circuit 13. Plastic sealing, and then encapsulating the entire board.

In other embodiments, a surface treatment layer (not shown in the figure) is attached to one side of the conductive circuit 13 at a position corresponding to at least one hole 141, and the surface treatment layer is arranged on the conductive circuit 13 and the pad bump 151 , so as to improve the quality of mounting the chip 15 on the exposed conductive circuit 13 through the bonding pad bump 151 .

Wherein, the surface treatment layer includes one or more of a silver layer, a nickel layer, a palladium layer, a gold layer, a tin layer, and an organometallic compound layer, which can be selected based on actual needs.

In other embodiments, the line width of the conductive line 13 is in the range of 1-20 microns, that is, the conductive line 13 can be an ultra-fine conductive line, for example: 1 micron, 5 microns, 8 microns, 10 microns, 13 microns, 16 microns, 20 microns, etc., which can be selected based on actual needs.

In other embodiments, the conductive lines 13 include one or more of copper lines, silver lines, gold lines, nickel lines, tin lines, palladium lines, cobalt lines, ruthenium lines, and molybdenum lines, which can be based on actual needs. choose.

Wherein, the conductive circuit 13 can be used for fanning out the pins of the chip 15 , and also used for welding with the pad bump 151 of the chip 15 to conduct the chip 15 .

In other embodiments, the line width range of the conductive line 13 may also be in any width range.

In other embodiments, the thickness of the first solder resist layer 14 is in the range of 5-50 microns. Specifically, it can be 5 microns, 10 microns, 13 microns, 20 microns, 24 microns, 26 microns, 28 microns, 30 microns, 35 microns, 36 microns, 39 microns, 42 microns, 46 microns, 50 microns, etc. Wherein, the thickness of the first solder resist layer 14 is greater than that of the conductive lines 13 so as to completely cover and protect the conductive lines 13 and fill the gaps between the conductive lines 13 .

In other embodiments, at least one through groove 171 is formed on the second solder resist layer 17 , and at least one through groove 171 exposes a part of the surface of the conductive circuit 13 away from the first solder resist layer 14 . This part of the surface can be used for planting balls on the conductive circuit 13 , and then used for soldering the packaging mechanism 100 to the printed circuit board, other components or other devices.

The second solder resist layer 17 is used to protect the conductive circuit 13 from oxidation, corrosion, scratch resistance, electrical insulation and water vapor isolation during the transportation, storage and use of the packaging mechanism 100, and between the packaging mechanism 100 and the printing It acts as a solder mask when soldering circuit boards, other components or other equipment.

In other embodiments, the insulating layer 16 may include an organic resin layer and a silicon dioxide layer, and the proportion of the silicon dioxide layer in the insulating layer 16 is in the range of 1-95%, specifically 1%, 20%, or 1%. 50%, 62%, 75%, 80%, 90%, 95%, etc., can be set based on actual conditions, and are not limited here.

Wherein, the thickness of the insulating layer 16 is greater than or equal to the height difference between the side of the chip 15 away from the conductive circuit 13 and the side of the first solder resist layer 14 away from the conductive circuit 13 , so as to package the entire chip 15 in plastic.

Please refer to FIG. 5 . FIG. 5 is a schematic structural diagram of another embodiment of the packaging mechanism of the present application. Among them, the connection relationship, position structure, thickness range, composition, etc. among the conductive circuit, the first solder resist layer, the chip, the solder bump and the insulating layer in the packaging mechanism of this embodiment are the same as those of the previous embodiment, please refer to the previous , which will not be repeated here.

In this embodiment, the packaging mechanism 200 further includes: at least one bottom circuit layer 220 and/or at least one top layer circuit layer 219.

Wherein, at least one underlying circuit layer 220 is stacked between the conductive circuit 213 and the second solder resist layer 217 . Specifically, each underlying circuit layer 220 includes a bottom conductive circuit 2201 , a bottom insulating layer 2203 and at least one interconnection hole 2202 . At least one interconnection hole 2202 is connected to the conductive layer on the side close to the chip, and the side of the interconnection hole 2202 away from the chip is connected to the bottom conductive circuit 2201, and the bottom insulating layer 2203 fills the gap between the conductive layer and the bottom conductive circuit 2201 . The conductive layer here includes other bottom conductive traces 2201 or conductive traces 213 . The interconnection hole 2202 may be a metallized hole or a metal pillar, and specifically may include a through hole or a blind hole.

The second solder resist layer 217 is adhered to the second preset position on the side of the at least one underlying circuit layer 220 away from the chip. Specifically, the second solder resist layer 217 is attached to the second predetermined position on the side of the bottom conductive circuit 2201 farthest from the chip of at least one bottom circuit layer 220 away from the chip. The position of the bottom conductive circuit 2201 not covered by the second solder resist layer 217 is used for soldering the packaging mechanism 200 to a printed circuit board, other components or other devices.

And at least one top circuit layer 219 is disposed on the side of the insulating layer away from the chip. Specifically, a first top circuit layer 226 is bonded on the side of the insulating layer away from the chip, and at least one top circuit layer 219 is disposed on the side of the first top circuit layer 226 away from the chip.

Wherein, each top circuit layer 219 includes a top conductive circuit, a top insulating layer and at least one interconnection hole, and its specific setting method is similar to that of the bottom circuit layer 220 , please refer to the above, and will not repeat them here.

The third solder resist layer 218 is adhered to the third preset position on the side of the at least one top circuit layer 219 away from the chip. Specifically, the third solder resist layer 218 is attached to the third predetermined position on the side of the top conductive circuit farthest from the chip on the top conductive circuit of at least one top circuit layer 219 away from the chip. The portion of the top conductive circuit not covered by the third solder resist layer 218 is used for soldering passive components or various chips and modules.

In other embodiments, the packaging mechanism 200 further includes: a metallized through hole 222 and/or a metallized blind hole 223 . Wherein, the metallized through hole 222 runs through the entire packaging mechanism 200 and can communicate with all circuit layers or a part of the circuit layer, while the metallized blind hole 223 is provided inside the packaging mechanism 200 to communicate with part of the circuit layers.

Wherein, the metallized blind hole 223 can be connected to any circuit layer based on actual requirements.

The metalized blind holes 223 in this embodiment include metal blind holes 2231 and conductive copper posts 2241 . The metal blind hole 2231 and the conductive copper pillar 2241 can connect the bottom circuit layer 220 and the top circuit layer 219 . In other embodiments, the metal blind vias 2231 and the conductive copper posts 2241 may be located between at least one bottom circuit layer 220 or between at least one top circuit layer 219 .

Please refer to FIG. 6 . FIG. 6 is a schematic structural diagram of another embodiment of the packaging mechanism of the present application. Wherein, in the packaging mechanism of this embodiment, at least one bottom circuit layer, at least one top layer circuit layer, metallized blind holes, metallized through holes, conductive lines, first solder resist layer, chip, solder bumps and insulating layer The connection relationship, location structure, thickness range, composition, etc. are the same as those of the foregoing embodiments, please refer to the foregoing, and will not repeat them here.

The packaging mechanism 300 of this embodiment further includes one or more of a resistor 303 , a capacitor 304 , an inductor 305 , a passive element 302 and a functional semiconductor device 301 . Wherein, the resistor 303, the capacitor 304 and the inductor 305 can be embedded in the bottom circuit layer in the form of a thin film, and be in contact with the bottom circuit layer for conduction; and the top circuit layer can also contain a passive element 302 and a functional semiconductor device 301, Among them, the passive element 302 may include one or more of resistors, capacitors and inductors; the functional semiconductor device 301 may include one or more of storage devices, power devices, logic devices, optoelectronic devices, analog devices, and discrete devices ; In an embodiment, the functional semiconductor device 301 is interconnected with the top wiring layer through the wire 306 .

Through the above structure, the packaging mechanism of this embodiment saves the existence of the dielectric layer through the arrangement of conductive lines, chips and insulating layers, and can obtain a packaging mechanism with a thinner thickness and smaller packaging volume, improving the portability of the packaging mechanism and applicable range, and due to the removal of the dielectric layer, the dielectric transmission loss in the packaging mechanism is reduced, and through at least one bottom circuit layer, at least one top layer circuit layer, metallized through holes and/or blind holes and other components And so on to further develop the three-dimensional packaging of the packaging mechanism, so as to further improve the performance and versatility of the packaging mechanism.

The above is only the implementation of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process conversion made by using the specification and drawings of the application, or directly or indirectly used in other related technologies fields, are all included in the scope of patent protection of this application in the same way.

Claims

A method for preparing a packaging mechanism, characterized in that the method for preparing the packaging mechanism comprises:

A detachable support layer is obtained;

performing electroplating on a first predetermined position of the detachable support layer to form a conductive line at the first predetermined position;

preparing a first solder resist layer on the side of the conductive circuit away from the detachable support layer, and exposing part of the conductive circuit;

electrically connecting the chip to the exposed part of the conductive circuit, and plastic-encapsulating the chip to form an insulating layer;

The detachable support layer is removed, and a second solder resist layer is prepared at a second preset position on the side of the conductive circuit away from the first solder resist layer.
The method for manufacturing a packaging mechanism according to claim 1, wherein the detachable support layer comprises a peelable copper layer and a carrier layer that are stacked and bonded together;

The step of electroplating the first preset position of the detachable support layer to form a conductive circuit at the first preset position includes:

performing electroplating on a first predetermined position of the strippable copper layer of the detachable support layer to form a conductive line at the first predetermined position;

The step of removing the detachable support layer comprises:

removing the carrier layer; and

The strippable copper layer is removed by etching to expose a side of the conductive line away from the first solder resist layer.
The manufacturing method of the packaging mechanism according to claim 2, characterized in that, the step of electroplating the first preset position of the detachable support layer to form a conductive circuit at the first preset position include:

preparing a photosensitive resist layer on the side of the strippable copper layer away from the carrier layer;

sequentially performing exposure and development on the side of the strippable copper layer provided with the photosensitive resist layer, so as to prepare a groove pattern at the first preset position;

performing pattern electroplating on the groove pattern at the first preset position, so as to form a conductive circuit at the first preset position;

removing the photosensitive resist layer.
The manufacturing method of the packaging mechanism according to claim 1, characterized in that, the step of preparing a first solder resist layer on the side of the conductive circuit away from the detachable support layer, and exposing part of the conductive circuit include:

preparing the entire board of the solder mask to the side of the conductive circuit away from the detachable support layer by means of attachment, dip coating, spray coating or spin coating;

performing window opening treatment on the solder resist film to form the first solder resist layer.
The manufacturing method of the packaging mechanism according to claim 1, characterized in that, after the step of exposing part of the conductive circuit, it further comprises:

A surface treatment layer is made on the exposed part of the conductive circuit.
The preparation method of the packaging mechanism according to claim 1, wherein the step of electrically connecting the chip with the exposed part of the conductive circuit, and plastic-sealing the chip to form an insulating layer comprises:

Welding the pad bump on the chip and the exposed part of the conductive circuit by reflow soldering;

The chip is plastic-sealed with a plastic-encapsulation material to form the insulating layer around the chip.
The method for manufacturing a packaging mechanism according to claim 1, wherein the detachable support layer is removed, and a second solder mask is prepared at a second preset position where the conductive circuit is far away from the first solder resist layer. The steps for the solder mask include:

removing the detachable support layer to expose a side of the conductive circuit away from the first solder resist layer;

preparing the entire board of the solder resist film to the side of the conductive circuit away from the first solder resist layer by attaching, dip coating, spray coating or spin coating;

Carrying out window treatment on positions on the solder resist film other than the second preset position to form the second solder resist layer.
The method for manufacturing a packaging mechanism according to any one of claims 1-7, characterized in that, after the step of removing the detachable support layer, the conductive circuit is far away from the first solder resist layer Before the step of preparing the second solder resist layer at the second preset position on one side includes:

preparing at least one underlying circuit layer on the side of the conductive circuit away from the first solder resist layer by a build-up method;

The step of preparing a second solder resist layer at a second preset position on the side of the conductive circuit away from the first solder resist layer includes:

The second solder resist layer is prepared at a second predetermined position on the side of the at least one underlying circuit layer away from the first solder resist layer.
The preparation method of the packaging mechanism according to any one of claims 1-7, characterized in that, the preparation method of the packaging mechanism further comprises:

preparing at least one top circuit layer on the side of the insulating layer away from the conductive circuit by a build-up method;

A third solder resist layer is prepared on the side of the at least one top circuit layer away from the insulating layer.
A packaging mechanism, characterized in that the packaging mechanism comprises:

conductive lines;

The first solder resist layer is attached to one side of the conductive circuit and fills the gap between the conductive circuits, and the first solder resist layer is provided with at least one hole;

A chip is disposed on a side of the first solder resist layer away from the conductive circuit, and the chip is electrically connected to the conductive circuit through the hole;

an insulating layer covering the chip and filling the gap between the chip and the first solder resist layer;

The second solder resist layer is disposed on a side of the conductive circuit away from the first solder resist layer.
The packaging mechanism according to claim 10, wherein the chip includes a chip body and at least one pad bump, and the chip body is electrically connected to at least one pad bump;

The at least one pad bump is correspondingly passed through at least one hole in the first solder resist layer and soldered to the conductive circuit.
The packaging mechanism according to claim 11, characterized in that,

The insulating layer covers the chip and fills the gap between the chip, the pad bump and the first solder resist layer.
The packaging mechanism according to claim 11, characterized in that,

A surface treatment layer is attached to one side of the conductive circuit at a position corresponding to the at least one hole;

And the surface treatment layer is disposed between the conductive circuit and the pad bump.
The packaging mechanism according to claim 10, characterized in that,

The line width of the conductive line is in the range of 1-20 microns.
The packaging mechanism according to claim 10, characterized in that,

The thickness range of the first solder resist layer is 5-50 microns.
The packaging mechanism according to claim 10, further comprising: at least one underlying circuit layer;

At least one underlying circuit layer is stacked between the conductive circuit and the second solder resist layer.
The packaging mechanism according to claim 10 or 16, wherein the packaging mechanism further comprises: at least one top circuit layer and a third solder resist layer;

At least one top circuit layer is disposed on a side of the insulating layer away from the chip;

The third solder resist layer is attached to the side of the at least one circuit layer away from the insulating layer.
The packaging mechanism according to claim 17, further comprising: metallized through holes and/or metallized blind holes;

Wherein, the metallized through hole is used for electrical connection with each circuit layer, and the metallized blind hole is used for electrical connection with at least two circuit layers.
The packaging mechanism according to claim 17, further comprising: one or more of resistors, capacitors, inductors, passive components and functional semiconductor devices.