201029125 f 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種嵌埋半導體晶片之封裝基板及其製 . 法，尤指一種當半導體晶片電極墊縮小時，可避免雷射開 .5 孔對位偏差而導致晶片損壞之嵌埋半導體晶片之封裝基板 及其製法。 【先前技術】 ® 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 10 能、高性能的研發方向。為滿足半導體封裝件高積集度 (integration)以及微型化（miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (interlayer connection)擴大電路板上可利用的佈線面積而 15 配合高電子密度之積體電路（integrated circuit)需求。 一般半導體裝置之製程，首先係由晶片載板製造業者 • 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 線、封膠以及植球等封裝製程。又一般半導體封裝是將半 20 導體晶片背面黏貼於封裝基板頂面進行打線接合（wire bonding)，或者將半導體晶片之作用面以覆晶接合（flip chip) 方式與封裝基板接合，再於基板之背面植以焊料球以供與 其他電子裝置進行電性連接。 4 201029125 隨著技術發展，近來有許多研究發展出半導體晶片嵌 埋於基板中之方法，在相同封裝單位體積中容納更多數量 的線路及半導體晶片，以滿足電子產品輕薄短小化之需 求。業界現行嵌埋晶片於基板之技術中，多將晶片埋入基 5 板後，於晶片及基板表面同時進行增層，透過增層線路層 及導電盲孔所構成之層間電性連接結構（interlayer electrically connecting structure)將半導體晶片之電極墊扇 出（fan out)。 請參閱圖1A至圖ID，此為習知之嵌埋半導趙晶片之封 10 裝結構之製作流程剖視圖。首先，如圖1A所示，提供一第 一承載板1，並於第一承載板1上形成一第二承載板1〇，其 中第二承載板具有一貫穿開口 ιοί。接著，提供一半導體 晶片11 ’並將其置入第二承載板10之貫穿開口 101中，其中 半導體晶片11具有複數電極墊111，如圖1B所示。而後，在 15 半導體晶片Π與第二承載板10上以熱壓形成一第一介電層 12，如圖1C所示。最後，以雷射在第一介電層12中形成複 魯 數盲孔121，再於盲孔121中及第一介電層12上形成導電盲 孔131及第一線路13，以電性連接半導體晶片丨丨之電極墊 111 ’如圖1D所示。 20 接著，請參閱圖2A及圖2B，此為習知以雷射形成盲孔 之示意圖。如圖2 A所示之例子中，習知電極塾hi之寬度w 係為100仁m’而目前雷射光束之最小光徑l係為60 ym,其 中雷射光束具有±15#m之對位偏差D，故雷射光束之光徑 範圍會介於90 " m範圍内。因此，在電極墊111之寬度w為 5 201029125 ψ 100 /ζ m之情況下，若使用光徑L為60 /ζ m之雷射光束，即使 對位不精準，雷射光束仍打在電極墊111上，而不會損害到 半導體晶片11之表面。 為因應電子產品輕薄短小化之需求，半導體晶片尺寸 5 也隨之縮小，造成電極塾之表面積也相對縮小。如圖2B所 示之例子中，當電極塾111寬度W縮小至80以m時，由於目 前雷射光束之最小光徑L係為60 y m且具有± 15私m之對位 偏差D，因此，在對位不夠精準的情形下，會造成雷射光束 ^ 打在半導體晶片11電極塾ill周緣外之表面的情形發生，而 10 損壞半導體晶片11之表面，導致產品良率降低。 綜上所述’習知之嵌埋半導體晶片之封裝基板，係先 將半導想晶片置入已開口之基板中，再以雷射鑽孔。然而， 由於半導體晶片置入並固定於基板之開口時可能會有對位 偏差’而降低後續製程之對位精準度。同時，隨著電子產 15 品逐漸往微型化發展之需求，半導體晶片上之電極墊也隨 之縮小。然而，在製程上雷射光束之光徑大小仍有其限制， 鲁 且雷射光束本身亦有對位偏差。因此，當半導體晶片之電 極墊縮小時’以習知製作嵌埋半導體晶片之封裝基板，可 能會產生雷射光束打在電極塾周緣外而破壞半導體晶片之 20 情形，而造成良率降低β 因此，現行亟需研發出能改善上述問題或缺點之封裝 基板結構及其製法，以避免因對位不精準而造成雷射光束 打在半導體晶片電極墊周緣外表面而損壞半導體晶片之情 形。 6 201029125 【發明内容】 本發明之主要目的係在提供一種嵌埋半導體晶片之封 裝基板，其利用—導接環以防止雷射開孔破壞半導體晶片 表面’而導致良率降低。 5 本發明之另一目的係在提供一種换埋半導艘晶片之封 裝基板=製法，藉由在麼合介電層前先將半導體晶片與承 載板固疋並在雷射開孔前形成-導接環，以提升雷射鐵 孔之精準度。 ^ 嚳 I達成上述目的，本發明之第—實施態樣係提供一種 ίο故埋半導體晶片之封裝基板，包括：一第一介電層，具有 一第一表面及相對之—第二表面卜半導體晶片，係設於 該第一介電層中，該半導體晶片具有相對之一作用面與一 非作用®，該作用自具有複數電極塾，且該作用面係面向 該第一表面；一黏著層，係位於該半導體晶片之該作用面 15上並具有一第三表面，且該第三表面係外露於該第一介電 層之該第一表面；複數具有開孔之導接環係嵌埋並外露 ❹ 於該黏著層之一第三表面上且對應於各該電極墊；以及複 數第一導電盲孔，係設於該黏著層中，各該第一導電盲孔 之頂部係與各該導接環相對應並填滿開孔且延伸至導接環 20表面，其中部分該第一導電盲孔之頂部係做為電性連接 墊，又各該第一導電盲孔之底部係電性連接至各該電極墊。 此外，本發明之第二實施態樣係提供一種嵌埋半導體 晶片之封裝基板，包括：一金屬板，具有一第五表面及一 第六表面，其中該金屬板具有一開口；一半導體晶片，係 7 201029125 i 設於該開口中，該半導體晶片具有相對之一作用面與一非 作用面，且該作用面與該第五表面同側且具有複數電極 墊，一導熱材料，係填充於該金屬板之該開孔與該半導體 晶片間之間隙令；一第一介電層，具有一第一表面及相對 5 之一第二表面，且該第二表面係與該金屬板之該第五表面 相結合；一黏著層，係位於該半導體晶片之該作用面上並 具有一第三表面，且該第三表面係外露於該第一介電層之 該第一表面；複數具有開孔之導接環，係嵌埋並外露於該 • Ί 占著層t第二表面上且對應於各該電極塾；以及複數第 10 導電盲孔，係設於該黏著層中，各該第一導電盲孔之頂 部係與各該導接環相對應並填滿開孔且延伸至導接環表 面’其中部分該第一導電盲孔之頂部係做為 電性連接墊， 又各該第—導電盲孔之底部係電性連接至各該電極墊。 於本發明之第二實施態樣之封裝基板中，該半導體晶 15片之該非作用面可外露於該金屬板之該第六表面。或，該 半導趙sa片之厚度可小於該金屬板之厚度，該導熱材料更 參 覆蓋該半導體晶片之該非作用面，且該導熱材料係外露於 該金屬板之該第六表面。亦或，該導熱材料可更覆蓋該半 導趙晶片之該非作用面與該金屬板之該第六表面。 20 本發明之第一或第二實施態樣之封裝基板，其更包括 第一線路，係嵌埋並外露於該第一介電層之第一表面及 該黏著層之第三表面，且該第一線路係電性連接至部分該 導接環。 8 201029125 t 本發明之第一或第二實施態樣之封裝基板，可更包括 一第一增層結構，係設於該第一線路及該第一介電層之該 第一表面上’該第一增層結構係包括至少一第二介電層、 至少一設於該第二介電層上之第三線路層、及複數設於該 5 第二介電層中且電性連接該第三線路層之第二導電盲孔， 其中部分該第二導電盲孔係電性連接至該第一線路，且另 部分第二導電盲孔係電性連接至該電性連接墊，而最外層 之第二線路層具有複數電性接觸塾。此外，上述之封裝基 ® 板可更包括一防焊層’係設於該第一增層結構之表面，且 10 該防焊層具有複數防焊層開孔以露出各該電性接觸墊。 於本發明之第一實施態樣之封裝基板中，該第一介電 層之該第二表面係設有一第二線路層。此外，上述之封裝 基板可更包括一第二增層結構，係設於該第二線路層及該 第一介電層之該第二表面上，該第二增層結構係包括至少 15 一第二介電層、至少一設於該第二介電層上之第三線路 層、及複數設於該第二介電層中且電性連接該第三線路層 φ 之第二導電盲孔’其中部分第二導電盲孔係電性連接至第 二線路層’且最外層之第三線路層具有複數電性接觸墊。 同時’上述之封裝基板可更包括一防焊層，係設於該第二 20 增層結構之表面，且該防焊層具有複數防焊層開孔以露出 各該電性接觸墊。 於上述之封裝基板中，該黏著層之材料可為樹脂。 本發明除提供上述之嵌埋半導體晶片之封裝基板外， 更提供其製作方法。 9 201029125 之贺ί發明係提供一種嵌埋半導體晶片之封裝基板 系^"括·（Α)提供一承載板，並於該承載板上形 線路層，其中該第—線路層具有複數具有開孔之 環，（Β)提供一半導趙晶片，其具有相對之一作用面 及非作用面’其令該作用面具有複數電極堅’且一黏著 層係形成於該作用面上；⑹藉由該黏著層貼合該承載板 與該半導想晶片，其中該半導趙晶片之該作用面係面向該 承載板上之該第一線路層’各該電極塾係對應於各該導接 • 冑之開孔，以使該黏著層位於該第一線路層與該半導體晶 10 >1之該作用面間並填入該導接環之開孔内；（D)於該承載 板、該第-線路層、及該半導體晶片之該非作用面上形成 一第一介電層，使該半導體晶片埋於該第一介電層中其 中該第一介電層具有一第一表面及相對之一第二表面且 該第一線路層係嵌埋於該第一表面；（Ε)移除承載板以 15外露該第-線路層；（F)移除對應該導接環之開孔之黏著 層，並形成與開孔相連通之複數盲孔以外露該電極墊；以 φ 及於該盲孔中形成複數第一導電盲孔，各該第一導電盲 孔之頂部係與各該導接環相對應並填滿開孔且延伸至導接 環表面，其中部分該第一導電盲孔之頂部係做為電性連接 20墊，又各該第一導電盲孔之底部係電性連接至各該電極墊。 其中，步驟（G)後，係在該第一線路層之該第二表面上 形成一第二線路層。此外，於步驟（G)後，上述之製法可更 包括一步驟（H):於該第一線路層及該第一介電層之該第一 表面上形成一第一增層結構。同時，於步驟（G)後，上述之 201029125 製法可更包括一步驟（Η，）：於該第二線路層及該第一介電層 之該第二表面上形成一第二增層結構。其中，該第一增層 結構及該第二增層結構係分別包括至少一第二介電層、至 少一設於該第二介電層上之第三線路層、及複數設於該第 5 二介電層中且電性連接該第三線路層之第二導電盲孔，其 中，部分該第二導電盲孔係電性連接至該第一線路層，部 分該第二導電盲孔係電性連接至該第二線路層，且另部分 第二導電盲孔252係電性連接至該電性連接墊222，而最外 丨層之第三線路層253具有複數電性接觸墊254。 10 同時，於上述製法中，於該第一及第二增層結構之表 面上更分別形成一防焊層，且該防烊層具有複數防焊層開 孔以露出各該電性接觸墊。 此外，本發明更提供另一種嵌埋半導體晶片之封裝基 板之製法，係包括：一種嵌埋半導體晶片之封裝基板之製 15 法，係包括：（Α)提供一承載板，並於該承載板上形成一 第一線路層，其中該第一線路層具有複數具有開孔之導接 > 環；（Β)提供一半導鱧晶片，其具有相對之一作用面及一 非作用面’其中該作用面具有複數電極墊，且一黏著層係 形成於該作用面上；（C)藉由該黏著層貼合該承載板與該 2〇半導體晶片，其中該半導體晶片之該作用面係面向該承載 板上之該第一線路層，各該電極墊係對應於各該導接環之 開孔’以使該黏著層位於該第一線路層與該半導體晶片之 該作用面間並填入該導接環之開孔内；（D)於該承載板及 線路層上形成一第一介電層，使該黏著層埋於該第 201029125 一介電層中，其中該第一介電層具有一第一表面及相對之 一第一表面，且該第一線路層係嵌埋於該第一表面；（E)於 該第一介電層之一第二表面上層疊一具有一開口之金屬 板，使該半導體晶片置於該開口中，且一導熱材料係填充 5於該金屬板之該開口與該半導體晶片間之間隙中；（F)移 除承載板，以外露該第一線路層；移除對應該導接環 之開孔之黏著層’並形成與開孔相連通之複數盲孔以外露 該電極墊；以及（H)於該盲孔中形成複數第一導電盲孔，各 攀 It第-導電盲孔之頂冑係與各該導接環相對應並填滿開孔 10且延伸i導接環表面，纟中部分該第一導電盲孔之頂部係 做為電性連接墊，又各該第一導電盲孔之底部係電性連接 至各該電極塾。 於上述製法之步驟（E)中，該半導體晶片之該非作用面 可外露於該金屬板之一第六表面。或，該半導想晶片之厚 15度可小於該金屬板之厚度，該導熱材料更覆蓋該半導艘晶 片之該非作用面，且該導熱材料係外露該金屬板之一第六 馨表面。減’該導熱材料可更覆蓋該半導體晶片之該非作 用面與該金屬板之一第六表面。 此外，於步驟（G)後，上述之製法可更包括一步驟（I) ·· 20於該第一線路層及該第一介電層之該第一表面上形成一第 一增層結構，其中該第一增層結構係包括至少一第二介電 層、至少-权於該第二介電層上之第三線路層及複數設 於該第二介電層中且電性連接該第三線路層之 孔，其中部分該第二導電盲孔係電性連接至該第一線路， 12 201029125 且另部分第二導電盲孔係電性連接至該電性連接墊，而最 外層之第三線路層具有複數電性接觸墊。同時，於該第一 增層結構之表面上可更形成一防焊層，且該防焊層具有複 數防焊層開孔以露出該電性接觸墊。 5 於上述之兩種嵌埋半導體晶片之封裝基板之製法中， 該承載板可更具有一第一導體層，且該第一線路層係形成 於該第一導體層上。此外，該黏著層之材料係為樹脂。 由於本發明之嵌埋半導體晶片之封裝基板之製法，係 在介電層壓合前即將半導體晶片與承載板結合，以提升後 10 續製程精準度。相較於習知之製作方法，即先將半導體晶 片置入已開口之基板’壓合介電層後，再進行雷射鑽孔， 本發明可解決半導體晶片置入基板之開口時之對位偏差的 問題。 此外，因微型化需求使得半導體晶片上之電極墊縮 15 小’故以習知方法製作嵌埋半導體晶片之封裝基板時，可 能會因雷射光束本身之對位偏差，而產生雷射光束破壞半 導體晶片之情形。然而’利用本發明之嵌埋半導體晶片之 封裝基板及其製法，其透過導接環以控制雷射光束僅會打 在電極墊上而不會打在半導體晶片電極墊周緣外表面上。 20 因此’即使電極墊縮小’仍可透過導接環控制雷射鑽孔區 域’而避免雷射光束破壞半導體晶片表面，以提升產品之 良率。 【實施方式】 13 201029125 ▼ 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 5可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 實施例1 請參考圖3A至圖3H，此為本實施例之嵌埋半導體晶片 • 之封裝結構之製作流程剖視圖。 10 如圖3A所示，首先，提供一承載板2，並於承載板2上 形成一第一線路層22,其中第一線路層22具有複數具有開 孔220之導接環22a。同時，第一線路層22更具有第一線路 22b » 此外，如圖3A所示，承載板2更可具有一第一導體層 15 2a’且第一線路層22係形成於該第一導體層2&上。其_， 承載板2之材料係為一絕緣材料，而第一導體層以係可為一 •金屬層’其材料係例如為一銅箔。因此，利用此第一導體 層2a可以電鍍形成第一線路層22在承載板2上。 接著，如圖3A所示’提供一半導體晶片21，其具有相 20 對之一作用面2la及一非作用面21b，其中作用面21a具有複 數電極塾211 ’且一黏著層23係形成於作用 面21a上。在此， 係利用印刷或貼合等方式，將樹脂形成在半導體晶片2之作 用面21a上，以形成黏著層23。 14 201029125 隨後，如圖3B所示，藉由黏著層23以貼合承載板2與半 導體晶片21’其中半導體晶片21之作用面21a係面向承載板 2上之第一線路層22，各電極墊211係對應於各導接環22&之 開孔220,以使黏著層23位於第一線路層22與半導體晶片21 5 之作用面21a間並填入導接環22a之開孔220内。如此，第一 線路層22即與電極墊211之對位完成，且透過黏著層23即可 將半導體晶片21與承載板2上之第一線路層22固定。。 接下來，如圖3C所示’於承載板2、第一線路層22、及 丨半導體晶片21之非作用面21b上形成一第一介電層2〇,使半 10 導體晶片21埋於第一介電層20中，其中第一介電層2〇具有 一第一表面20a及相對之一第二表面2〇b，且第一線路層22 係嵌埋於第一表面20a。此外，於第一介電層2〇之第二表面 20b上’更可形成有一例如為銅箔之第二導體層2〇1。 如圖3D所示’移除承載板2，以外露第一線路層22。 15 接著’移除對應導接環22a之開孔220之黏著層23，並形成 與開孔220相連通之複數盲孔231以外露電極塾211，如圖3E • 所示。在此，係利用雷射鑽孔移除黏著層23。 為更清楚了解本實施例之導接環構造，囷3E’係為圖3E 之導接環示意圖。由圖3E’可明顯得知，本實施例之導接環 20 22a確實為一環狀結構，並可選擇性的與第一線路22b電性 連接。由於第一線路層22係為一金屬材質，因此利用雷射 鑽孔移除黏著層時，雷射光束在本身對位偏差範圍都落於 導接環22a之尺寸内且完全覆蓋開孔22〇，而能精準的移除 導接環22a之開孔220中之黏著層。同時，由於導接環223之 15 201029125 開孔220係對應於半導體晶片21之電極墊21][，且導接環22a 之開孔220面積係小於電極墊211面積，因此，當利用雷射 鑽孔方式移除開孔220内之黏著層以形成盲孔231時，可避 免雷射光束打在半導體晶片21電極墊211周緣外之作用面 5 21a 上。 接下來’如圖3F所示，同時於盲孔231中形成複數第一 導電盲孔221，各第一導電盲孔221之頂部222, 222，係與各 導接環22a相對應並填滿開孔220且延伸至導接環22a表 ► 面，其中部分第一導電盲孔221之頂部222係做為電性連接 10塾，且第一導電盲孔221係電性連接於電極墊211。因此， 所形成之嵌埋半導體晶片之封裝基板，其包括：一第一介 電層20’具有一第一表面2〇a及相對之一第二表面2〇b ; 一 半導體晶片21，係設於第一介電層2〇中，半導體晶片21具 有相對之一作用面21a與一非作用面21b，作用面21a具有複 15 數電極墊211，且作用面21 a係面向第一表面20a ; —黏著層 23 ’係位於半導體晶片21之作用面21a上並具有一第三表面 . 23a’且第三表面23a係外露於第一介電層2〇之第一表面 20a;複數具有開孔22〇之導接環22a，係嵌埋並外露於黏著 層23之一第三表面23a上且對應於各電極墊2U ;以及複數 20 第一導電盲孔221，係設於黏著層23中，各第一導電盲孔221 之頂部222, 222,係與各導接環22a相對應並填滿開孔220且 延伸至導接環22a表面，其中部分第一導電盲孔221之頂部 222係做為電性連接墊’又各該第一導電盲孔221之底部係 電性連接至各該電極墊211。此外，上述之嵌埋半導體晶片 16 201029125 之封裝基板更包括一第一線路22b，係嵌埋並外露於第一介 電層20之第一表面20a及黏著層23之第三表面23a，且第一 線路22b係電性連接至部分導接環22a。 接下來，如圖3F所示，於第一線路層22之第二表面20b 5 上形成一第二線路層24。其中，本實施例之嵌埋半導體晶 片之封裝基板可更包括導電通孔（圖中未示），其貫穿第一介 電層20以電性連接第一線路層22與第二線路層24。 而後，如圖3G所示，於第一線路層22及第一介電層20 p 之第一表面20a上形成一第一增層結構25a，並於第二線路 10 層24及第一介電層20之第二表面20b上形成一第二增層結 構25b。其中，第一及第二增層結構25a，25b分別包括至少 一第二介電層251、至少一設於第二介電層251上之第三線 路層253、及複數設於第二介電層251中且電性連接第三線 路層253之第二導電盲孔252，其中部分第二導電盲孔252係 15 電性連接至第一線路層22,部分第二導電盲孔252係電性連 接至第二線路層24,且另部分第二導電盲孔252係電性連接 至做為電性連接墊的第一導電盲孔221之頂部222，而最外 層之第三線路層253具有複數電性接觸墊254。 為更加清楚本實施例之電性連接墊與第一增層結構相 20 對關係，圖3G’係為第二導電盲孔252與做為電性連接墊的 第一導電盲孔221之頂部222電性連接之示意圖。如圖3G’ 所示，部份第一導電盲孔221之頂部222係做為電性連接 墊，其直徑約等於導接環22a之外徑。另部份第一導電盲孔 17 201029125 221之頂部222’ ’因無需與第二導電盲孔252電性連接，其 直徑係可小於導接環22a之外徑。 5 10 15 20 此外’如圖3H所示’於第一及第二增層結構25a, 25b 之表面上更分別形成一防焊層26a, 26b，且防焊層26a, 26b 具有複數防焊層開孔261以露出各電性接觸塾254。此外， 第一及第二增層結構25a，25b更包括一金屬保護層255，係 設於電性接觸墊254上。 為更加清楚了解本實施例之功效’圖4係為以雷射鑽孔 形成盲孔之示意圖。如圖4之示例所示，若以光徑l為80私 m之雷射光束進行鑽孔形成盲孔時，由於雷射光束之對位偏 差D為±15//m’因此雷射光束之光徑範圍l’為ii〇#m。當 半導趙晶片21之電極塾211尺寸W縮小至60/zm時，本實施 例之封裝基板及其製法’可先形成一外徑11為11〇#111之導 接環22a，且導接環22a之開孔220之孔徑R’係為50// m。在 此，導接環22a之外徑R係等於雷射光束之光徑範圍[，，因 此雷射光束在本身對位偏差範圍都落於導接環22a之尺寸 内且完全覆蓋開孔220。再者’導接環22a開孔220之孔徑R， 係小於電極墊211之寬度W，且開孔220係對應於電極墊 211 ’對於雷射光束之對位偏差士15απι之影響，導接環22a 可遮蔽其開孔220範圍以外的雷射光束，以讓開孔220範圍 以内的雷射光束通過，而能精準的移除開孔22〇中之黏著層 23並形成一對應於電極墊211尺寸W範圍内之盲孔231(如圖 3E及圖3E’所示）。因此’利用導接環22a及其開孔222，可 精準的控制雷射鑽孔所形成之盲孔，使盲孔能準確的對應 18 201029125 於電極墊2U尺寸範圍職。同時，因導接環m開孔22〇之 孔徑R’係小於電極塾211之寬度w，故不會因雷射鐵孔而破 壞到半導體晶片21電極墊211周緣外之作用面⑴。 因此，本實施例之封裝基板及其製法，可隨著半導體 5晶片電極塾之面積，調整雷射光束光徑、導接環外徑、及 導接環之開孔，而提升雷射鑽孔之精準度，進而提昇產品 之良率。 實施例2 I 請參考圖5A至圖5D，此為本實施例之嵌埋半導體晶片 10 之封裝結構之製作流程剖視圖。 如圖5A所示，首先，提供一承載板2，並於承載板2上 形成一第一線路層22，其中第一線路層22具有複數具有開 孔220之導接環22a。此外，第一線路層22更具有第一線路 22b，而承載板2更可具有一第一導體層23，且第一線路層 15 22係形成於該第一導體層2a上。 同時’如圊5A所示，提供一半導體晶片21，其具有相 I 對之一作用面21a及一非作用面21b，其中作用面21a具有複 數電極墊21卜且一黏著層23係形成於作用面21 a上。在此， 係利用印刷或貼合之方式，將樹脂形成在半導體晶片2之作 20 用面21a上，以形成黏著層23。 隨後，如圖5A所示，藉由黏著層23貼合承載板2與半 導體晶片21’其中半導體晶片21之作用面21a係面向承載板 2上之第一線路層22，各電極墊211係對應於各導接環22a之 19 201029125 * 開孔220,以使黏著層23位於第一線路層22與半導體晶片21 之作用面21a間並填入導接環22a之開孔220内。 接著，如圖5B所示，於承載板2及第一線路層22上形成 一第一介電層20,使黏著層23埋於第一介電層20中，其中 5 第一介電層20具有一第一表面20a及相對之一第二表面 20b ’且第一線路層22係欲埋於第一表面20a。 然後，於第一介電層20之一第二表面20b上層疊一具有 一開口 271之金屬板27，使半導體晶片21置於該開口 271 中，且於金屬板27之開口 271與半導體晶片21間之間隙中填 10 充一導熱材料28，該導熱材料28可以電鍍方式形成，或者 可以填入金屬膏方式形成。在此，導熱材料28並未覆蓋半 導艘晶片21之非作用面2lb ’以使金屬板27之第六表面27b 外露出來。 接著’如圖5C所示，移除承載板2及，以外露該第一線 15 路層22;而後，移除對應導接環22a之開孔220之黏著層23， 並形成與開孔220相連通之複數盲孔231以外露該電極塾 > 211。在此，係利用雷射鑽孔移除黏著層23。 如圖5D所示，於盲孔231中形成複數第一導電盲孔 221 ’各該第一導電盲孔221之頂部222,222,係與各該導接環 2〇 22a相對應並填滿開孔220且延伸至導接環22a表面，其中部 分該第一導電盲孔221之頂部係做為電性連接墊，又各該第 一導電盲孔221之底部係電性連接至各該電極墊2U。 因此，本實施例所形成之嵌埋半導體晶片之封裝基 板，其包括：一金屬板27,具有一第五表面27a及一第六表 20 201029125 面27b，其中金屬板27具有一開口271 ; 一半導體晶片21， 係設於開口 271中，半導體晶片21具有相對之一作用面21a 與一非作用面21b，且作用面21a與第五表面27a同側且具有 複數電極墊211 ; —導熱材料28,係填充於金屬板27之開孔 5 271與半導體晶片21間之間隙中；一第一介電層20,具有一 第一表面20a及相對之一第二表面20b，且第二表面20b係與 金屬板27之第五表面27a相結合；一黏著層23，係位於半導 體晶片21之作用面21a上並具有一第三表面23a，且第三表 面23a係外露於第一介電層20之第一表面20a ;複數具有開 10 孔220之導接環22a，係嵌埋並外露於黏著層23之一第三表 面23a上且對應於各電極墊211 ;以及複數第一導電盲孔 221，係設於黏著層23中，各第一導電盲孔221之頂部係與 各該導接環22a相對應並填滿開孔220且延伸至導接環22a 表面，其中部分第一導電盲孔221之頂部係做為電性連接塾 15 222,222’，又各第一導電盲孔221之底部係電性連接至各電 極墊211。 _ 在此’本實施例所形成之嵌埋半導體晶片之封裝基板 更包括一第一線路22b’係嵌埋並外露於第一介電層2〇之第 一表面20a及黏著層23之第三表面23a，且第一線路22b係電 2〇 性連接至部分導接環22a。同時’半導體晶片21之非作用面 21b係外露於金屬板27之第六表面27b » 接下來’如圖5D所示，更可於第一線路層22及第一介 電層20之第一表面20a上形成一第一增層結構25c。其中， 第一增層結構25 c係包括至少一第二介電層251、至少一設 21 201029125 於第二介電層251上之第三線路層253、及複數設於第二介 電層251中且電性連接第三線路層253之第二導電盲孔 252 ’其中部分第二導電盲孔252係電性連接至第一線路 22b，且另部分第二導電盲孔252係電性連接至電性連接墊 5 222，而最外層之第三線路層253具有複數電性接觸墊254。 此外’如圖5D所示，於該第一增層結構25c之表面上更 可形成一防焊層26,且防焊層26具有複數防焊層開孔261以 露出該電性接觸墊254。同時，第一增層結構25c可更包括 一設於電性接觸墊254上之金屬保護層255。 10 實施例3 本實施例之嵌埋半導體晶片之封裝基板及其製法，係 與實施例2相同’除了半導體晶片21之厚度係小於金屬板27 之厚度’而導熱材料28更覆蓋半導體晶片21之非作用面 21b ’且導熱材料28係外露於金屬板27之第六表面27b，如 15 圖6A所示。 實施例4 丨 本實施例之嵌埋半導體晶片之封裝基板及其製法，係 與實施例2相同，除了導熱材料28更覆蓋半導體晶片21之非 作用面2lb與金屬板27之第六表面27b，如圊6B所示。 20 實施例5 本實施例之嵌埋半導體晶片之封裝基板及其製法，係 與實施例2相同，除了半導體晶片21之厚度係小於金屬板27 之厚度，且導熱材料28更覆蓋半導體晶片21之非作用面21b 與金屬板27之第六表面27b，如圖6C所示。 22 201029125 綜上所述，本發明之嵌埋半導體晶片之封裝基板及其 製法，先利用黏著層將半導體晶片與承載板上之^路層對 準並固定’不需經過將半導體晶片先精準置入並固定於一 承載板之貫穿開口的步驟，故免除半導體晶片放 5板開口中定位之偏差，可增加後續製程之精準度。 本發明之嵌埋半導體晶片之封裝基板及其製法^係利用導 接環以限制雷射光束鑽孔之區域，可防止雷射光束打在半 導體晶片電極墊周緣外之作用面上所造成之半導體晶片損 • 壞。尤其當半導體晶片電極墊縮小時，因雷射光束之對^ 10偏差，更容易造成產品良率降低。因此，相較於習知嵌埋 半導艘晶片之封裝基板之製法’本發明可提升半導艘晶片 與扇出（fan out)線路之對位精準度。同時，藉由形成一導接 環以限制雷射鑽孔之區域’而可增加雷射鑽孔之精準产， 進而提升產品良率。 & 15 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 20 圖1Α至圖1D係習知之嵌埋半導體晶片之封裝結構之製作 流程剖視圖。 圖2Α及圖2Β係習知以雷射形成盲孔之示意圖。 圖3Α至圖3Η係本發明實施例1之嵌埋半導體晶片之封裝结 構之製作流程剖視圖。 23 201029125 圖4係本發明實施例1之以雷射形成盲孔之示意圖。 圖5 A至圖5D係本發明實施例2之嵌埋半導體晶片之封裝衾士 構之製作流程剖視圖。 ~ 圖6A係本發明實施例3之嵌埋半導體晶片之封裝結構立 視圖。 "剖 之封装·結構之剖 圖6B係本發明實施例4之嵌埋半導趙晶片 視囷。 10 係本發明實施例3之嵌埋半導趙晶片之封裝結構之剖 【主要元件符號說明】 1 第一承載板 101 貫穿開口 111 電極墊 121 盲孔 131 導電盲孔 2a 第一導體層 20a 第一表面 201 第二導體層 21a 作用面 211 電極墊 22a 導接環 220 開孔 222, 222' 導電盲孔頂部 10 第一承載板 11 半導馥晶片 12 第一介電層 13 第一線路 2 承栽板 20 第—介電層 20b 第二表面 21 半導艘晶片 21b 非作用面 22 第一線路層 22b 第一線路 221 第一導電盲 23 黏著層201029125 f VI. Description of the Invention: [Technical Field] The present invention relates to a package substrate embedded with a semiconductor wafer and a system therefor. The method, in particular, can prevent the laser from opening when the semiconductor wafer electrode pad is shrunk. A package substrate for embedding a semiconductor wafer in which the hole is misaligned to cause wafer damage and a method of manufacturing the same. [Prior Art] ® With the booming electronics industry, electronic products are gradually entering the direction of multi-functional and high-performance research and development. In order to meet the high integration and miniaturization packaging requirements of semiconductor packages, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. In space, the area of the available wiring on the board is expanded by the interlayer connection technology to meet the requirements of the integrated circuit of high electron density. The general semiconductor device process is first developed by a wafer carrier manufacturer to produce a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. The wafer carriers are then placed in a packaging process by a semiconductor packager for crystallization, wire bonding, encapsulation, and ball placement. In a general semiconductor package, the back surface of the semiconductor chip is bonded to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor chip is bonded to the package substrate by flip chip bonding, and then the substrate is bonded to the substrate. The back side is implanted with solder balls for electrical connection with other electronic devices. 4 201029125 With the development of technology, many recent studies have developed a method in which semiconductor wafers are embedded in a substrate, and a larger number of lines and semiconductor wafers are accommodated in the same package unit volume to meet the demand for light and thin electronic products. In the current technology of embedding a wafer in a substrate, the wafer is embedded in the base 5, and the layers are simultaneously layered on the surface of the wafer and the substrate, and the interlayer electrical connection structure (interlayer) formed by the layered wiring layer and the conductive via hole is formed. Electrical connecting structure) Fan out the electrode pads of the semiconductor wafer. Please refer to FIG. 1A to FIG. 1D, which is a cross-sectional view showing the manufacturing process of a conventional sealed semiconductor wafer package. First, as shown in FIG. 1A, a first carrier board 1 is provided, and a second carrier board 1 is formed on the first carrier board 1, wherein the second carrier board has a through opening ιοί. Next, a semiconductor wafer 11' is provided and placed in the through opening 101 of the second carrier 10, wherein the semiconductor wafer 11 has a plurality of electrode pads 111 as shown in Fig. 1B. Then, a first dielectric layer 12 is formed by heat pressing on the 15 semiconductor wafer and the second carrier 10 as shown in Fig. 1C. Finally, a plurality of blind holes 121 are formed in the first dielectric layer 12 by lasers, and conductive blind holes 131 and first lines 13 are formed in the blind holes 121 and the first dielectric layer 12 to be electrically connected. The electrode pad 111' of the semiconductor wafer is shown in Fig. 1D. 20 Next, please refer to FIG. 2A and FIG. 2B , which are schematic diagrams of forming blind holes by laser. In the example shown in FIG. 2A, the width w of the conventional electrode 塾hi is 100 Å and the minimum optical path of the current laser beam is 60 ym, wherein the laser beam has a pair of ±15#m. The bit deviation is D, so the optical path of the laser beam will be in the range of 90 " m. Therefore, in the case where the width w of the electrode pad 111 is 5 201029125 ψ 100 /ζ m, if a laser beam having an optical path L of 60 / ζ m is used, even if the alignment is not accurate, the laser beam is still on the electrode pad. 111 does not damage the surface of the semiconductor wafer 11. In response to the demand for thin and light electronic products, the size of the semiconductor wafer 5 has also been reduced, resulting in a relatively small surface area of the electrode. In the example shown in FIG. 2B, when the width W of the electrode 塾111 is reduced to 80 m, since the minimum optical path L of the current laser beam is 60 ym and has a registration deviation D of ±15 private m, therefore, In the case where the alignment is not precise enough, the laser beam is caused to hit the surface outside the periphery of the electrode ill of the semiconductor wafer 11, and 10 damages the surface of the semiconductor wafer 11, resulting in a decrease in product yield. In summary, the conventional package substrate for embedding a semiconductor wafer is obtained by first placing a semiconductor wafer into an open substrate and drilling with a laser. However, since the semiconductor wafer is placed and fixed to the opening of the substrate, there may be a misalignment of the substrate, which reduces the alignment accuracy of subsequent processes. At the same time, as the electronic products gradually become more and more miniaturized, the electrode pads on the semiconductor wafers also shrink. However, there are still limits to the size of the laser beam in the process, and the laser beam itself has a misalignment. Therefore, when the electrode pad of the semiconductor wafer is shrunk, the package substrate in which the semiconductor wafer is embedded is conventionally fabricated, and the laser beam may be generated outside the periphery of the electrode and the semiconductor wafer may be destroyed, resulting in a decrease in yield β. Currently, there is an urgent need to develop a package substrate structure and a method for manufacturing the same that can improve the above problems or disadvantages, so as to avoid damage to the semiconductor wafer caused by laser beam hitting the outer surface of the periphery of the electrode pad of the semiconductor wafer due to misalignment. 6 201029125 SUMMARY OF THE INVENTION A primary object of the present invention is to provide a package substrate in which a semiconductor wafer is embedded, which utilizes a via ring to prevent the laser opening from damaging the surface of the semiconductor wafer, resulting in a decrease in yield. 5 Another object of the present invention is to provide a package substrate for a buried semiconductor wafer, in which the semiconductor wafer and the carrier are fixed before the dielectric layer and formed before the laser opening - Guide ring to improve the accuracy of the laser iron hole. ^ 喾 I achieve the above object, the first embodiment of the present invention provides a package substrate for semiconductor wafers, comprising: a first dielectric layer having a first surface and opposite - a second surface semiconductor The wafer is disposed in the first dielectric layer, the semiconductor wafer has a relative active surface and a non-active®, the function has a plurality of electrodes, and the active surface faces the first surface; an adhesive layer Is located on the active surface 15 of the semiconductor wafer and has a third surface, and the third surface is exposed on the first surface of the first dielectric layer; a plurality of conductive rings with open holes are embedded And being exposed on the third surface of the adhesive layer and corresponding to each of the electrode pads; and the plurality of first conductive blind holes are disposed in the adhesive layer, and the tops of the first conductive blind holes are respectively The guiding ring is corresponding to the filling hole and extends to the surface of the guiding ring 20, wherein a part of the first conductive blind hole is used as an electrical connection pad, and the bottom of each of the first conductive blind holes is electrically connected. Connected to each of the electrode pads. In addition, a second embodiment of the present invention provides a package substrate embedded with a semiconductor wafer, comprising: a metal plate having a fifth surface and a sixth surface, wherein the metal plate has an opening; a semiconductor wafer, The system 7 is disposed in the opening, the semiconductor wafer has a pair of active surfaces and a non-active surface, and the active surface is on the same side of the fifth surface and has a plurality of electrode pads, and a heat conductive material is filled in the a gap between the opening of the metal plate and the semiconductor wafer; a first dielectric layer having a first surface and a second surface opposite to the fifth surface, and the second surface and the fifth surface of the metal plate The surface is combined; an adhesive layer is disposed on the active surface of the semiconductor wafer and has a third surface, and the third surface is exposed on the first surface of the first dielectric layer; the plurality of openings have openings a conductive ring embedded and exposed on the second surface of the layer t corresponding to each of the electrodes; and a plurality of 10th conductive blind holes disposed in the adhesive layer, each of the first conductive Top of the blind hole Corresponding to each of the guiding rings and filling the opening and extending to the surface of the guiding ring, wherein a part of the first conductive blind hole is used as an electrical connection pad, and the bottom of each of the first conductive blind holes Electrically connected to each of the electrode pads. In the package substrate of the second embodiment of the present invention, the non-active surface of the semiconductor wafer 15 may be exposed on the sixth surface of the metal plate. Alternatively, the thickness of the semi-conductive sa sheet may be less than the thickness of the metal plate, the thermally conductive material further covering the non-active surface of the semiconductor wafer, and the thermally conductive material is exposed on the sixth surface of the metal plate. Alternatively, the thermally conductive material may cover the non-active surface of the semiconductor wafer and the sixth surface of the metal plate. The package substrate of the first or second embodiment of the present invention further includes a first line embedded and exposed on the first surface of the first dielectric layer and the third surface of the adhesive layer, and The first line is electrically connected to a portion of the lead ring. 8 201029125 t The package substrate of the first or second embodiment of the present invention may further include a first build-up structure disposed on the first surface of the first line and the first dielectric layer. The first build-up structure includes at least one second dielectric layer, at least one third circuit layer disposed on the second dielectric layer, and a plurality of the second dielectric layers disposed in the second dielectric layer and electrically connected to the first a second conductive blind via of the three-layer layer, wherein a portion of the second conductive via is electrically connected to the first trace, and another portion of the second conductive via is electrically connected to the electrical connection pad, and the outermost layer The second circuit layer has a plurality of electrical contacts. In addition, the package base plate may further include a solder resist layer disposed on the surface of the first build-up structure, and 10 the solder resist layer has a plurality of solder mask openings to expose the respective electrical contact pads. In the package substrate of the first embodiment of the present invention, the second surface of the first dielectric layer is provided with a second circuit layer. In addition, the package substrate may further include a second build-up structure disposed on the second surface of the second circuit layer and the first dielectric layer, the second build-up structure comprising at least 15 a second dielectric layer, at least one third wiring layer disposed on the second dielectric layer, and a plurality of second conductive blind vias disposed in the second dielectric layer and electrically connected to the third wiring layer φ A portion of the second conductive via is electrically connected to the second circuit layer 'and the third circuit layer of the outermost layer has a plurality of electrical contact pads. Meanwhile, the package substrate may further include a solder resist layer disposed on a surface of the second 20 build-up structure, and the solder resist layer has a plurality of solder resist openings to expose the respective electrical contact pads. In the above package substrate, the material of the adhesive layer may be a resin. In addition to the above-mentioned package substrate for embedding a semiconductor wafer, the present invention further provides a method for fabricating the same. 9 201029125 The invention provides a package substrate embedded with a semiconductor wafer, and provides a carrier board on which a circuit layer is formed, wherein the first circuit layer has a plurality of openings a ring of holes, (Β) providing a half-guided wafer having a relative active surface and a non-active surface 'having a plurality of electrodes on the active surface and an adhesive layer formed on the active surface; (6) The adhesive layer is attached to the carrier and the semiconductor wafer, wherein the active surface of the semiconductor wafer faces the first circuit layer on the carrier board, and each of the electrodes corresponds to each of the conductive contacts. Opening the hole so that the adhesive layer is located between the first circuit layer and the active surface of the semiconductor crystal 10 > 1 and filled into the opening of the conductive ring; (D) the carrier board, the Forming a first dielectric layer on the first circuit layer and the non-active surface of the semiconductor wafer, wherein the semiconductor wafer is buried in the first dielectric layer, wherein the first dielectric layer has a first surface and opposite sides a second surface and the first circuit layer is embedded in the first surface (Ε) removing the carrier plate to expose the first circuit layer; (F) removing the adhesive layer corresponding to the opening of the conductive ring, and forming a plurality of blind holes communicating with the opening to expose the electrode pad Forming a plurality of first conductive blind vias in the φ and the blind vias, the tops of the first conductive vias corresponding to the respective via loops and filling the openings and extending to the surface of the via ring, wherein a portion thereof The top of the first conductive via is electrically connected to the pad, and the bottom of each of the first conductive vias is electrically connected to each of the electrode pads. Wherein, after the step (G), a second circuit layer is formed on the second surface of the first circuit layer. In addition, after the step (G), the above method may further comprise a step (H) of forming a first build-up structure on the first surface layer and the first surface of the first dielectric layer. Meanwhile, after the step (G), the above method of 201029125 may further include a step (Η): forming a second build-up structure on the second circuit layer and the second surface of the first dielectric layer. The first build-up structure and the second build-up structure respectively include at least one second dielectric layer, at least one third circuit layer disposed on the second dielectric layer, and a plurality of the fifth layer a second conductive via hole electrically connected to the third circuit layer, wherein the second conductive blind via is electrically connected to the first circuit layer, and the second conductive blind via is electrically connected The second circuit layer 253 is electrically connected to the second connection layer, and the other second conductive layer 253 is electrically connected to the electrical connection pad 222, and the third circuit layer 253 of the outermost layer has a plurality of electrical contact pads 254. 10 In the above method, a solder resist layer is further formed on the surfaces of the first and second build-up structures, and the anti-corrugation layer has a plurality of solder mask openings to expose the respective electrical contact pads. In addition, the present invention further provides a method for fabricating a package substrate for embedding a semiconductor wafer, comprising: a method for manufacturing a package substrate embedded with a semiconductor wafer, comprising: providing a carrier board on the carrier board Forming a first circuit layer thereon, wherein the first circuit layer has a plurality of conductive contacts having an opening; (Β) providing a half guiding wafer having a relative one of a working surface and a non-active surface The active surface has a plurality of electrode pads, and an adhesive layer is formed on the active surface; (C) the carrier layer and the two semiconductor wafers are bonded by the adhesive layer, wherein the active surface of the semiconductor wafer faces the The first circuit layer on the carrier board, each of the electrode pads corresponding to the opening of each of the conductive rings such that the adhesive layer is located between the first circuit layer and the active surface of the semiconductor wafer and filled in (D) forming a first dielectric layer on the carrier and the circuit layer, and embedding the adhesive layer in the dielectric layer of the 201029125, wherein the first dielectric layer has a first surface and a relative one a surface, and the first circuit layer is embedded in the first surface; (E) laminating a metal plate having an opening on a second surface of the first dielectric layer, the semiconductor wafer is placed in the opening And a thermally conductive material is filled in the gap between the opening of the metal plate and the semiconductor wafer; (F) removing the carrier plate to expose the first circuit layer; removing the opening of the corresponding guiding ring The adhesive layer of the hole 'and forming a plurality of blind holes communicating with the opening to expose the electrode pad; and (H) forming a plurality of first conductive blind holes in the blind hole, the top of each of the first conductive holes Corresponding to each of the guiding rings and filling the opening 10 and extending the surface of the guiding ring, the top portion of the first conductive blind hole is used as an electrical connection pad, and each of the first conductive blind holes The bottom is electrically connected to each of the electrodes. In the step (E) of the above process, the non-active surface of the semiconductor wafer may be exposed on a sixth surface of the metal plate. Alternatively, the semiconducting wafer may have a thickness of 15 degrees less than the thickness of the metal plate, the thermally conductive material further covering the inactive surface of the semiconductor wafer, and the thermally conductive material exposes a sixth surface of the metal plate. The heat conductive material may cover the non-functional surface of the semiconductor wafer and a sixth surface of the metal plate. In addition, after the step (G), the method further includes a step (I) of forming a first build-up structure on the first surface of the first circuit layer and the first dielectric layer. The first build-up structure includes at least one second dielectric layer, at least one of the third circuit layers on the second dielectric layer, and a plurality of the second dielectric layers disposed in the second dielectric layer and electrically connected to the first a hole of the three-layer layer, wherein a portion of the second conductive blind via is electrically connected to the first line, 12 201029125 and another portion of the second conductive blind via is electrically connected to the electrical connection pad, and the outermost layer The three circuit layers have a plurality of electrical contact pads. At the same time, a solder resist layer may be further formed on the surface of the first build-up structure, and the solder resist layer has a plurality of solder mask openings to expose the electrical contact pads. 5 In the above two methods of packaging a semiconductor chip embedded with a semiconductor chip, the carrier board may further have a first conductor layer, and the first circuit layer is formed on the first conductor layer. Further, the material of the adhesive layer is a resin. Since the package substrate of the embedded semiconductor wafer of the present invention is prepared, the semiconductor wafer and the carrier plate are combined before the dielectric lamination to improve the accuracy of the subsequent process. Compared with the conventional manufacturing method, the semiconductor wafer is first placed in the opened substrate 'pressed dielectric layer, and then the laser drilling is performed. The present invention can solve the alignment deviation when the semiconductor wafer is placed in the opening of the substrate. The problem. In addition, due to the miniaturization demand, the electrode on the semiconductor wafer is shrunk by 15 small. Therefore, when the package substrate embedded with the semiconductor wafer is fabricated by a conventional method, the laser beam may be destroyed due to the alignment deviation of the laser beam itself. The case of a semiconductor wafer. However, the package substrate using the embedded semiconductor wafer of the present invention and the method of manufacturing the same, which pass through the via ring to control the laser beam, will only strike the electrode pad without hitting the outer surface of the periphery of the electrode pad of the semiconductor wafer. 20 Therefore, even if the electrode pad is shrunk, the laser drilling area can be controlled through the guiding ring to prevent the laser beam from damaging the surface of the semiconductor wafer to improve the yield of the product. [Embodiment] 13 201029125 The following is a description of the embodiments of the present invention by way of specific examples, and those skilled in the art can readily understand other advantages and advantages of the present invention from the disclosure. The present invention may be embodied or applied in various other specific embodiments, and the details of the present invention may be variously modified and changed without departing from the spirit and scope of the invention. Embodiment 1 Please refer to FIG. 3A to FIG. 3H, which are cross-sectional views showing the manufacturing process of the package structure of the embedded semiconductor wafer of the present embodiment. As shown in Fig. 3A, first, a carrier board 2 is provided, and a first wiring layer 22 is formed on the carrier board 2, wherein the first circuit layer 22 has a plurality of guiding rings 22a having openings 220. At the same time, the first circuit layer 22 further has a first line 22b. Further, as shown in FIG. 3A, the carrier board 2 may further have a first conductor layer 15 2a' and the first circuit layer 22 is formed on the first conductor layer. 2& The material of the carrier plate 2 is an insulating material, and the first conductor layer may be a metal layer, such as a copper foil. Therefore, the first wiring layer 22 can be plated to form the first wiring layer 22 on the carrier board 2 by this first conductor layer 2a. Next, as shown in FIG. 3A, a semiconductor wafer 21 having a pair of active surfaces 21a and a non-active surface 21b is provided, wherein the active surface 21a has a plurality of electrodes 211' and an adhesive layer 23 is formed. On face 21a. Here, the resin is formed on the surface 21a of the semiconductor wafer 2 by printing or lamination to form the adhesive layer 23. 14 201029125 Subsequently, as shown in FIG. 3B, the carrier layer 2 and the semiconductor wafer 21' are bonded by the adhesive layer 23, wherein the active surface 21a of the semiconductor wafer 21 faces the first wiring layer 22 on the carrier board 2, and the electrode pads are respectively The 211 is corresponding to the opening 220 of each of the guiding rings 22 & so that the adhesive layer 23 is located between the first wiring layer 22 and the active surface 21a of the semiconductor wafer 215 and is filled in the opening 220 of the guiding ring 22a. Thus, the first wiring layer 22 is aligned with the electrode pad 211, and the semiconductor wafer 21 can be fixed to the first wiring layer 22 on the carrier board 2 through the adhesive layer 23. . Next, as shown in FIG. 3C, a first dielectric layer 2 is formed on the carrier layer 2, the first wiring layer 22, and the non-active surface 21b of the germanium semiconductor wafer 21, so that the half-10 conductor wafer 21 is buried. In a dielectric layer 20, the first dielectric layer 2 has a first surface 20a and a second surface 2〇b, and the first circuit layer 22 is embedded in the first surface 20a. Further, a second conductor layer 2?, such as a copper foil, may be formed on the second surface 20b of the first dielectric layer 2'. The carrier board 2 is removed as shown in Fig. 3D, and the first wiring layer 22 is exposed. 15 Next, the adhesive layer 23 of the opening 220 of the corresponding guiding ring 22a is removed, and a plurality of blind holes 231 are formed in contact with the opening 220 to expose the electrode 211, as shown in Fig. 3E. Here, the adhesive layer 23 is removed by laser drilling. To better understand the construction of the junction ring of this embodiment, the 囷3E' is a schematic diagram of the junction ring of FIG. 3E. As is apparent from Fig. 3E', the junction ring 20 22a of the present embodiment is indeed a ring structure and can be selectively electrically connected to the first line 22b. Since the first circuit layer 22 is made of a metal material, when the adhesive layer is removed by laser drilling, the laser beam falls within the size of the guiding ring 22a and completely covers the opening 22 in the range of the self-alignment deviation. The adhesive layer in the opening 220 of the guiding ring 22a can be accurately removed. At the same time, since the opening 22 of the guiding ring 223 201029125 corresponds to the electrode pad 21] of the semiconductor wafer 21, and the area of the opening 220 of the guiding ring 22a is smaller than the area of the electrode pad 211, when using a laser drill When the adhesive layer in the opening 220 is removed by the hole to form the blind hole 231, the laser beam can be prevented from hitting the active surface 5 21a outside the periphery of the electrode pad 211 of the semiconductor wafer 21. Next, as shown in FIG. 3F, a plurality of first conductive blind vias 221 are formed in the blind vias 231, and the tops 222, 222 of the first conductive vias 221 are corresponding to the respective via loops 22a and are filled. The hole 220 extends to the surface of the lead ring 22a. The top portion 222 of the first conductive blind hole 221 is electrically connected to the top surface 222, and the first conductive blind hole 221 is electrically connected to the electrode pad 211. Therefore, the package substrate for embedding the semiconductor wafer comprises: a first dielectric layer 20' having a first surface 2a and a second surface 2?b; a semiconductor wafer 21; In the first dielectric layer 2, the semiconductor wafer 21 has a pair of active surfaces 21a and a non-active surface 21b, the active surface 21a has a plurality of electrode pads 211, and the active surface 21a faces the first surface 20a; The adhesive layer 23' is located on the active surface 21a of the semiconductor wafer 21 and has a third surface. 23a' and the third surface 23a is exposed on the first surface 20a of the first dielectric layer 2A; the plurality of conductive rings 22a having the opening 22 is embedded and exposed on the third surface 23a of the adhesive layer 23. And corresponding to each of the electrode pads 2U; and the plurality of first conductive blind holes 221 are disposed in the adhesive layer 23, and the tops 222, 222 of the first conductive blind holes 221 correspond to the respective conductive rings 22a. Filling the opening 220 and extending to the surface of the guiding ring 22a, wherein the top 222 of the first conductive blind hole 221 is used as an electrical connection pad, and the bottom of each of the first conductive blind holes 221 is electrically connected to each The electrode pad 211. In addition, the package substrate of the embedded semiconductor wafer 16 201029125 further includes a first line 22b embedded in the first surface 20a of the first dielectric layer 20 and the third surface 23a of the adhesive layer 23, and A line 22b is electrically connected to the partial lead ring 22a. Next, as shown in FIG. 3F, a second wiring layer 24 is formed on the second surface 20b 5 of the first wiring layer 22. The package substrate of the semiconductor wafer embedded in the embodiment may further include a conductive via (not shown) extending through the first dielectric layer 20 to electrically connect the first circuit layer 22 and the second circuit layer 24. Then, as shown in FIG. 3G, a first build-up structure 25a is formed on the first surface 2022 and the first surface 20a of the first dielectric layer 20p, and the second trace 10 layer 24 and the first dielectric A second build-up structure 25b is formed on the second surface 20b of the layer 20. The first and second build-up structures 25a, 25b respectively include at least one second dielectric layer 251, at least one third circuit layer 253 disposed on the second dielectric layer 251, and a plurality of second dielectric layers. The second conductive via 252 is electrically connected to the second conductive layer 253, wherein a portion of the second conductive via 252 is electrically connected to the first circuit layer 22, and a portion of the second conductive via 252 is electrically connected. Connected to the second circuit layer 24, and another portion of the second conductive via 252 is electrically connected to the top 222 of the first conductive via 221 as an electrical connection pad, and the third circuit layer 253 of the outermost layer has a plurality Electrical contact pads 254. To further clarify the relationship between the electrical connection pads of the present embodiment and the first build-up structure, FIG. 3G′ is the second conductive blind via 252 and the top 222 of the first conductive blind via 221 as an electrical connection pad. Schematic diagram of electrical connections. As shown in Fig. 3G', the top portion 222 of the portion of the first conductive via 221 is used as an electrical connection pad having a diameter approximately equal to the outer diameter of the via ring 22a. The top portion 222' of the first conductive blind via 17 201029125 221 is smaller than the outer diameter of the via loop 22a because it does not need to be electrically connected to the second conductive via 252. 5 10 15 20 Further, as shown in FIG. 3H, a solder resist layer 26a, 26b is formed on the surfaces of the first and second build-up structures 25a, 25b, respectively, and the solder resist layers 26a, 26b have a plurality of solder resist layers. The opening 261 is exposed to expose the respective electrical contacts 254. In addition, the first and second build-up structures 25a, 25b further include a metal protective layer 255 disposed on the electrical contact pads 254. To better understand the effect of the present embodiment, Fig. 4 is a schematic view showing the formation of blind holes by laser drilling. As shown in the example of FIG. 4, if a laser beam with a light path of l is 80 m is drilled to form a blind hole, since the alignment D of the laser beam is ±15//m', the laser beam is The optical path range l' is ii〇#m. When the size W W of the semiconductor wafer 211 of the semiconductor wafer 21 is reduced to 60/zm, the package substrate of the present embodiment and the method for manufacturing the same can form a lead ring 22a having an outer diameter 11 of 11 〇 #111, and the guiding The aperture R' of the opening 220 of the ring 22a is 50/m. Here, the outer diameter R of the guiding ring 22a is equal to the optical path range of the laser beam [, so that the laser beam falls within the size of the guiding ring 22a in its own alignment deviation range and completely covers the opening 220. Furthermore, the aperture R of the opening 220 of the conductive ring 22a is smaller than the width W of the electrode pad 211, and the opening 220 corresponds to the influence of the electrode pad 211 'for the offset of the laser beam 15απι, the guiding ring 22a can shield the laser beam outside the range of the opening 220 to pass the laser beam within the range of the opening 220, and can accurately remove the adhesive layer 23 in the opening 22 and form a corresponding electrode pad 211. Blind holes 231 in the size W range (as shown in Figures 3E and 3E'). Therefore, by using the guiding ring 22a and its opening 222, the blind hole formed by the laser drilling can be precisely controlled, so that the blind hole can accurately correspond to the size range of the electrode pad 2U. At the same time, since the aperture R' of the opening 22 of the terminal ring m is smaller than the width w of the electrode 211, the action surface (1) outside the periphery of the electrode pad 211 of the semiconductor wafer 21 is not broken by the laser hole. Therefore, the package substrate of the embodiment and the method for manufacturing the same can adjust the laser beam diameter, the outer diameter of the guide ring, and the opening of the lead ring according to the area of the electrode of the semiconductor 5 wafer, thereby improving the laser drilling The precision, which in turn increases the yield of the product. Embodiment 2 I Please refer to FIG. 5A to FIG. 5D, which are cross-sectional views showing the manufacturing process of the package structure of the embedded semiconductor wafer 10 of the present embodiment. As shown in Fig. 5A, first, a carrier board 2 is provided, and a first circuit layer 22 is formed on the carrier board 2, wherein the first circuit layer 22 has a plurality of guiding rings 22a having openings 220. In addition, the first circuit layer 22 further has a first line 22b, and the carrier board 2 further has a first conductor layer 23, and the first circuit layer 1522 is formed on the first conductor layer 2a. Meanwhile, as shown in FIG. 5A, a semiconductor wafer 21 having a pair of active surface 21a and a non-active surface 21b is provided, wherein the active surface 21a has a plurality of electrode pads 21 and an adhesive layer 23 is formed. Face 21 a. Here, the resin is formed on the surface 21a of the semiconductor wafer 2 by printing or lamination to form the adhesive layer 23. Subsequently, as shown in FIG. 5A, the carrier layer 2 and the semiconductor wafer 21' are bonded together by the adhesive layer 23, wherein the active surface 21a of the semiconductor wafer 21 faces the first wiring layer 22 on the carrier board 2, and the electrode pads 211 correspond to each other. 19 201029125* of each of the guiding rings 22a is opened, so that the adhesive layer 23 is located between the first wiring layer 22 and the active surface 21a of the semiconductor wafer 21 and filled into the opening 220 of the guiding ring 22a. Next, as shown in FIG. 5B, a first dielectric layer 20 is formed on the carrier layer 2 and the first circuit layer 22, so that the adhesive layer 23 is buried in the first dielectric layer 20, wherein the first dielectric layer 20 is There is a first surface 20a and a second surface 20b' opposite to each other and the first circuit layer 22 is intended to be buried on the first surface 20a. Then, a metal plate 27 having an opening 271 is stacked on the second surface 20b of the first dielectric layer 20, and the semiconductor wafer 21 is placed in the opening 271, and the opening 271 of the metal plate 27 and the semiconductor wafer 21 are formed. The gap between the gaps is filled with a heat conductive material 28, which may be formed by electroplating or may be formed by filling a metal paste. Here, the thermally conductive material 28 does not cover the inactive surface 2lb' of the semiconductor wafer 21 to expose the sixth surface 27b of the metal plate 27. Then, as shown in FIG. 5C, the carrier board 2 is removed and the first line 15 layer 22 is exposed; then, the adhesive layer 23 of the opening 220 of the corresponding guiding ring 22a is removed, and the opening 220 is formed and formed. The plurality of blind vias 231 that are in communication are exposed to the electrode 塾 > 211. Here, the adhesive layer 23 is removed by laser drilling. As shown in FIG. 5D, a plurality of first conductive blind vias 221' are formed in the blind vias 221, and the tops 222, 222 of the first conductive vias 221 are corresponding to the respective via loops 22 and 22a and fill the vias 220. The bottom of the first conductive via 221 is electrically connected to the electrode pad 2U. The bottom of each of the first conductive vias 221 is electrically connected to each of the electrode pads 2U. Therefore, the package substrate of the embedded semiconductor wafer formed in this embodiment includes: a metal plate 27 having a fifth surface 27a and a sixth surface 20 201029125 surface 27b, wherein the metal plate 27 has an opening 271; The semiconductor wafer 21 is disposed in the opening 271. The semiconductor wafer 21 has a pair of active surfaces 21a and a non-active surface 21b, and the active surface 21a is on the same side as the fifth surface 27a and has a plurality of electrode pads 211. Filled in the gap between the opening 5 271 of the metal plate 27 and the semiconductor wafer 21; a first dielectric layer 20 having a first surface 20a and a second surface 20b opposite thereto, and the second surface 20b is The fifth surface 27a of the metal plate 27 is combined; an adhesive layer 23 is disposed on the active surface 21a of the semiconductor wafer 21 and has a third surface 23a, and the third surface 23a is exposed to the first dielectric layer 20. The first surface 20a; the plurality of conductive rings 22a having the opening 10 holes 220 are embedded and exposed on one of the third surfaces 23a of the adhesive layer 23 and corresponding to the electrode pads 211; and the plurality of first conductive blind holes 221, The system is disposed in the adhesive layer 23, and each of the first conductive blinds The top of the hole 221 corresponds to each of the guiding rings 22a and fills the opening 220 and extends to the surface of the guiding ring 22a. The top of the portion of the first conductive blind hole 221 is electrically connected to the 塾15 222, 222'. Further, the bottom of each of the first conductive blind vias 221 is electrically connected to each of the electrode pads 211. The package substrate of the embedded semiconductor wafer formed by the present embodiment further includes a first line 22b' embedded and exposed on the first surface 20a of the first dielectric layer 2 and the third layer of the adhesive layer 23. The surface 23a, and the first line 22b is electrically connected to the partial lead ring 22a. At the same time, the non-active surface 21b of the semiconductor wafer 21 is exposed on the sixth surface 27b of the metal plate 27. Next, as shown in FIG. 5D, the first surface layer 22 and the first surface of the first dielectric layer 20 are further provided. A first build-up structure 25c is formed on 20a. The first build-up structure 25 c includes at least one second dielectric layer 251 , at least one third circuit layer 253 on which the 21 201029125 is disposed on the second dielectric layer 251 , and a plurality of second dielectric layers 251 . The second conductive via 252 ′ is electrically connected to the first conductive via 252 ′, wherein a portion of the second conductive via 252 is electrically connected to the first line 22 b , and another portion of the second conductive via 252 is electrically connected to The electrical connection pads 5 222, while the outermost third circuit layer 253 has a plurality of electrical contact pads 254. Further, as shown in FIG. 5D, a solder resist layer 26 is further formed on the surface of the first build-up structure 25c, and the solder resist layer 26 has a plurality of solder resist openings 261 to expose the electrical contact pads 254. At the same time, the first build-up structure 25c may further include a metal protection layer 255 disposed on the electrical contact pads 254. 10 Embodiment 3 The package substrate for embedding a semiconductor wafer of the present embodiment and the method for manufacturing the same are the same as in Embodiment 2, except that the thickness of the semiconductor wafer 21 is smaller than the thickness of the metal plate 27, and the heat conductive material 28 covers the semiconductor wafer 21. The non-active surface 21b' and the thermally conductive material 28 are exposed to the sixth surface 27b of the metal plate 27 as shown in Fig. 6A. Embodiment 4 The package substrate of the embedded semiconductor wafer of the present embodiment and the method for manufacturing the same are the same as Embodiment 2 except that the heat conductive material 28 covers the non-active surface 21b of the semiconductor wafer 21 and the sixth surface 27b of the metal plate 27, As shown in Figure 6B. 20 Embodiment 5 The package substrate for embedding a semiconductor wafer of the present embodiment and the method for manufacturing the same are the same as Embodiment 2 except that the thickness of the semiconductor wafer 21 is smaller than the thickness of the metal plate 27, and the heat conductive material 28 covers the semiconductor wafer 21. The non-active surface 21b and the sixth surface 27b of the metal plate 27 are as shown in Fig. 6C. 22 201029125 In summary, the package substrate for embedding a semiconductor wafer of the present invention and the method for fabricating the same, first align and fix the semiconductor wafer and the layer on the carrier board by using an adhesive layer. The step of being inserted into and fixed to the through opening of a carrier board eliminates the deviation of the positioning of the semiconductor chip in the opening of the 5 board, thereby increasing the accuracy of the subsequent process. The package substrate for embedding a semiconductor wafer of the present invention and the method for manufacturing the same use the conduction ring to limit the area of the laser beam drilling, thereby preventing the semiconductor beam caused by the laser beam on the action surface outside the periphery of the electrode pad of the semiconductor wafer Wafer loss • Bad. Especially when the semiconductor wafer electrode pad is shrunk, the product yield is more likely to be lowered due to the deviation of the laser beam. Therefore, the present invention can improve the alignment accuracy of the semi-conductor wafer and the fan out line as compared with the conventional method of embedding the package substrate of the semiconductor wafer. At the same time, by forming a conductive ring to limit the area of the laser drilled hole, the precision of the laser drilling can be increased, thereby improving the product yield. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited only by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a process of fabricating a package structure of a conventional embedded semiconductor wafer. 2A and 2 are schematic diagrams showing the formation of blind holes by laser. 3A to 3 are cross-sectional views showing a manufacturing process of a package structure of an embedded semiconductor wafer according to Embodiment 1 of the present invention. 23 201029125 FIG. 4 is a schematic view showing a blind hole formed by laser in Embodiment 1 of the present invention. 5A to 5D are cross-sectional views showing a manufacturing process of a packaged semiconductor wafer in which a semiconductor wafer is embedded in a second embodiment of the present invention. Figure 6A is a perspective view showing the package structure of the embedded semiconductor wafer of Embodiment 3 of the present invention. "Divisional Package and Structure Section 6B is an embedded semiconductor semiconductor wafer of Example 4 of the present invention. 10 is a cross-sectional view of a package structure of an embedded semiconductor wafer of Embodiment 3 of the present invention. [Main element symbol description] 1 First carrier plate 101 through opening 111 electrode pad 121 blind hole 131 conductive blind hole 2a first conductor layer 20a a surface 201 second conductor layer 21a active surface 211 electrode pad 22a conductive ring 220 opening 222, 222' conductive blind hole top 10 first carrier plate 11 semi-conductive wafer 12 first dielectric layer 13 first line 2 Planting plate 20 - dielectric layer 20b second surface 21 semi-conductive wafer 21b non-active surface 22 first circuit layer 22b first line 221 first conductive blind 23 adhesive layer
24 201029125 23a 第三表面 231 盲孔 24 第二線路層 25a, 25c 第一增層結構 25b 第二增層結構 251 第二介電層 252 第二導電盲孔 253 第三線路層 254 電性接觸墊 255 金屬保護層 26a, 26b 防焊層 261 防焊層開孔 27 金屬板 27a 第五表面 27b 第六表面 271 開口 28 導熱材料 D 對位偏差 L 光徑 L， 光徑範圍 R 外徑 R, 孔徑 W 寬度 2524 201029125 23a third surface 231 blind hole 24 second circuit layer 25a, 25c first build-up structure 25b second build-up structure 251 second dielectric layer 252 second conductive blind hole 253 third circuit layer 254 electrical contact pad 255 metal protection layer 26a, 26b solder mask 261 solder mask opening 27 metal plate 27a fifth surface 27b sixth surface 271 opening 28 thermal material D alignment deviation L optical path L, optical path range R outer diameter R, aperture W width 25