TW200527556A - Wire bonding method and semiconductor package using the method - Google Patents

Wire bonding method and semiconductor package using the method Download PDF

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Publication number
TW200527556A
TW200527556A TW093102738A TW93102738A TW200527556A TW 200527556 A TW200527556 A TW 200527556A TW 093102738 A TW093102738 A TW 093102738A TW 93102738 A TW93102738 A TW 93102738A TW 200527556 A TW200527556 A TW 200527556A
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Taiwan
Prior art keywords
wire
bonding
welding
scope
patent application
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Application number
TW093102738A
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English (en)
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TWI263286B (en
Inventor
Chin-Teng Hsu
Ming-Chun Laio
Holman Chen
Chun-Yuan Li
Fu-Di Tang
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Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW093102738A priority Critical patent/TWI263286B/zh
Priority to US10/894,925 priority patent/US7126229B2/en
Publication of TW200527556A publication Critical patent/TW200527556A/zh
Priority to US11/521,792 priority patent/US20070007669A1/en
Application granted granted Critical
Publication of TWI263286B publication Critical patent/TWI263286B/zh

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

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200527556 五、發明說明（1) 【發明所屬之技術領域】 本發明係關於一種打線方法及運用此打線方法之半導 體封裝件，尤指一種令相鄰銲線具有不同線弧高度之打線 方法及運用此打線方法之半導體封裝件。 【先前技術】 對於習知上運用鲜線（W i r e Β ο n d i n g )技術以電性連接 晶片及外界的半導體封裝件而言，其銲線之電性連接品質 與佈設密度往往決定了該封裝件之信賴性與運作效能，因 此，如何於銲線步驟乃至其他製程中維持一較高的銲線可 靠度，顯然為半導體工業發展上的重要電性課題。 習知上運用銲線技術之半導體封裝件可如第7圖所 示，例如一以導線架為晶片承載件的半導體封裝件，係先 於一具有晶片座51 (Die Pad)及多數導腳52 (Lead)之導 線架50上黏置一半導體晶片53，復藉多數銲線54 (Wire) 電性連接該晶片5 3作用表面上之銲墊5 5 ( Pad )與其對應之 多數導腳5 2，復以一封裝膠體5 6包覆該晶片5 3及銲線5 4而 形成一半導體封裝件；因此，如依製程順序來看，即知為 使該銲線5 4之電性品質達至最佳，則除了提升銲線步驟之 可靠度外，接續於銲線步驟後的封膠製程顯然亦為一大關 鍵，如何令該封膠製程中所注入之封裝膠體5 6不致於包覆 銲線5 4時降低該銲線5 4之電性品質，確亦為封裝製程設計 上不可不考量之重點。 第8圖所示即為該型封裝件進行封膠製程之剖視圖， 其係將該導線架5 0置於一上、下模具6 0、6 1間，以令該導
17572石夕品.ptd 第7頁 200527556 五、發明說明（2) 線架5 0上之晶片5 3與多數銲線5 4容設於該上模具6 0與導線 架5 0所形成之上模穴6 2中，並令該上模穴6 2與下模穴6 3間 藉該晶片座5卜導腳5 2與相鄰導腳5 2間之間隙而相互連 通，再自該上、下模具6 0、6 1—側之注膠口 6 4注入一封裝 膠體6 5，以藉封裝膠體6 5之模流而逐步流動並填充滿該 上、下模穴6 2、6 3，進而包覆該晶片5 3及其周圍之多數銲 線5 4 ;然而，若自第9 A圖之上視圖觀之，即知該晶片5 3周 圍之多數銲線5 4具有各種佈設方向，故而不論模流6 6自何 方向流動而進行包覆，其流向均可能與部分銲線5 4之佈設 方向相互垂直，而將使該些銲線5 4受流體壓力之壓迫，導 致如第9B圖所示的銲線54偏移（Sweep)現象，進而令相鄰 之銲線54因偏移而互相接觸，形成短路（Short)並影響其 電性品質，特別對較長且線弧（Loop)較高之銲線而言，其 發生偏移之機率更高；再者，為使半導體裝置之功能更加 多元、運算更為快速，封裝技術正不斷朝向使銲線之佈設 數量增加、使相鄰銲線之間隙降低等趨勢發展，此些趨勢 更將使得相鄰銲線因受壓而致接觸短路的機率大為提高。 因此，習知上為解決此一問題，係如美國專利第 5，3 5 9，2 2 7號案所揭示，而如第1 0圖之側視圖般改變部分 銲線之線弧高度，以令相鄰兩銲線7 5、7 6分別具有不同的 線弧高度，俾使其除了相鄰之間隙外，復增加了高度差之 間隙Η，此時，銲線7 5、7 6即便受模流壓力而產生偏移， 亦可因其高度差而不致碰觸相鄰銲線而產生短路，確可解 決前述的習知電性問題；然而，此一改良將使得銲線7 5的
17572石夕品.ptd 第8頁 200527556 五、發明說明（3) ^^~^ 最大線弧高度S遠高於原本之線弧高度及曰u 八’入曰曰片7 7高 致整體封裝件之高度大為增加，非但不铃a 1 π度’導 封裝發展趨勢，亦將造成模具與封裝膠妒ΛΑ々& /寻短小之 ^肢的多餘成士 形成薄型化與低成本趨勢下的發展障礙。 /Λ x本’而 另有美國專利笫5，156，32 3號案，复後 升係於形忐和 過程中利用打線機（W i r e Β ο n d e r )之銲嘴的紅 、干線之 a 角的軌跡轉折握 作丄以如第1 1圖所示形成具有預定線弧形狀之銲線85木進 而藉此一特殊線弧形狀而強化銲線8 5之剛性，降低其受壓 偏移機率；惟，此一設計僅係改變銲線8 5之線弧形狀，對 於相鄰兩銲線而言，其間隙並未減少，故而一旦模流壓力 甚大’則仍可能使受壓之銲線8 5偏移而碰觸相鄰之銲線， 故同樣未能解決短路等電性問題，而形成良率上的瓶頸； 另如美國專利第5，1 1 1，9 8 9號案所揭示之技術，亦同樣提 出一控制線弧形狀的打線方法，惟亦具有相同之缺點，而 難以徹底解決前述諸問題。 因此，如何提出一種改良式打線方法及運用此打線方 法之半導體封裝件，以避免銲線受模流壓力而產生短路’ 進而可兼顧薄型化封裝、製程簡易與高良率等發展趨勢’ 確為此相關領域所迫切待解之課題。 【發明内容】 因此，本發明之一目的即在於提供一種可提升電性品 質的打線方法及運用此打線方法之半導體封裝件。 本發明之復一目的在於提供一種可符合薄型化封裝需 求的打線方法及運用此打線方法之半導體封裝件。
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第9頁 200527556 五 發明說明（4) 本發明之另一目的右认切 M , 於楗供一種可增加相鄰銲 短路的打续古 、、果方法及運用此打線方法之半導體 線間隙 避免其接觸 封裝件。 本發明之又一目的在於扭 方法及運用此村線方法供一種可減低模流影響的打 本發明之再一目的在 :® :装件 及運用此打線方法之半導體-種便於操作的打線方法 為達前述及其他目的，士 =件 件，係包括··具有電性連接二明所提供之半導體封裝 μ在且有多數第二銲結點署承載件，且該電性連接部 之作用表面上係具有；；件上之晶片，且 線，係佈設於該晶片之周圚、 、干、、、°點，多數第一銲 …圍Μ分別電性…-鋒結點與: 而 線 係 上係具有多數第 該晶片之作用 ，…1夕數第 / in於a之周圍以分… 弟二ί干結點，夕數弟二銲線， 佈設於該晶片之周圍，以分則邊弟一銲線間隔排列 銲結點，其中，該第二薛=性連接第—銲結點與第 鋅線與該第一銲線間具有_高戶弧係向下言折而令該第 一銲線、第二銲線、與部份包覆該晶片、第 此外，本發明所提供之厥=的封裝膠體。 係包括：製備一承戴有晶片之=^的打線方法，其步驟 有電性連接部，而該電性連 ，且該承载件上係具 分別具有第二銲結點與第一銲^點曰^片之作用表面上係 打線工具上移-預定距；，；；；自該第-鲜結點而‘ 銲結點之方向移動—第一 ’ d亥打線工具朝遠離該第_ 離’以令該第二銲線產生
17572石夕品.ptd 第10頁 200527556 五、發明說明（5) 折；將該打線工具上移一預定距離，再使該打線工具朝靠 近該第二銲結點之方向移動一第二距離，以令該第二銲線 再產生一彎折，且該第二距離係大於該第一距離；復將該 打線工具上移一預定距離；以及將該打線工具移動至該第 二銲結點，並以該打線工具截斷該第二銲線，俾使該第二 銲線之截斷端連接於該第二銲結點上，而令該第二銲線之 兩端分別連接該第一銲結點與第二銲結點。 前述第二銲線之線弧係低於該第一銲線之線弧，且該 線弧係低於該晶片之作用表面，而該第二銲線係可視不同 之線路設計而作為一訊號線（S i g n a 1 W i r e )或一接地線 (G r o u n d W i r e );同時，該打線工具係為一習知打線機 (Wire Bonder)上之銲嘴（Capillary)。 前述之承載件係為一導線架或一基板，若其為一導線 架，則該電性連接部係為該導線架上之多數導腳或晶片 座，其中，當該第二銲線連接至該導腳時，該第二銲線係 作為一訊號線，而當該第二銲線連接至該晶片座時，該第 二銲線係作為一接地線；此外，若該承載件為一基板，則 該電性連接部係為該基板上之多數導電跡線。 因此，本發明所揭示之打線方法及運用此打線方法之 半導體封裝件，確可利用該第二銲線之線弧設計，而避免 相鄰之銲線受模流壓力而接觸短路，同時復可達至薄型 化、製程簡易與高良率之功效，大幅解決了習知上所面臨 之問題。 【實施方式】
17572石夕品.ptd 第11頁 200527556 五、發明說明（6) - 以下係藉由特定的具體實例說明本發明之實施方式， 熟悉此技藝之人士可由本說明書所揭示之内容輕易地瞭解 本發明之其他優點與功效。本發明亦可藉由其他不同的具 體實例加以施行或應用，本說明書中的各項細節亦可基ς 不同觀點與應用，在不悖離本發明之精神下進行各種修飾 以下即以採導線架為承載件之半導體封裝件為例，古兒 明本發明之打線方法的較佳實施例，俾使所成形之銲線電 性連接該導線架上之晶片與該導線架之多數導 直 ^第1Α至⑽，首先，如第咖，製備一 /、= ，有晶片15之導、線架1G，i該該多數導腳u與 』 ^用表® 15a上係、分別具有多數之第：鲜結點13與第一銲 、、，。點1 6，其次，如第1 B圖所示以一打 、’ 進行打線作業’其係先於一耐高㈤^機（Wlre Bonder) (Capi 1 lary)中置入一例如金線^^之轉毛細管狀銲嘴2〇 (Spark D1Scharge)技術而於二二^25,復藉電子點火 26，以將該球體26壓置於該晶片Μ末端曰燒結出一球體 該球體2 6受壓變形，再利用超立、之第一銲結點1 6上而使 Wei ding)技術令其銲結於該第接（Ultras〇nic 第1 C圖，向上拉舉該銲嘴2 〇而入i旱結點1 6上；接著，再如 放線，並於該銲嘴2 〇上移—預^為球體2 6延伸變形並進行 遠離該第二銲結點丨3之方向承^距離h 1後，將該銲嘴2 〇朝 丨J f移一楚 線2 5之拉動軌跡產生一垂直轉折 弟一距離s 1，以令該銲 所示之虛線軌跡T ;復如第〗’其技動軌跡即如第1 D圖 將該銲嘴2 0再上移 預
200527556 五、發明說明（7) 定距離h 2 (h 2可略大於h 1 )後，將該銲嘴2 0朝靠近該第二 銲結點1 3之方向、亦即相對於第一次轉折之方向平移一第 二距離s 2，以令該銲線2 5之拉動軌跡再產生一垂直轉折， 同時，該第二距離s 2係大於該第一距離s 1 ;接著，如第1 E 圖，復將該銲嘴2 0上移一預定距離h 3，該距離之長度係視 已拉出之銲線2 5與該第二銲結點1 3之距離而定，俾使該銲 嘴2 0出口之銲線區段2 5 a恰可接置於該第二銲結點1 3上， 同時，為使該銲嘴2 0出口之銲線區段2 5 a更易壓置於該第 二銲結點1 3上，此時可如圖示之虛線軌跡T而令該銲嘴2 0 再朝遠離該第二銲結點1 3之方向平移一適當距離，以控制 該銲線2 5之線弧形狀；最後，再如第1 F圖，將該銲嘴2 0移 動至該第二銲結點1 3，並對該銲嘴2 0出口之銲線區段2 5 a 進行一下壓銲接動作，以令該銲線區段2 5 a壓置並銲接於 該第二銲結點1 3上，再藉該銲嘴2 0前端之平口刀部2 0 a (圖示於第1 E圖）截斷尚未拉出之銲線，此時，該銲線2 5上 之截斷端2 5 a即可銲接定位於該第二銲結點1 3上，俾使其 兩端分別連接於該第二銲結點1 3與第一銲結點1 6而電性連 接該晶片1 5及導腳1 1，並利用本發明所提出之預定拉線軌 跡，而令該銲線2 5具有一向下彎折且低於晶片1 5作用表面 1 5 a之線弧形狀，解決習知打線方法與其所形成之銲線所 遭逢的問題。 因此，藉由前述打線方法，即可令該銲線2 5搭配習知 之銲線3 0而整合於同一封裝件中，解決習知上的電性問 題；該習知銲線3 0之製法係如第2 A圖所示，操作打線機之
17572石夕品.ptd 第13頁 200527556 五、發明說明（8) 銲嘴20而依虛綠 銲嘴2 0並朝遠離 示之執跡T進行拉線’其執跡係上拉該 段較長之銲線3〇= ^應導腳11之方向平移兩次，再拉出一 線30由於並未進置於其所對應導腳11上’此-習知銲 出之銲線25線弧：：下之：折，&其線弧將較本發明所提 因此 以下即將該類習知銲線命名為第一銲線3 〇，而將本發明所 提出之銲線命名為第二銲線2 5。 马n ’而令該習知銲線3 0與本發明所提出 之鮮線25具有—高度差（可比較第1F圖與第2B圖） 故而’可將該習知第一銲線3 〇與本發明所提出之第二 崔干線2 5格配並佈没於同一封裝件中，如第3圖所示，令該 第一銲線3 0與第二銲線2 5相互間隔排列地佈設於該封裝件 之晶片1 5周圍，以將該第一銲線3 0與第二銲線2 5作為訊號 線（S i g n a 1 W i r e )，電性連接該晶片1 5之作用表面1 5 a與其 對應導腳1 1並進行況號傳輸，此時，由於該第一銲線3 〇與 弟一銲線2 5之線弧間具有一高度差，故相鄰兩銲線將不再 具有相同之線弧形狀與高度，而使該兩相鄰銲線間除了其 相鄰間隙X外，復增加了高度上之間隙γ，俾使該封裝件進 行如第4 A、4 B圖所示之封膠製程時，將不再因銲線偏移而 有碰觸短路之問題，因為對佈設方向與封裝膠體4 〇模流流 向35相互垂直之銲線而言，即便其受到模流壓力之壓迫2 偏移，亦將因相鄰銲線間的高度差間隙γ而不致相互碰 觸，且不論該封裝件之線路佈設密度如何提高，相鄰銲飧 之間隙X如何縮小，亦不欵使其受壓之碰觸機率增加，大 幅解決了習知打線技術的問題。
200527556 五、發明說明（9) 此外，由於該第二銲線2 5之線弧高度係較該第一銲線 3 0為低，且有部份線弧甚至較該晶片1 5之作用表面1 5 a為 低，因此，完成封膠製程後之封裝件將具有薄型化之優 點，無需因本發明所提出之第二銲線2 5而增加該封裝件之 厚度，再者，本發明之打線技術亦具有製程簡易與成本低 廉之功效，僅需改變打線機之自動化操作軌跡，而控制該 銲嘴依預定軌跡拉線作動即可，非但可解決習知上之缺 點，更可符合商業量產上之需求。 前述之第二銲線2 5除了作為訊號線外，亦可運用於具 有接地線（G r 〇 u n d W i r e )的封裝產品上，而令其電性連接 該晶片1 5之作用表面1 5 3«與該導線架1 0之晶片座1 2 ’此時 即可作為接地線而發揮接地效能，並避免該接地線因受壓 偏移而與相鄰之訊號線產生接觸短路，影響接地之電性效 能。 因此，利用本發明之打線方法所製成之半導體封裝件 即如第5圖之剖視圖所示，包括一導線架1 0，係具有一晶 片座1 2與圍繞該晶片座1 2的多數導腳1 1，該多數導腳1 1上 係均具有第二鲜結點1 3 ’而該晶片座1 2上則黏置有一晶片 1 5，且該晶片1 5之作用表面1 5 a周圍係佈設有多數第一銲 結點1 6 ;同時，該晶片1 5之周圍係佈設有多數用以電性連 接該第一銲結點1 6與第二銲結點1 3的銲線，該多數銲線係 包括習知之第一銲線3 0與利用本發明之打線方法所形成之 第二銲線2 5，其中，該第一銲線3 0與第二銲線2 5係相互間 隔排列，且該第二銲線2 5之線弧係向下彎折，而令部份第
17572石夕品· ptd 第15頁 200527556 五、發明說明（10) 讀封 銲線 以藉讀外 號 二銲線2 5低於該第一銲線3 0並具有一高度差；此外 裝件復包括一用以包覆該晶片座1 2、晶片1 5、第 3 0、第二銲線2 5、與部份導腳丨丨之封裝膠體4 〇， 露出封裝膠體4 0且具有一彎折的多數導腳丨丨 士 成外界與晶片1 5間的電性連接關係。 别机％ ’定 前述實施例與相關圖式 承載件，惟本發明之打線方法亦可適 ：2裳件之 電性連接之封裝件，例如μ _ ^ ‘線作為 球柵陣列半導體封裝件，^ :所不以“反45為承載件之 連接該晶片15之作用夺=、、fq3與弟/銲線25,俾使其電性 (未圖示），而藉該導電跡線層 γ數線層 46將該=15之訊號傳送至外界，或者，亦可將；； 所設計^第二銲線25，即可造成相鄰兩锝線間的高3 _ Μ π，π π ΜI ί 成封裝膠體40時造成相鄰銲線的接 觸短路’攸而解決習知技術之諸多問題。 綠方Ϊ i:ΐ:t本發明所揭示之打線方法及運用此打 、、' / ±、杜令衣件，確可避免銲線受模流壓力而接觸 短路I同％復可達至薄型化、製 與高良 上述實例僅為例 大幅兼顧了封裝技術的各方面發展需求。 性說明本發明之原理及其功效，而 ϊ=:ίΠ 範 違
17572 矽品.ptd 第16頁 200527556
1757¾夕品.ptd 第17頁 200527556 圖式簡單說明 【圖式簡單說明】 第1 A至1 F圖係本發明之打線方法的較佳實施例流程 圖，所形成之銲線係為第二銲線； 第2 A及2 B圖係習知打線方法之流程圖，所形成之銲線 係為第一銲線； 第3圖係本發明將第一銲線與第二銲線間隔佈設於晶 片周圍之示意圖； 第4 A及4 B圖係第3圖所示之晶片與銲線進行封膠製程 之示意圖； 第5圖係本發明所揭示之半導體封裝件的較佳實施例 剖視圖； 第6圖係本發明所揭示之半導體封裝件的第二實施例 剖視圖； 第7圖係習知上以導線架為晶片承載件之半導體封裝 件剖視圖； 第8圖係第7圖所示之封裝件進行封膠製程之剖視圖； 第9 A圖係第7圖所示之封裝件進行封膠製程之上視 圖， 第9 B圖係第7圖所示之封裝件於封膠製程中產生銲線 偏移之上視圖； 第1 0圖係美國專利第5，3 5 9，2 2 7號案所揭示之半導體 封裝件剖視圖；以及 第1 1圖係美國專利第5，1 5 6，3 2 3號案所揭示之半導體 封裝件剖視圖。
17572石夕品.ptd 第18頁 200527556
圖式簡單說明 10 導 線 架 11 導 腳 12 晶 片 座 13 第 二 銲 結 15 晶 片 15a 作 用 表 面 16 第 一 銲 結點 20 銲 嘴 2 0a 平 π 刀 部 25 第 二 銲 線 2 5a 銲 線 區 段 26 球 體 30 第 一 銲 線 35 模 流 40 封 裝 膠 體 45 基 板 46 銲 球 50 導 線 架 51 晶 片 座 52 導 腳 53 晶 片 54 銲 線 55 銲 塾 56 封 裝 膠 體 60 上 模 具 61 下 模 具 62 上 模 穴 63 下 模 穴 64 注 膠 口 65 封 裝 膠 體 66 模 流 75 銲 線 76 鲜 線 77 晶 片 85 群 線 T 軌 跡 17572石夕品.ptd 第19頁

Claims (1)

  1. 200527556 六、申請專利範圍 1. 一種半導體封裝件，係包括： 承載件，係具有電性連接部，且該電性連接部上 係具有多數第二銲結點； 晶片，係接置於該承載件上，且該晶片之作用表 面上係具有多數第一銲結點； 多數第一銲線，係佈設於該晶片之周圍以分別電 性連接第一銲結點與第二銲結點； 多數第二銲線，係與該第一銲線間隔排列而佈設 於該晶片之周圍，以分別電性連接第一銲結點與第二 銲結點，其中，該第二銲線之線弧係向下彎折而令該 第二銲線與該第一銲線間具有一高度差；以及 封裝膠體，係包覆該晶片、第一銲線、第二銲 線、與部份承載件。 2. 如申請專利範圍第1項之半導體封裝件，其中，該第二 銲線之線弧係低於該第一銲線之線弧。 3. 如申請專利範圍第1項之半導體封裝件，其中，該第二 銲線係向下彎折而令其線弧低於該晶片之作用表面。 4. 如申請專利範圍第1項之半導體封裝件，其中，該第一 銲線與第二銲線係為金線。 5. 如申請專利範圍第1項之半導體封裝件，其中，該第一 銲線與第二銲線係均為訊號線（S i g n a 1 W i r e )。 6. 如申請專利範圍第1項之半導體封裝件，其中，該第二 鮮線係為接地線（G r 〇 u n d W i r e )。 7. 如申請專利範圍第1項之半導體封裝件，其中，該承載
    17572石夕品.ptd 第20頁 200527556 六、申請專利範圍 件係為一導線架。 8. 如申請專利範圍第7項之半導體封裝件，其中，該電性 連接部係為該導線架上之多數導腳。 9. 如申請專利範圍第7項之半導體封裝件，其中，該電性 連接部係為該導線架上之晶片座。 1 0 .如申請專利範圍第1項之半導體封裝件，其中，該承載 件係為一基板。 11.如申請專利範圍第1 0項之半導體封裝件，其中，該電 性連接部係為該基板上之多數導電跡線。 1 2 . —種打線方法，其步驟係包括： 製備一承載有晶片之承載件，且該承載件上係具 有電性連接部，而該電性連接部與該晶片之作用表面 與上係分別具有第二銲結點與第一銲結點； 進行打線步驟，而以銲線之一端連接該第一銲結 點； 自該第一銲結點而將打線工具上移一預定距離， 再將該打線工具朝遠離該第二銲結點之方向移動一第 一距離，以令該銲線產生一彎折； 將該打線工具上移一預定距離，再使該打線工具 朝靠近該第二銲結點之方向移動一第二距離，以令該 銲線再產生一彎折，且該第二距離係大於該第一距 離， 復將該打線工具上移一預定距離；以及 將該打線工具移動至該第二銲結點，並以該打線
    17572石夕品.ptd 第21頁 200527556 六、申請專利範圍 工具截斷該銲線，俾使該銲線之截斷端連接於該第二 銲結點上，而令該銲線之兩端分別連接該第一銲結點 與第二銲結點。 1 3 .如申請專利範圍第1 2項之打線方法，其中，該第二銲 線之線弧係低於該第一銲線之線弧。 1 4.如申請專利範圍第1 2項之打線方法，其中，該銲線之 線弧係低於該晶片之作用表面。 1 5 .如申請專利範圍第1 2項之打線方法，其中，該銲線係 為金線。 1 6 .如申請專利範圍第1 2項之打線方法，其中，該銲線係 為訊號線（S i g n a 1 W i r e )。 1 7 .如申請專利範圍第1 2項之打線方法，其中，該銲線係 為接地線（Ground Wire)。 1 8 .如申請專利範圍第1 2項之打線方法，其中，該打線工 具係為一打線機（W i r e Β ο n d e r )上之銲嘴（C a p i 1 1 a r y ) 〇 1 9 .如申請專利範圍第1 2項之打線方法，其中，該承載件 係為一導線架。 2 0 .如申請專利範圍第1 9項之打線方法，其中，該電性連 接部係為該導線架上之多數導腳。 2 1.如申請專利範圍第1 9項之打線方法，其中，該電性連 接部係為該導線架上之晶片座。 2 2 .如申請專利範圍第1 2項之打線方法，其中，該承載件 係為一基板。
    17572石夕品.ptd 第22頁 200527556
    17572石夕品.ptd 第23頁
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