TW200409228A - Methods for manufacturing contact plugs of semiconductor device - Google Patents
Methods for manufacturing contact plugs of semiconductor device Download PDFInfo
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- TW200409228A TW200409228A TW092117815A TW92117815A TW200409228A TW 200409228 A TW200409228 A TW 200409228A TW 092117815 A TW092117815 A TW 092117815A TW 92117815 A TW92117815 A TW 92117815A TW 200409228 A TW200409228 A TW 200409228A
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- film
- insulating film
- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 59
- 239000002002 slurry Substances 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 239000007800 oxidant agent Substances 0.000 claims abstract description 15
- 230000002378 acidificating effect Effects 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 230000001590 oxidative effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 2
- MVFCKEFYUDZOCX-UHFFFAOYSA-N iron(2+);dinitrate Chemical compound [Fe+2].[O-][N+]([O-])=O.[O-][N+]([O-])=O MVFCKEFYUDZOCX-UHFFFAOYSA-N 0.000 claims description 2
- KHIWWQKSHDUIBK-UHFFFAOYSA-N periodic acid Chemical compound OI(=O)(=O)=O KHIWWQKSHDUIBK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 239000012530 fluid Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 150000003376 silicon Chemical class 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 80
- 230000015572 biosynthetic process Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000002474 experimental method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000003082 abrasive agent Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000002144 chemical decomposition reaction Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013039 cover film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- -1 hydrogen peroxide) Chemical compound 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QWXYZCJEXYQNEI-OSZHWHEXSA-N intermediate I Chemical compound COC(=O)[C@@]1(C=O)[C@H]2CC=[N+](C\C2=C\C)CCc2c1[nH]c1ccccc21 QWXYZCJEXYQNEI-OSZHWHEXSA-N 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 239000006193 liquid solution Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Weting (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
200409228 玖、發明說明: 【發明所屬之技術領域】 本發明係揭示製造半導體裝置接觸塞柱之方法。更明確言 之所揭丁之方法可形成安定著陸塞柱多晶矽(Lpp),其方 式疋進行中門層n蓴膜與多晶碎層之化學機械拋光(c縱) 製程,其係為一種塞柱材料,利用含有氧化劑之酸性漿液 ,使氧化物薄膜與多晶矽層之盤形化現象降至最低。 【先前技術】 為提供小、高容量及高度整合之半導體裝置,故在形成半 導體裝置之電晶體、位元線及電容器之後,必須進行接觸 基柱之形成製程,其可電連接至各裝置,意即電晶體、位 元線及電容器。 一般ΠΤ7 a,當進行接觸塞柱之形成製程時,必須進行平面 化製程,其方式是利用單一漿液,同時拋光多層,以形成 具有高縱橫比之接觸塞柱。 但是,當僅使用單一漿液拋光多層狀薄膜時,各層係在差 異拋光速度下被拋光,意即具有不同拋光選擇比,階層差 兴係在諸層中產生。結果,難以應用各種後續製程以進行 精製。 特定T之,階層差異係更強烈地產生於中間層絕緣薄膜上 ’在比其他層較高拋光速度下被拋光。因此,在拋光製程 中產生之各層副產物’及衆液之磨料殘留物,係被充填在 中間層絕緣薄膜之上方部份中。結果,在塞柱裝置之間產 生缺陷,譬如電橋。 86356 200409228 圖la至Id係概要地說明製造半導體裝置接觸塞柱之習用方 法。 參考圖la,一個界定活性區域之壕溝型裝置隔離薄膜丨2係 在矽基材11上形成。並使字元線導電層(未示出)與硬罩蓋 膜(未示出),意即氮化物薄膜,在基材丨丨之單元區域上形 成,及連績地蝕刻。結果,形成字元線圖樣16,其中硬罩 蓋圖樣14係於字元線導電層圖樣13上形成。 參考圖lb,隔體15係於字元線圖樣16之側面上形成。中間 層絕緣薄膜17係於所形成結構之整個表面上形成。 參考圖lc中間層、纟巴、纟豕薄膜17係使用著陸塞柱接觸罩蓋( 未示出)選擇性地蝕刻,以形成供塞柱用之接點空穴(未示 出)。 在多晶矽層(未示出)被沉積於所形成結構之整個表面上之 後,其包括供塞柱用之接點空穴(未示出),係使用中間I 絕緣薄膜17作為㈣障壁薄膜,進行掘光製程,以沉積多 晶矽層18在供塞柱用之接點空穴處。 參考圖Id,CMP製程係利用一般鹼性CMp漿液,對多晶矽 層18正個衣面上之氧化物薄膜,及中間層絕緣薄膜π進行 直到使硬罩盍圖樣14曝露為止,以形成塞柱多晶矽19。 於上逑CMP製程中使用之驗性漿液,係為氧化物薄膜用之 一般CMP漿液,具有pH範圍從8至丨2,包含磨料,譬如膠態 或煙霧狀SK)24 ai2〇3。 叙而s,必須使用在多層之間具有類似拋光速度之漿液 以移除多層薄膜。但是,由於習用拋光製程係使用氧化 86356 200409228 物薄膜用之驗性衆液進行, 之拋光選擇比係高於硬罩蓋 選擇比係高於多晶矽層。結 拋光速度。 故中間層絕緣薄膜與多晶矽層 膜,且中間層絕緣薄膜之拋光 果,中間層絕緣薄膜具有最高 7 μ可陘暴枉多晶矽 膜形成之硬罩蓋絕緣薄膜外露為止時^二w化物薄 路马止時,嚴重盤形化作 在中間層絕緣薄膜與多^層上產生。在具有較高抱光選 擇比之中間層絕緣薄膜上之盤形化作用識,係比在多晶碎 層上之盤形化作用20a,更嚴重地產生。 中間層絕緣薄膜之盤形化作用,需要其他氧化物薄膜之另 個/儿積製程’以防止薄膜之表面形態在後續製程中被轉 變。由於CMP製程所造成之拋光殘留物,係被充填在中間層 、’·巴緣薄膜之上方部份中,此係由於盤形化作用21a與仙所致 …不,產生著陸|柱多晶矽之缺陷22,因為殘留物未在· 後績洗淨製程中被移除(參閱圖2a與。此等缺陷會在後續 接觸製程中’於接觸塞柱之間形成電橋,於是使裝置之良 率、特徵及可靠性降級。因此,難以具體化表現裝置之高 整合。 【發明内容】 本發明係揭示一種製造半導體裝置接觸塞拄之方法,其中 薄膜之盤形化現象,係利用對各層具有類似選擇性之氧化 物薄膜用CMP漿液,而被降至最低。 較佳具體實施例之詳述 本發明係揭示一種製造半導體裝置接觸塞柱之方法。 86356 200409228 ’係包括: 與硬罩蓋氮化 以形成接點 所揭示用於製造半導體裝置接觸塞柱之方法 形成子兀線圖樣,其具有字元線導電性材料 物薄膜之連續堆疊結構,在半導體基材上; 形成氮化物薄膜隔體於字元線圖樣之側面上 形成平面化中間層絕緣薄膜於字元線圖樣上 I虫刻該中間層絕緣薄膜,直到基材外露為止 空穴; 形成多晶咬層於中間層絕緣薄膜之表面上,其中係形成接 點空穴;及 接 在多晶石夕層與中間層絕緣薄膜上,使用氧化物薄膜用之酸
性CMP漿液,進行化學機械拋光(CMP)製程,該漿液具有pH 乾圍從2至7 ’含有氧化劑,直到硬罩蓋氮化物薄膜外露為 止。 、' 孩氧化劑包括過氧化氫既仏)、過碘酸恥1〇6)、硝酸鐵 [Fe(N3 〇9)]或其組合。較佳係使用氏仏作為此氧化劑。氧化 劑之存在量範圍係從丨至4〇體積%,更佳為2〇至3〇體積%, 以CMP漿液為基準。 此具有pH範圍從2至5之酸性漿液,係包含磨料,選自包 括矽石(Si〇2)、氧化鈽(Ce〇2)、氧化锆(Zr〇2)、氧化鋁㈧A;) 及其組合。磨料之存在量範圍係從10至50重量%,更佳為25 至35重量%,以CMP漿液為基準。 一般而言,習用上,係使用具有pH範圍從10至13之鹼性 衆:液’作為氧化物薄膜用之漿液。由於鹼性漿液包含許多〇H-基團’故盤形化現象係在氧化物薄膜上產生,此係由於其 86356 200409228 在CMP製程期間化學分解所致。 但是’本發明供氧化物薄膜用之酸性漿液,可防止氧化物 薄膜之化學分解,因其包含比〇H-基團更多之矿基團。 由於本發明氧化物薄膜用之酸性漿液,對於多晶矽層比對 於氧化物薄膜,具有較低拋光選擇比,故所揭示之酸性衆 液包含氧化劑,以改良對多晶物質之拋光選擇比。 多晶矽層較佳係使用選自包括摻雜非晶質矽薄膜、ρ_摻 雜多晶碎薄膜、Ρ-摻雜磊晶矽薄膜及其組合之一形成。 所揭示之製造方法將參照附圖詳細描述。 圖3a至3d係概要地說明所揭示之方法,根據此揭示内容製 造半導體裝置之接觸塞柱。 參考圖3a,一個界定活性區域之壕溝型裝置隔離薄膜义係 在矽基材31上形成。且字元線導電層(未示出)與硬罩蓋膜( 未不出),意即氮化物薄膜,係於基材31之單元區域上形成^ ,及連續蝕刻。結果,形成字元線圖樣36,其中硬罩蓋圖 樣34係於字元線導電層圖樣33上形成。 硬罩盍膜較佳係由氮化物薄膜所組成,而字元線導電層係 由SiON或有機底arc層所組成。 參考圖3b,隔體35係於字元線圖樣36之側面上形成。平面 化中間層絕緣薄膜37係於所形成結構之整個表面上形成。 絕緣薄膜隔體較佳係使用氮化物薄膜形成,而中間層絕緣 薄膜係由具有優越流動性之絕緣材料所組成,譬如BpsG(硼 鱗碎酸鹽玻璃)或HDP(高密度電漿)氧化物薄膜。 參考圖3c,中間層絕緣薄膜37係使用著陸塞柱接觸罩蓋( 86356 -10- 200409228 以形成供塞柱用之接點空穴(未 未示出)選擇性地蝕刻 出)〇 /在多晶矽層(未示出)被沉積在所形成結構之整個表面上之 ,^包括供塞柱用之接點空穴(未示出),係使用中間層 蜿緣薄膜37作為蝕刻障壁薄μ,進行拋光製程,以沉積多 晶矽層38,在供塞柱用之接點空穴(未示出)處。/男夕 /曰日碎層較佳係由ρ_摻雜非晶f碎薄膜、ρ_摻雜多晶碎薄 膜、ρ'摻雜磊晶矽薄膜或其組合所組成。 此處,供塞柱用之接點空穴,較佳係使用,,τ,,_型著陸塞柱 多^矽(參閱圖4a)形成。而在圖3kSEM照片巾,顯=柱 之夕BEJ矽係在接觸區域上形成(參閱圖牝)。 參考圖3d,CMP製程係利用所揭示供氧化物薄膜用之⑽ 漿夜,在多晶碎層38與中間層絕緣薄膜37之整個表面上進 行’直到硬罩蓋圖樣34外露為止。結果,形成塞柱多晶㈣5. 應明瞭的是,可形成具有很少受到傷害部份之接觸塞柱, 因為根據所揭示之製造方法 、〜、 去盤形化作用幾乎不會在所形 成塞柱多晶矽之橫截面上產生(參閱圖“與允卜 【實施方式】 二揭示供氧化物薄膜用之酸性⑽漿液,將參考下文實例 更詳細地描述,其並不意欲成為限制。 Α·所揭示漿液之製備 Β實例1. 於含有30重量%Sl〇2作為磨料之94重量%供氧化物薄膜用 〈酸性CMP漿液中’添加6重量%H2〇2,並攪拌。然後,將
-1U 86356 200409228 所形成〈混合物進—步攪拌約3〇分鐘,直到混合物完全混 合且安定化為止。因此,製成所揭示之漿液。 B.使用所揭示漿液在諸層中之抛光速度之比較 _比較實例1. 使碎層/儿積在中間層絕緣薄膜之整個表面上,包括供塞柱 用〈接點艾穴。然I’在矽層與中間層絕緣薄膜上,使用 未具有氧化劑之習用鹼性CMP漿液,進行CMP製程,直到硬 罩蓋氮化物薄膜外露為止。 CMP製程係藉執道系統之CMp設備,在頭壓為3跸且檯桌 轉數為600 rpm下進行。 此處’經拋光氧化物薄膜與經拋光多晶矽層之厚度,在第 一次貫驗中,個別為2609人與1821A ,而在第二次實驗中,為 2620A與1342A。氧化物薄膜/多晶矽層顯示具有拋光選擇比 在第’入只驗中為1.43,而在第二次實驗中為ι·95,平均為1.69· 。因此,明瞭氧化物薄膜比多晶矽層更迅速地被拋光(參閱 圖6) 〇 實例1. 使碎層沉積在中間層絕緣薄膜之整個表面上,包括供塞柱 用之接點空穴。然後,在矽層與中間層絕緣薄膜上,使用 所揭示之得自製備實例1之CMP漿液,進行CMP製程,直到 硬罩蓋氮化物薄膜外露為止。 此CMP製程之條件係與比較實例1相同。
結果’經拋光之氧化物薄膜與多晶矽層之厚度,在第一次 實驗中,個別為1437人與5292A,而在第二次實驗中,為1429A 86356 -12- 200409228 與5684A。氧化物薄膜/多晶矽層顯示具有拋光選擇比,在 第一次實驗中為0·25,而在第二次實驗中為0.27,平均為0.26 。因此’明瞭多晶矽層係比氧化物薄膜更迅速地被拋光(參 閱圖6)。 正如實驗結果所証實,當CMp製程在氧化物薄膜與多晶矽 層上’使用所揭示之含有氧化劑之酸性CMP漿液進行時,多 晶矽層比氧化物薄膜具有較快速之拋光速度,達兩倍或更 大。因此,多晶矽層可容易地被拋光。 如前文所討論者,其中盤形化現象係在中間層絕緣薄膜與 多晶矽層上被降至最低之接觸塞柱,可經由CMP製程,使用 所揭示之含有氧化劑之酸性CMp漿液形成,因為中間層絕緣 薄膜與多晶矽層,在用於形成塞柱多晶矽之製程中,與使 用未具有氧化劑之習用鹼性CMP漿液之CMp製程比較,係具 有逆轉之拋光選擇比。因此,裝置特徵之降質可被防止,一 這會造成半導體裝置之特徵與可靠性之改良,以製造高度 整合之半導體裝置。 【囷式簡單說明】 圖la至Id係概要地說明製造半導體裝置接觸塞柱之習用方 法。 圖2a與2b為SEM照片,顯示圖1(1之習用接觸塞柱之平面與 橫截面圖。 圖μ至3d係概要地說明根據本揭示内容製造半導體裝置接 觸塞柱之所揭示方法。 圖4a與4b為SEM照片,說明圖3C柱縮宏gβ,、 M JC袪觸塞柱足頂邵視圖與橫 86356 -13 - 200409228 截面。 圖5a與5b為SEM照片,顯示圖3d接觸塞柱之平面與橫截面 圖。 圖6為一圖表,說明當薄膜在晶圓上使用所揭示之CMP漿 液拋光時之拋光速度。 【圖式代表符號說明】 11,31 :矽基材 12, 32 :隔離薄膜 13, 33 :字元線導電層圖樣 14, 34:硬罩蓋圖樣 15, 35 :隔體 16, 36 :字元線圖樣 17,37 :中間層絕緣薄膜 18, 38 :多晶矽層 _ 19, 39 :塞柱多晶矽 20, 21 :盤形化作用 20a :盤形化作用 20b :盤形化作用 21a :盤形化作用 21b :盤形化作用 22 :缺陷 -14 - 86356
Claims (1)
- 200409228 拾、申請專利範圍: 1. 一種製造半導體裝置接觸塞柱之方法,其包括: 形成字元線圖樣,其具有纟元線I電性㈣與硬罩蓋 氮化物薄膜之連續堆疊結構,在半導體基材上; 1 形成氮化物薄膜隔體於字元線圖樣之侧面上; 形成平面化中間層絕緣薄膜於字元線圖樣上; 蝕刻中間層絕緣薄膜,直到基材外露為止,以形成接 點空穴; 形成多晶矽層於中間層絕緣薄膜之表面上,其中係形 成接點空穴;及 於多晶矽層與中間層絕緣薄膜上,使用氧化物薄膜用 之酸性CMP漿液,進行化學機械拋光(CMp)製程,該漿液 具有pH範圍從2至7,含有氧化劑,直到硬罩蓋氮化物薄 膜外露為止。 、 2·根據申請專利範圍第丨項之方法,其中氧化劑係選自包括 過氧化氫(H2〇2)、過碘酸阳21〇6)、硝酸鐵[Fe(N3 〇9)]及其 組合。 3·根據申請專利範圍第1項之方法,其中氧化劑之存在量範 圍係從1至40體積%,以CMP漿液為基準。 4.根據申請專利範圍第1項之方法,其中氧化劑之存在量範 圍係從20至30體積%,以CMP漿液為基準。 5·根據申清專利範圍第1項之方法,其中酸性衆液具有pH 範圍從2至5。 6.根據申請專利範圍第丨項之方法,其中酸性槳液包含磨料 86356 200409228 ,選自包括石夕石(Sl〇2)、氧化卸(Ce〇2)、氧化锆⑽2)、氧 化鋁(Al2〇3)及其組合。 7.根據_請專利範圍第6項之方法,其中磨料之存在量範圍 係從10至50重量%,以CMP漿液為基準。 8·根據申請專利笳[篥7項> +、、土 月兮π靶囷罘/貝又万法,其中磨料之存在量範圍 係從25至35重量%,以CMP漿液為基準。 9. 根據申請專利範圍第η之方法,其中多晶梦層係使用選 自包括Ρ-摻雜非晶質矽薄膜、ρ_摻雜多晶矽薄膜、&摻 雜磊晶碎薄膜及其組合之一形成。 10. 根據中請專利範圍第1項之方法,其中字元線導電性材料 係由SiON或有機底ARC層形成。 11·根據申請專利範圍第丨項之方法,其中中間層絕緣薄膜係 由BPSG (硼磷矽酸鹽玻璃)或HDp (高密度電漿)氧化物薄 膜形成。 12·種製造半導體裝置接觸塞柱之方法,其包括·· 形成罕元線圖樣,其具有字元線導電性材料與硬罩蓋 氮化物薄膜之連續堆疊,在半導體基材上; 形成氮化物薄膜隔體於字元線圖樣之側面上; 形成平面化中間層絕緣薄膜於字元線圖樣上; 蚀刻中間層絕緣薄膜,直到基材外露為止,以形成接 點空穴; 形成多晶矽層於中間層絕緣薄膜之表面上,其中係形 成接點空穴;及 在多晶碎層與中間層絕緣薄膜上,使用氧化物薄膜用 86356 200409228 之CMP槳液, ,含有〇2, 進行CMP製程,該漿液具有pH範圍為2至7 其含量範圍從1至40體積%。 86356
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JP2006005237A (ja) * | 2004-06-18 | 2006-01-05 | Sharp Corp | 半導体装置の製造方法 |
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US20090056744A1 (en) * | 2007-08-29 | 2009-03-05 | Micron Technology, Inc. | Wafer cleaning compositions and methods |
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