SG68634A1 - Dynamic memory - Google Patents

Dynamic memory

Info

Publication number
SG68634A1
SG68634A1 SG1997003540A SG1997003540A SG68634A1 SG 68634 A1 SG68634 A1 SG 68634A1 SG 1997003540 A SG1997003540 A SG 1997003540A SG 1997003540 A SG1997003540 A SG 1997003540A SG 68634 A1 SG68634 A1 SG 68634A1
Authority
SG
Singapore
Prior art keywords
dynamic memory
dynamic
memory
Prior art date
Application number
SG1997003540A
Other languages
English (en)
Inventor
Masayuki Nakamura
Masatoshi Hasegawa
Seiji Narui
Yousuke Tanaka
Shinichi Miyatake
Shuichi Kubouchi
Kazuhiko Kajigaya
Original Assignee
Hitachi Ulsi Eng Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ulsi Eng Corp, Hitachi Ltd filed Critical Hitachi Ulsi Eng Corp
Publication of SG68634A1 publication Critical patent/SG68634A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
SG1997003540A 1996-10-25 1997-09-24 Dynamic memory SG68634A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30122296A JP3712150B2 (ja) 1996-10-25 1996-10-25 半導体集積回路装置

Publications (1)

Publication Number Publication Date
SG68634A1 true SG68634A1 (en) 1999-11-16

Family

ID=17894259

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997003540A SG68634A1 (en) 1996-10-25 1997-09-24 Dynamic memory

Country Status (6)

Country Link
US (1) US5905685A (ko)
JP (1) JP3712150B2 (ko)
KR (1) KR100499452B1 (ko)
CN (1) CN1181632A (ko)
SG (1) SG68634A1 (ko)
TW (1) TW348316B (ko)

Families Citing this family (33)

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US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US7064376B2 (en) * 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US6111802A (en) * 1997-05-19 2000-08-29 Fujitsu Limited Semiconductor memory device
WO1998058382A1 (fr) 1997-06-16 1998-12-23 Hitachi, Ltd. Dispositif a circuit integre transistorise
JPH11260054A (ja) * 1998-01-08 1999-09-24 Mitsubishi Electric Corp ダイナミック型半導体記憶装置
TW441088B (en) * 1998-03-16 2001-06-16 Hitachi Ltd Semiconductor integrated circuit apparatus
KR100279058B1 (ko) * 1998-07-13 2001-01-15 윤종용 낮은 전원 전압 하에서 고속 쓰기/읽기 동작을 수행하는 반도체메모리 장치
KR100297727B1 (ko) * 1998-08-13 2001-09-26 윤종용 분리 제어라인의 큰 부하에 의한 스피드 손실을 방지할 수 있는반도체 메모리 장치
US6300183B1 (en) * 1999-03-19 2001-10-09 Microchip Technology Incorporated Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor
EP1039470A3 (en) 1999-03-25 2000-11-29 SANYO ELECTRIC Co., Ltd. Semiconductor memory device
KR100368312B1 (ko) * 1999-12-27 2003-01-24 주식회사 하이닉스반도체 워드라인 디코더
KR100347140B1 (ko) * 1999-12-31 2002-08-03 주식회사 하이닉스반도체 전압 변환 회로
DE10026275A1 (de) 2000-05-26 2001-12-13 Infineon Technologies Ag Verfahren zum Testen einer Vielzahl von Wortleitungen einer Halbleiterspeicheranordnung
US6504766B1 (en) * 2001-06-29 2003-01-07 International Business Machines Corporation System and method for early write to memory by injecting small voltage signal
JP2003132683A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP4437891B2 (ja) * 2003-03-24 2010-03-24 Ｏｋｉセミコンダクタ株式会社 同期型ｄｒａｍのデータ書込方法
KR100528806B1 (ko) * 2003-05-26 2005-11-15 주식회사 하이닉스반도체 반도체 메모리 장치
JP4662437B2 (ja) * 2004-11-30 2011-03-30 ルネサスエレクトロニクス株式会社 半導体集積回路
KR100648280B1 (ko) * 2005-01-04 2006-11-23 삼성전자주식회사 반도체 메모리 장치 및 그것의 워드라인 전압 공급 방법
US7375999B2 (en) * 2005-09-29 2008-05-20 Infineon Technologies Ag Low equalized sense-amp for twin cell DRAMs
US20070223296A1 (en) * 2006-03-24 2007-09-27 Christopher Miller Bitline isolation control to reduce leakage current in memory device
JP5068615B2 (ja) * 2007-09-21 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置
US8238141B2 (en) 2010-08-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. VSS-sensing amplifier
US9001606B2 (en) * 2010-08-27 2015-04-07 Rambus Inc. Memory methods and systems with adiabatic switching
EP2849218B1 (en) * 2013-09-16 2016-02-03 ST-Ericsson SA Integrated circuit of CMOS type comprising first and second circuit parts
CN104299650A (zh) * 2014-09-25 2015-01-21 苏州宽温电子科技有限公司 一种改进型选择栅驱动电路
KR102368878B1 (ko) * 2015-07-31 2022-03-02 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 비트 라인 센스 앰프 동작 방법
KR20180049502A (ko) * 2016-11-03 2018-05-11 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법
KR102413984B1 (ko) * 2017-11-23 2022-06-29 에스케이하이닉스 주식회사 반도체 메모리 장치
KR102424285B1 (ko) * 2018-02-01 2022-07-25 에스케이하이닉스 주식회사 멀티 레벨 센싱 회로 및 이를 포함하는 반도체 장치
US11403033B2 (en) * 2019-12-31 2022-08-02 Taiwan Semiconductor Manufacturing Company Limited Memory circuit including an array control inhibitor
CN115954040B (zh) * 2023-03-14 2023-06-02 长鑫存储技术有限公司 缺陷检测方法及其装置、电子设备及存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025290A (ja) * 1988-06-22 1990-01-10 Nec Corp 半導体メモリ
KR940002859B1 (ko) * 1991-03-14 1994-04-04 삼성전자 주식회사 반도체 메모리장치에서의 워드라인 구동회로
JP3373534B2 (ja) * 1991-07-02 2003-02-04 株式会社東芝 半導体記憶装置
JP3345449B2 (ja) * 1993-01-13 2002-11-18 株式会社東芝 ダイナミック型半導体記憶装置
JP3402641B2 (ja) * 1993-01-21 2003-05-06 株式会社東芝 ダイナミック型半導体記憶装置
JPH06309869A (ja) * 1993-04-28 1994-11-04 Oki Electric Ind Co Ltd 半導体記憶装置
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置

Also Published As

Publication number Publication date
KR19980032605A (ko) 1998-07-25
CN1181632A (zh) 1998-05-13
KR100499452B1 (ko) 2006-06-19
JP3712150B2 (ja) 2005-11-02
TW348316B (en) 1998-12-21
JPH10134570A (ja) 1998-05-22
US5905685A (en) 1999-05-18

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