GB9725367D0 - Dynamic memory allocation - Google Patents

Dynamic memory allocation

Info

Publication number
GB9725367D0
GB9725367D0 GBGB9725367.8A GB9725367A GB9725367D0 GB 9725367 D0 GB9725367 D0 GB 9725367D0 GB 9725367 A GB9725367 A GB 9725367A GB 9725367 D0 GB9725367 D0 GB 9725367D0
Authority
GB
United Kingdom
Prior art keywords
dynamic memory
memory allocation
allocation
dynamic
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB9725367.8A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3Com Ireland
Original Assignee
3Com Ireland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3Com Ireland filed Critical 3Com Ireland
Priority to GBGB9725367.8A priority Critical patent/GB9725367D0/en
Publication of GB9725367D0 publication Critical patent/GB9725367D0/en
Priority to PCT/GB1998/003574 priority patent/WO1999028816A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9021—Plurality of buffers per packet
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9036—Common buffer combined with individual queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
GBGB9725367.8A 1997-11-28 1997-11-28 Dynamic memory allocation Ceased GB9725367D0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GBGB9725367.8A GB9725367D0 (en) 1997-11-28 1997-11-28 Dynamic memory allocation
PCT/GB1998/003574 WO1999028816A1 (en) 1997-11-28 1998-11-30 Dynamic memory allocation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9725367.8A GB9725367D0 (en) 1997-11-28 1997-11-28 Dynamic memory allocation

Publications (1)

Publication Number Publication Date
GB9725367D0 true GB9725367D0 (en) 1998-01-28

Family

ID=10822905

Family Applications (1)

Application Number Title Priority Date Filing Date
GBGB9725367.8A Ceased GB9725367D0 (en) 1997-11-28 1997-11-28 Dynamic memory allocation

Country Status (2)

Country Link
GB (1) GB9725367D0 (en)
WO (1) WO1999028816A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19841447A1 (en) 1998-09-10 2000-03-16 Siemens Ag Method of transferring data via several parallel interfaces
KR20190086177A (en) * 2018-01-12 2019-07-22 에스케이하이닉스 주식회사 The controller and the operation method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381645A3 (en) * 1989-01-18 1992-08-05 International Business Machines Corporation System and method for communicating between a plurality of processors
GB2267588B (en) * 1992-06-06 1996-03-20 Motorola Inc FIFO memory system

Also Published As

Publication number Publication date
WO1999028816A1 (en) 1999-06-10

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)