SG45266A1 - Semiconductor device having a flag with opening - Google Patents

Semiconductor device having a flag with opening

Info

Publication number
SG45266A1
SG45266A1 SG1996002292A SG1996002292A SG45266A1 SG 45266 A1 SG45266 A1 SG 45266A1 SG 1996002292 A SG1996002292 A SG 1996002292A SG 1996002292 A SG1996002292 A SG 1996002292A SG 45266 A1 SG45266 A1 SG 45266A1
Authority
SG
Singapore
Prior art keywords
flag
opening
semiconductor device
semiconductor
Prior art date
Application number
SG1996002292A
Other languages
English (en)
Inventor
Frank Djennas
Alan H Woosley
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of SG45266A1 publication Critical patent/SG45266A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
SG1996002292A 1992-07-27 1993-06-01 Semiconductor device having a flag with opening SG45266A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/919,442 US5233222A (en) 1992-07-27 1992-07-27 Semiconductor device having window-frame flag with tapered edge in opening

Publications (1)

Publication Number Publication Date
SG45266A1 true SG45266A1 (en) 1998-01-16

Family

ID=25442089

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996002292A SG45266A1 (en) 1992-07-27 1993-06-01 Semiconductor device having a flag with opening

Country Status (5)

Country Link
US (1) US5233222A (ko)
EP (1) EP0580987A1 (ko)
JP (1) JP3504297B2 (ko)
KR (1) KR100296531B1 (ko)
SG (1) SG45266A1 (ko)

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JP2957335B2 (ja) * 1991-10-29 1999-10-04 ローム株式会社 リードフレームの製造方法
JPH0794539A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd 半導体装置
JPH0878605A (ja) * 1994-09-01 1996-03-22 Hitachi Ltd リードフレームおよびそれを用いた半導体集積回路装置
DE4433689C2 (de) * 1994-09-21 1996-07-11 Siemens Ag Chipkonfiguration und Verwendung eines entsprechenden Chips
SE514116C2 (sv) 1994-10-19 2001-01-08 Ericsson Telefon Ab L M Förfarande för framställning av en kapslad optokomponent, gjutform för kapsling av en optokomponent och tryckanordning för gjutform
JP2767404B2 (ja) * 1994-12-14 1998-06-18 アナムインダストリアル株式会社 半導体パッケージのリードフレーム構造
DE19506958C2 (de) * 1995-02-28 1998-09-24 Siemens Ag Halbleitervorrichtung mit gutem thermischen Verhalten
DE19536525B4 (de) * 1995-09-29 2005-11-17 Infineon Technologies Ag Leiterrahmen für integrierte Schaltungen
EP0833382B1 (en) * 1996-09-30 2005-11-30 STMicroelectronics S.r.l. Plastic package for electronic devices
KR100216064B1 (ko) * 1996-10-04 1999-08-16 윤종용 반도체 칩 패키지
JP3012816B2 (ja) * 1996-10-22 2000-02-28 松下電子工業株式会社 樹脂封止型半導体装置およびその製造方法
KR100205353B1 (ko) * 1996-12-27 1999-07-01 구본준 프리-몰드 패들을 갖는 반도체 패키지 제조 공정용 리드 프레임
TW330337B (en) * 1997-05-23 1998-04-21 Siliconware Precision Industries Co Ltd Semiconductor package with detached die pad
US5932924A (en) * 1998-02-02 1999-08-03 Motorola, Inc. Leadframe having continuously reducing width and semiconductor device including such a leadframe
JPH11307713A (ja) * 1998-04-24 1999-11-05 Sony Corp 半導体装置用リードフレーム
US6239480B1 (en) * 1998-07-06 2001-05-29 Clear Logic, Inc. Modified lead frame for improved parallelism of a die to package
JP2000058735A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd リードフレーム、半導体装置及び半導体装置の製造方法
US6753922B1 (en) * 1998-10-13 2004-06-22 Intel Corporation Image sensor mounted by mass reflow
US6677665B2 (en) 1999-01-18 2004-01-13 Siliconware Precision Industries Co., Ltd. Dual-die integrated circuit package
SG91808A1 (en) * 1999-02-09 2002-10-15 Inst Of Microelectronics Lead frame for an integrated circuit chip (small window)
JP2000280570A (ja) 1999-03-31 2000-10-10 Brother Ind Ltd 画像形成装置
KR100350046B1 (ko) 1999-04-14 2002-08-24 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 방열판이 부착된 반도체패키지
TW410452B (en) * 1999-04-28 2000-11-01 Siliconware Precision Industries Co Ltd Semiconductor package having dual chips attachment on the backs and the manufacturing method thereof
US7034382B2 (en) * 2001-04-16 2006-04-25 M/A-Com, Inc. Leadframe-based chip scale package
US6512286B1 (en) 2001-10-09 2003-01-28 Siliconware Precision Industries Co., Ltd. Semiconductor package with no void in encapsulant and method for fabricating the same
US6809408B2 (en) 2002-01-31 2004-10-26 Siliconware Precision Industries Co., Ltd. Semiconductor package with die pad having recessed portion
US6996897B2 (en) * 2002-07-31 2006-02-14 Freescale Semiconductor, Inc. Method of making a mount for electronic devices
TWI267958B (en) * 2002-11-21 2006-12-01 Siliconware Precision Industries Co Ltd Semiconductor package with stilts for supporting dice
US7012324B2 (en) 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Lead frame with flag support structure
MY136216A (en) * 2004-02-13 2008-08-29 Semiconductor Components Ind Method of forming a leadframe for a semiconductor package
KR100586699B1 (ko) * 2004-04-29 2006-06-08 삼성전자주식회사 반도체 칩 패키지와 그 제조 방법
JP2005327830A (ja) * 2004-05-13 2005-11-24 Mitsubishi Electric Corp 半導体マイクロデバイス
US8138586B2 (en) * 2005-05-06 2012-03-20 Stats Chippac Ltd. Integrated circuit package system with multi-planar paddle
JP4668729B2 (ja) * 2005-08-17 2011-04-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4518113B2 (ja) * 2007-07-25 2010-08-04 Ｔｄｋ株式会社 電子部品内蔵基板及びその製造方法
US7839004B2 (en) * 2008-07-30 2010-11-23 Sanyo Electric Co., Ltd. Semiconductor device, semiconductor module, method for manufacturing semiconductor device, and lead frame
JP5167203B2 (ja) * 2009-06-29 2013-03-21 ルネサスエレクトロニクス株式会社 半導体装置
TWI595608B (zh) * 2013-12-23 2017-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP2016018979A (ja) * 2014-07-11 2016-02-01 株式会社デンソー モールドパッケージ
KR20170064594A (ko) * 2015-12-01 2017-06-12 삼성디스플레이 주식회사 전자 소자의 실장 방법 및 이에 사용되는 언더 필 필름
US10049969B1 (en) * 2017-06-16 2018-08-14 Allegro Microsystems, Llc Integrated circuit
JP7109347B2 (ja) * 2018-12-03 2022-07-29 三菱電機株式会社 半導体装置および電力変換装置
CN112236100B (zh) * 2019-04-15 2024-01-02 柯惠Lp公司 校准手术机器人的器械驱动单元的转矩传感器的方法

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Also Published As

Publication number Publication date
JP3504297B2 (ja) 2004-03-08
EP0580987A1 (en) 1994-02-02
JPH0697354A (ja) 1994-04-08
US5233222A (en) 1993-08-03
KR940003005A (ko) 1994-02-19
KR100296531B1 (ko) 2001-10-24

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