SG173283A1 - Method for manufacturing soi substrate - Google Patents

Method for manufacturing soi substrate Download PDF

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Publication number
SG173283A1
SG173283A1 SG2011004652A SG2011004652A SG173283A1 SG 173283 A1 SG173283 A1 SG 173283A1 SG 2011004652 A SG2011004652 A SG 2011004652A SG 2011004652 A SG2011004652 A SG 2011004652A SG 173283 A1 SG173283 A1 SG 173283A1
Authority
SG
Singapore
Prior art keywords
semiconductor wafer
heat treatment
wafer
insulating layer
manufacturing
Prior art date
Application number
SG2011004652A
Other languages
English (en)
Inventor
Kazuya Hanaoka
Hideki Tsuya
Yoshihiro Komatsu
Original Assignee
Semiconductor Energy Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of SG173283A1 publication Critical patent/SG173283A1/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • H10P36/20Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12Preparing bulk and homogeneous wafers
    • H10P90/16Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
SG2011004652A 2010-01-26 2011-01-21 Method for manufacturing soi substrate SG173283A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010014880 2010-01-26

Publications (1)

Publication Number Publication Date
SG173283A1 true SG173283A1 (en) 2011-08-29

Family

ID=44309256

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2011004652A SG173283A1 (en) 2010-01-26 2011-01-21 Method for manufacturing soi substrate

Country Status (3)

Country Link
US (1) US8367517B2 (https=)
JP (1) JP5719611B2 (https=)
SG (1) SG173283A1 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5799740B2 (ja) * 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
JP2013093434A (ja) * 2011-10-26 2013-05-16 Semiconductor Energy Lab Co Ltd 半導体基板の解析方法
JP2014082316A (ja) 2012-10-16 2014-05-08 Shin Etsu Handotai Co Ltd Soiウェーハの製造方法
JP2014107357A (ja) * 2012-11-26 2014-06-09 Shin Etsu Handotai Co Ltd Soiウェーハの製造方法
WO2015064338A1 (ja) * 2013-10-31 2015-05-07 独立行政法人科学技術振興機構 ゲルマニウム層を熱処理する半導体基板の製造方法および半導体装置の製造方法
JP6366383B2 (ja) * 2014-06-27 2018-08-01 株式会社ディスコ 加工装置
KR101911764B1 (ko) * 2014-11-05 2018-10-26 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 게르마늄층을 채널 영역으로 하는 반도체 장치 및 그 제조 방법
US9620376B2 (en) * 2015-08-19 2017-04-11 Lam Research Corporation Self limiting lateral atomic layer etch
DE102016000051A1 (de) * 2016-01-05 2017-07-06 Siltectra Gmbh Verfahren und Vorrichtung zum planaren Erzeugen von Modifikationen in Festkörpern
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
KR101820680B1 (ko) * 2016-12-05 2018-01-22 에스케이실트론 주식회사 반도체 기판 제조 방법
KR102376841B1 (ko) 2017-11-02 2022-03-18 쇼와 덴코 가부시키가이샤 에칭 방법 및 반도체의 제조 방법
CN110544668B (zh) * 2018-05-28 2022-03-25 沈阳硅基科技有限公司 一种通过贴膜改变soi边缘stir的方法
DE102020107236B4 (de) * 2019-09-30 2023-05-04 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zum herstellen eines halbleiter-auf-isolator(soi)-substrats
US11710656B2 (en) 2019-09-30 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor-on-insulator (SOI) substrate
CN116223183B (zh) * 2023-03-31 2026-02-03 洛阳中硅高科技有限公司 硅基体消解液、有机硅烷痕量金属杂质的检测方法以及试剂盒
FR3163205A1 (fr) * 2024-06-10 2025-12-12 Soitec Procédé de fabrication d’une plaquette donneuse pour le transfert de couches minces, et plaquette donneuse

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2635450B2 (ja) * 1991-03-26 1997-07-30 信越半導体株式会社 中性子照射用原料czシリコン単結晶
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3697106B2 (ja) 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP2001144275A (ja) 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせsoiウエーハの製造方法および貼り合わせsoiウエーハ
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
FR2858875B1 (fr) * 2003-08-12 2006-02-10 Soitec Silicon On Insulator Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse
US7563697B2 (en) * 2003-09-05 2009-07-21 Sumco Corporation Method for producing SOI wafer
KR101111436B1 (ko) * 2004-09-13 2012-02-15 신에쯔 한도타이 가부시키가이샤 Soi 웨이퍼의 제조 방법 및 soi 웨이퍼
JP2006294737A (ja) * 2005-04-07 2006-10-26 Sumco Corp Soi基板の製造方法及びその製造における剥離ウェーハの再生処理方法。
JP4715470B2 (ja) * 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
US7829436B2 (en) * 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
EP1835533B1 (en) * 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate
FR2899380B1 (fr) * 2006-03-31 2008-08-29 Soitec Sa Procede de revelation de defauts cristallins dans un substrat massif.
JP5314838B2 (ja) 2006-07-14 2013-10-16 信越半導体株式会社 剥離ウェーハを再利用する方法
JP5289805B2 (ja) 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 半導体装置製造用基板の作製方法
JP5459899B2 (ja) * 2007-06-01 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20090061593A1 (en) * 2007-08-28 2009-03-05 Kishor Purushottam Gadkaree Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment
JP5522917B2 (ja) 2007-10-10 2014-06-18 株式会社半導体エネルギー研究所 Soi基板の製造方法
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Also Published As

Publication number Publication date
JP2011176293A (ja) 2011-09-08
US8367517B2 (en) 2013-02-05
US20110183445A1 (en) 2011-07-28
JP5719611B2 (ja) 2015-05-20

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