SG150557A1 - System and method pertaining to semiconductor dies - Google Patents
System and method pertaining to semiconductor diesInfo
- Publication number
- SG150557A1 SG150557A1 SG200901436-6A SG2009014366A SG150557A1 SG 150557 A1 SG150557 A1 SG 150557A1 SG 2009014366 A SG2009014366 A SG 2009014366A SG 150557 A1 SG150557 A1 SG 150557A1
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor die
- semiconductor dies
- method pertaining
- signal
- hole
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/94—Laser ablative material removal
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/789,637 US7842948B2 (en) | 2004-02-27 | 2004-02-27 | Flip chip semiconductor die internal signal access system and method |
Publications (1)
Publication Number | Publication Date |
---|---|
SG150557A1 true SG150557A1 (en) | 2009-03-30 |
Family
ID=34887325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200901436-6A SG150557A1 (en) | 2004-02-27 | 2005-02-23 | System and method pertaining to semiconductor dies |
Country Status (5)
Country | Link |
---|---|
US (3) | US7842948B2 (zh) |
CN (1) | CN100490142C (zh) |
SG (1) | SG150557A1 (zh) |
TW (1) | TWI363183B (zh) |
WO (1) | WO2005088715A1 (zh) |
Families Citing this family (45)
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KR20190092584A (ko) | 2016-12-29 | 2019-08-07 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | 집적된 수동 컴포넌트를 구비한 접합된 구조체 |
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US10923408B2 (en) | 2017-12-22 | 2021-02-16 | Invensas Bonding Technologies, Inc. | Cavity packages |
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TWI270953B (en) * | 2005-08-17 | 2007-01-11 | Advanced Semiconductor Eng | Substrate and testing method thereof |
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JP2008122159A (ja) * | 2006-11-09 | 2008-05-29 | Toshiba Corp | 半導体集積回路 |
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JP4696227B2 (ja) | 2007-12-28 | 2011-06-08 | スパンション エルエルシー | 半導体装置の製造方法 |
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-
2004
- 2004-02-27 US US10/789,637 patent/US7842948B2/en not_active Expired - Lifetime
-
2005
- 2005-02-23 SG SG200901436-6A patent/SG150557A1/en unknown
- 2005-02-23 WO PCT/US2005/005671 patent/WO2005088715A1/en active Application Filing
- 2005-02-23 TW TW094105396A patent/TWI363183B/zh active
- 2005-02-23 CN CNB2005800032124A patent/CN100490142C/zh active Active
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2007
- 2007-12-28 US US12/005,716 patent/US8357931B2/en active Active
-
2013
- 2013-01-22 US US13/747,386 patent/US8951814B2/en not_active Expired - Lifetime
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US8357931B2 (en) | 2013-01-22 |
CN100490142C (zh) | 2009-05-20 |
US20050191770A1 (en) | 2005-09-01 |
TW200535942A (en) | 2005-11-01 |
US20080128695A1 (en) | 2008-06-05 |
CN1914726A (zh) | 2007-02-14 |
US8951814B2 (en) | 2015-02-10 |
US20130221354A1 (en) | 2013-08-29 |
US7842948B2 (en) | 2010-11-30 |
TWI363183B (en) | 2012-05-01 |
WO2005088715A1 (en) | 2005-09-22 |
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