SG11201810017VA - Semiconductor die offset compensation variation - Google Patents

Semiconductor die offset compensation variation

Info

Publication number
SG11201810017VA
SG11201810017VA SG11201810017VA SG11201810017VA SG11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA
Authority
SG
Singapore
Prior art keywords
international
shift measurement
semiconductor die
new york
new
Prior art date
Application number
SG11201810017VA
Other languages
English (en)
Inventor
Charles Andrew Coots
John Joseph Pichura
Maxim Factourovich
Original Assignee
Universal Instruments Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universal Instruments Corp filed Critical Universal Instruments Corp
Publication of SG11201810017VA publication Critical patent/SG11201810017VA/en

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41885—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by modeling, simulation of the manufacturing system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/45—Nc applications
    • G05B2219/45031—Manufacturing semiconductor wafers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Quality & Reliability (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
  • Semiconductor Integrated Circuits (AREA)
SG11201810017VA 2016-06-02 2017-06-02 Semiconductor die offset compensation variation SG11201810017VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662344820P 2016-06-02 2016-06-02
PCT/US2017/035714 WO2017210576A1 (en) 2016-06-02 2017-06-02 Semiconductor die offset compensation variation

Publications (1)

Publication Number Publication Date
SG11201810017VA true SG11201810017VA (en) 2018-12-28

Family

ID=60477971

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201810017VA SG11201810017VA (en) 2016-06-02 2017-06-02 Semiconductor die offset compensation variation

Country Status (9)

Country Link
US (1) US11156993B2 (zh)
JP (1) JP7138569B2 (zh)
KR (1) KR102443310B1 (zh)
CN (1) CN109429528B (zh)
DE (1) DE112017002802T5 (zh)
MY (1) MY196886A (zh)
SE (1) SE544800C2 (zh)
SG (1) SG11201810017VA (zh)
WO (1) WO2017210576A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE544800C2 (en) 2016-06-02 2022-11-22 Universal Instruments Corp Semiconductor die offset compensation variation
US11187992B2 (en) * 2017-10-23 2021-11-30 Applied Materials, Inc. Predictive modeling of metrology in semiconductor processes
CN113822009A (zh) * 2021-09-18 2021-12-21 武汉精创电子技术有限公司 晶粒排布方案自动生成方法、装置和系统

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US6625497B2 (en) * 2000-11-20 2003-09-23 Applied Materials Inc. Semiconductor processing module with integrated feedback/feed forward metrology
US6802045B1 (en) * 2001-04-19 2004-10-05 Advanced Micro Devices, Inc. Method and apparatus for incorporating control simulation environment
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US6965432B2 (en) * 2002-06-07 2005-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Non-invasive wafer transfer position diagnosis and calibration
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WO2004109793A1 (ja) * 2003-05-30 2004-12-16 Ebara Corporation 試料検査装置及び方法並びに該試料検査装置及び方法を用いたデバイス製造方法
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JP5077770B2 (ja) * 2006-03-07 2012-11-21 株式会社ニコン デバイス製造方法、デバイス製造システム及び測定検査装置
JP4873230B2 (ja) * 2006-05-19 2012-02-08 株式会社ニコン 露光方法、露光装置、計測方法及び計測装置
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US20080074678A1 (en) * 2006-09-26 2008-03-27 Tokyo Electron Limited Accuracy of optical metrology measurements
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SE544800C2 (en) 2016-06-02 2022-11-22 Universal Instruments Corp Semiconductor die offset compensation variation

Also Published As

Publication number Publication date
SE1851419A1 (en) 2018-11-14
JP2019522357A (ja) 2019-08-08
KR20190015243A (ko) 2019-02-13
US11156993B2 (en) 2021-10-26
US20200301404A1 (en) 2020-09-24
MY196886A (en) 2023-05-08
CN109429528B (zh) 2023-07-07
CN109429528A (zh) 2019-03-05
WO2017210576A1 (en) 2017-12-07
KR102443310B1 (ko) 2022-09-14
DE112017002802T5 (de) 2019-03-14
JP7138569B2 (ja) 2022-09-16
SE544800C2 (en) 2022-11-22

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