SG11201810017VA - Semiconductor die offset compensation variation - Google Patents

Semiconductor die offset compensation variation

Info

Publication number
SG11201810017VA
SG11201810017VA SG11201810017VA SG11201810017VA SG11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA SG 11201810017V A SG11201810017V A SG 11201810017VA
Authority
SG
Singapore
Prior art keywords
international
shift measurement
semiconductor die
new york
new
Prior art date
Application number
SG11201810017VA
Inventor
Charles Andrew Coots
John Joseph Pichura
Maxim Factourovich
Original Assignee
Universal Instruments Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universal Instruments Corp filed Critical Universal Instruments Corp
Publication of SG11201810017VA publication Critical patent/SG11201810017VA/en

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM]
    • G05B19/41885—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM] characterised by modeling, simulation of the manufacturing system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/45—Nc applications
    • G05B2219/45031—Manufacturing semiconductor wafers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Abstract

International Patent Classification: (71) Applicant: UNIVERSAL INSTRUMENTS CORPO- H01L 21/68 (2006.01) G06F 17/50 (2006.01) RATION [US/US]; 33 Broome Corporate Parkway, Con- G06F 13/10 (2006.01) H01L 21/66 (2006.01) klin, New York 13748 (US). G06F 17/30 (2006.01) H01L 21/67 (2006.01) (72) Inventors: COOTS, Charles Andrew; 1236 Cherese (21) International Application Number: PCT/US2017/035714 (22) International Filing Date: 02 June 2017 (02.06.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/344,820 02 June 2016 (02.06.2016) US Lane, Binghamton, New York 13905 (US). PICHURA, John Joseph; 100 Overlook Drive, Kirkwood, New York 13795 (US). FACTOUROVICH, Maxim; 43 San Marco Drive, Johnson City, New York 13790 (US). (74) Agent: OLSEN, Arlen L.; SCHMEISER, OLSEN & WATTS LLP, 22 Century Hill Drive, Suite 302, Latham, New York 12110 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, Circuitry/ Icgic 12 Controller 14 Memory Sy 8 Software Application 17 23.. Placement Hardware 19 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 07 December 2017 (07.12.2017) WIPO I PCT (54) Title: SEMICONDUCTOR DIE OFFSET COMPENSATION VARIATION 104 omit VIII tun Hol olollm ioo mom° oimIE (10) International Publication Number WO 2017/210576 Al 100 Network 14 N O N _ N O N C FIG. 1 (57) : A method and system for improving an automated pick and place apparatus semiconductor device placement process is provided. The method includes automatically executing a shift measurement associated with an offset from an original placement of a plurality of semiconductor die of a semiconductor wafer for processing. An associated shift measurement value is retrieved and stored in a database that includes previously retrieved shift measurement values of previously measured shift measurements. Specified models are executed with respect to all shift measurement values and a predicted shift measurement value associated with a future offset for a new plurality of semiconductor die on a new semiconductor wafer for processing is determined. Placement hardware of the pick and place apparatus is placed in multiple positions for generating the new plurality of semiconductor die on the new semiconductor wafer in accordance with the predicted shift measurement value. [Continued on next page] WO 2017/210576 Al MIDEDIMOMOIDEIRMEM001101011EMEROMEMOIMIE HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))
SG11201810017VA 2016-06-02 2017-06-02 Semiconductor die offset compensation variation SG11201810017VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662344820P 2016-06-02 2016-06-02
PCT/US2017/035714 WO2017210576A1 (en) 2016-06-02 2017-06-02 Semiconductor die offset compensation variation

Publications (1)

Publication Number Publication Date
SG11201810017VA true SG11201810017VA (en) 2018-12-28

Family

ID=60477971

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201810017VA SG11201810017VA (en) 2016-06-02 2017-06-02 Semiconductor die offset compensation variation

Country Status (9)

Country Link
US (1) US11156993B2 (en)
JP (1) JP7138569B2 (en)
KR (1) KR102443310B1 (en)
CN (1) CN109429528B (en)
DE (1) DE112017002802T5 (en)
MY (1) MY196886A (en)
SE (1) SE544800C2 (en)
SG (1) SG11201810017VA (en)
WO (1) WO2017210576A1 (en)

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US11187992B2 (en) * 2017-10-23 2021-11-30 Applied Materials, Inc. Predictive modeling of metrology in semiconductor processes
CN113822009A (en) * 2021-09-18 2021-12-21 武汉精创电子技术有限公司 Automatic generation method, device and system for crystal grain arrangement scheme

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Also Published As

Publication number Publication date
MY196886A (en) 2023-05-08
DE112017002802T5 (en) 2019-03-14
SE1851419A1 (en) 2018-11-14
US11156993B2 (en) 2021-10-26
US20200301404A1 (en) 2020-09-24
SE544800C2 (en) 2022-11-22
JP7138569B2 (en) 2022-09-16
JP2019522357A (en) 2019-08-08
CN109429528B (en) 2023-07-07
WO2017210576A1 (en) 2017-12-07
KR20190015243A (en) 2019-02-13
KR102443310B1 (en) 2022-09-14
CN109429528A (en) 2019-03-05

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