SG11201701659RA - Storage device - Google Patents
Storage deviceInfo
- Publication number
- SG11201701659RA SG11201701659RA SG11201701659RA SG11201701659RA SG11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA
- Authority
- SG
- Singapore
- Prior art keywords
- storage device
- storage
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2014/074330 WO2016038748A1 (ja) | 2014-09-12 | 2014-09-12 | 記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201701659RA true SG11201701659RA (en) | 2017-04-27 |
Family
ID=55458532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201701659RA SG11201701659RA (en) | 2014-09-12 | 2014-09-12 | Storage device |
Country Status (6)
Country | Link |
---|---|
US (1) | US10359961B2 (ja) |
JP (1) | JP6374008B2 (ja) |
CN (1) | CN106688039B (ja) |
SG (1) | SG11201701659RA (ja) |
TW (1) | TWI582786B (ja) |
WO (1) | WO2016038748A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10489324B2 (en) * | 2017-08-25 | 2019-11-26 | Qualcomm Incorporated | Systems and methods for port management |
US10468313B2 (en) * | 2017-09-26 | 2019-11-05 | Micron Technology, Inc. | Apparatuses and methods for TSV resistance and short measurement in a stacked device |
US11716073B2 (en) * | 2021-04-07 | 2023-08-01 | Mediatek Inc. | Chip with pad tracking |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5625593A (en) * | 1990-03-28 | 1997-04-29 | Mitsubishi Denki Kabushiki Kaisha | Memory card circuit with separate buffer chips |
US5159598A (en) * | 1990-05-03 | 1992-10-27 | General Electric Company | Buffer integrated circuit providing testing interface |
TW231343B (ja) | 1992-03-17 | 1994-10-01 | Hitachi Seisakusyo Kk | |
KR0157886B1 (ko) * | 1995-07-22 | 1999-03-20 | 문정환 | 반도체 메모리의 입력 버퍼 회로 |
US5774472A (en) * | 1997-05-30 | 1998-06-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of realizing stable test mode operation |
JP3431473B2 (ja) | 1997-12-11 | 2003-07-28 | 東芝マイクロエレクトロニクス株式会社 | ロジック混載メモリ及びそのテスト方法 |
JP2000315772A (ja) * | 1999-04-30 | 2000-11-14 | Fujitsu Ltd | 半導体集積回路装置 |
JP3779524B2 (ja) * | 2000-04-20 | 2006-05-31 | 株式会社東芝 | マルチチップ半導体装置及びメモリカード |
US20020088003A1 (en) * | 2000-06-27 | 2002-07-04 | Dror Salee | MAC redundancy in cable network headend |
US6732304B1 (en) * | 2000-09-21 | 2004-05-04 | Inapac Technology, Inc. | Chip testing within a multi-chip semiconductor package |
JP4419049B2 (ja) | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
JP4358056B2 (ja) | 2004-07-28 | 2009-11-04 | 東芝メモリシステムズ株式会社 | 半導体メモリ |
US7133798B1 (en) * | 2004-10-18 | 2006-11-07 | Inapac Technology, Inc. | Monitoring signals between two integrated circuit devices within a single package |
JP4309368B2 (ja) * | 2005-03-30 | 2009-08-05 | エルピーダメモリ株式会社 | 半導体記憶装置 |
DE112006002300B4 (de) | 2005-09-02 | 2013-12-19 | Google, Inc. | Vorrichtung zum Stapeln von DRAMs |
JP4901286B2 (ja) | 2006-04-24 | 2012-03-21 | 株式会社東芝 | 半導体装置及びメモリ回路システム |
JP5559507B2 (ja) | 2009-10-09 | 2014-07-23 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びこれを備える情報処理システム |
JP5595708B2 (ja) | 2009-10-09 | 2014-09-24 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその調整方法並びにデータ処理システム |
JP2011081884A (ja) | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体記憶装置及びこれを備える情報処理システム |
JP2011081730A (ja) | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム |
JP2011180848A (ja) | 2010-03-01 | 2011-09-15 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム、並びに、半導体装置を制御するコントローラ |
KR20110128047A (ko) | 2010-05-20 | 2011-11-28 | 삼성전자주식회사 | 3차원 적층 구조를 갖는 반도체 장치 및 데이터 디스큐잉 방법 |
JP5647026B2 (ja) | 2011-02-02 | 2014-12-24 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法 |
JP2012255704A (ja) | 2011-06-08 | 2012-12-27 | Elpida Memory Inc | 半導体装置 |
KR20130011138A (ko) * | 2011-07-20 | 2013-01-30 | 삼성전자주식회사 | 모노 랭크와 멀티 랭크로 호환 가능한 메모리 장치 |
KR101900423B1 (ko) | 2011-09-19 | 2018-09-21 | 삼성전자주식회사 | 반도체 메모리 장치 |
JP2013105512A (ja) * | 2011-11-15 | 2013-05-30 | Elpida Memory Inc | 半導体装置 |
JP2013134794A (ja) | 2011-12-26 | 2013-07-08 | Elpida Memory Inc | 半導体装置 |
US9087613B2 (en) * | 2012-02-29 | 2015-07-21 | Samsung Electronics Co., Ltd. | Device and method for repairing memory cell and memory system including the device |
KR101889509B1 (ko) * | 2012-04-20 | 2018-09-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 포함하는 반도체 시스템 |
CN102890859A (zh) | 2012-09-24 | 2013-01-23 | 西安博昱新能源有限公司 | 太阳能光伏发电反馈系统 |
KR102005814B1 (ko) * | 2013-04-02 | 2019-08-01 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치를 포함하는 반도체 시스템 |
KR20170036850A (ko) * | 2015-09-18 | 2017-04-03 | 에스케이하이닉스 주식회사 | 멀티 칩 패키지, 멀티 칩 패키지 시스템 및 멀티 칩 패키지의 테스트 방법 |
-
2014
- 2014-09-12 SG SG11201701659RA patent/SG11201701659RA/en unknown
- 2014-09-12 JP JP2016547650A patent/JP6374008B2/ja active Active
- 2014-09-12 CN CN201480081761.2A patent/CN106688039B/zh active Active
- 2014-09-12 US US15/507,822 patent/US10359961B2/en active Active
- 2014-09-12 WO PCT/JP2014/074330 patent/WO2016038748A1/ja active Application Filing
-
2015
- 2015-03-02 TW TW104106552A patent/TWI582786B/zh active
Also Published As
Publication number | Publication date |
---|---|
JP6374008B2 (ja) | 2018-08-15 |
US10359961B2 (en) | 2019-07-23 |
US20170286000A1 (en) | 2017-10-05 |
WO2016038748A1 (ja) | 2016-03-17 |
CN106688039A (zh) | 2017-05-17 |
JPWO2016038748A1 (ja) | 2017-06-29 |
CN106688039B (zh) | 2019-03-12 |
TWI582786B (zh) | 2017-05-11 |
TW201611029A (zh) | 2016-03-16 |
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