SG11201701659RA - Storage device - Google Patents

Storage device

Info

Publication number
SG11201701659RA
SG11201701659RA SG11201701659RA SG11201701659RA SG11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA SG 11201701659R A SG11201701659R A SG 11201701659RA
Authority
SG
Singapore
Prior art keywords
storage device
storage
Prior art date
Application number
SG11201701659RA
Inventor
Mikihiko Ito
Masaru Koyanagi
Shintaro Hayashi
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of SG11201701659RA publication Critical patent/SG11201701659RA/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • G06F3/0635Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625Power saving in storage systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656Data buffering arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0683Plurality of storage devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
SG11201701659RA 2014-09-12 2014-09-12 Storage device SG11201701659RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/074330 WO2016038748A1 (en) 2014-09-12 2014-09-12 Storage device

Publications (1)

Publication Number Publication Date
SG11201701659RA true SG11201701659RA (en) 2017-04-27

Family

ID=55458532

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201701659RA SG11201701659RA (en) 2014-09-12 2014-09-12 Storage device

Country Status (6)

Country Link
US (1) US10359961B2 (en)
JP (1) JP6374008B2 (en)
CN (1) CN106688039B (en)
SG (1) SG11201701659RA (en)
TW (1) TWI582786B (en)
WO (1) WO2016038748A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10489324B2 (en) * 2017-08-25 2019-11-26 Qualcomm Incorporated Systems and methods for port management
US10468313B2 (en) 2017-09-26 2019-11-05 Micron Technology, Inc. Apparatuses and methods for TSV resistance and short measurement in a stacked device
US11716073B2 (en) 2021-04-07 2023-08-01 Mediatek Inc. Chip with pad tracking

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TW231343B (en) 1992-03-17 1994-10-01 Hitachi Seisakusyo Kk
KR0157886B1 (en) * 1995-07-22 1999-03-20 문정환 Input buffer circuit
US5774472A (en) * 1997-05-30 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of realizing stable test mode operation
JP3431473B2 (en) 1997-12-11 2003-07-28 東芝マイクロエレクトロニクス株式会社 Logic embedded memory and test method thereof
JP2000315772A (en) * 1999-04-30 2000-11-14 Fujitsu Ltd Semiconductor integrated circuit device
JP3779524B2 (en) * 2000-04-20 2006-05-31 株式会社東芝 Multi-chip semiconductor device and memory card
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JP4358056B2 (en) 2004-07-28 2009-11-04 東芝メモリシステムズ株式会社 Semiconductor memory
US7133798B1 (en) * 2004-10-18 2006-11-07 Inapac Technology, Inc. Monitoring signals between two integrated circuit devices within a single package
JP4309368B2 (en) * 2005-03-30 2009-08-05 エルピーダメモリ株式会社 Semiconductor memory device
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JP4901286B2 (en) 2006-04-24 2012-03-21 株式会社東芝 Semiconductor device and memory circuit system
JP5559507B2 (en) 2009-10-09 2014-07-23 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and information processing system including the same
JP2011081730A (en) 2009-10-09 2011-04-21 Elpida Memory Inc Semiconductor device and information processing system including the same
JP2011081884A (en) 2009-10-09 2011-04-21 Elpida Memory Inc Semiconductor memory device and information processing system equipped with the same
JP5595708B2 (en) 2009-10-09 2014-09-24 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device, adjustment method thereof, and data processing system
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Also Published As

Publication number Publication date
JP6374008B2 (en) 2018-08-15
CN106688039B (en) 2019-03-12
WO2016038748A1 (en) 2016-03-17
US20170286000A1 (en) 2017-10-05
TWI582786B (en) 2017-05-11
TW201611029A (en) 2016-03-16
JPWO2016038748A1 (en) 2017-06-29
CN106688039A (en) 2017-05-17
US10359961B2 (en) 2019-07-23

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