SG11201604259PA - High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device - Google Patents

High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device

Info

Publication number
SG11201604259PA
SG11201604259PA SG11201604259PA SG11201604259PA SG11201604259PA SG 11201604259P A SG11201604259P A SG 11201604259PA SG 11201604259P A SG11201604259P A SG 11201604259PA SG 11201604259P A SG11201604259P A SG 11201604259PA SG 11201604259P A SG11201604259P A SG 11201604259PA
Authority
SG
Singapore
Prior art keywords
radio
silicon substrate
passive device
integrated passive
frequency
Prior art date
Application number
SG11201604259PA
Other languages
English (en)
Inventor
Atte Haapalinna
Original Assignee
Okmetic Oyj
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Okmetic Oyj filed Critical Okmetic Oyj
Publication of SG11201604259PA publication Critical patent/SG11201604259PA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07771—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card the record carrier comprising means for minimising adverse effects on the data communication capability of the record carrier, e.g. minimising Eddy currents induced in a proximate metal or otherwise electromagnetically interfering object
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
SG11201604259PA 2013-11-26 2014-11-26 High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device SG11201604259PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20136180A FI130149B (sv) 2013-11-26 2013-11-26 Högresistivt kiselsubstrat med minskad radiofrekvensförlust för en radiofrekvensintegrerad passiv anordning
PCT/FI2014/050910 WO2015079111A1 (en) 2013-11-26 2014-11-26 High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device

Publications (1)

Publication Number Publication Date
SG11201604259PA true SG11201604259PA (en) 2016-07-28

Family

ID=53181953

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201604259PA SG11201604259PA (en) 2013-11-26 2014-11-26 High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device

Country Status (9)

Country Link
US (1) US9312345B2 (sv)
EP (2) EP3872856A1 (sv)
JP (1) JP6438024B2 (sv)
KR (1) KR102284688B1 (sv)
CN (1) CN105993072B (sv)
FI (1) FI130149B (sv)
SG (1) SG11201604259PA (sv)
TW (1) TWI638454B (sv)
WO (1) WO2015079111A1 (sv)

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DE112016002435T5 (de) * 2015-05-29 2018-02-22 Analog Devices Inc. Galliumnitridapparat mit einer an Fangstellen reichen Region
CN105261586B (zh) * 2015-08-25 2018-05-25 上海新傲科技股份有限公司 带有电荷陷阱和绝缘埋层衬底的制备方法
EP3580776B1 (en) * 2017-02-10 2021-04-28 GlobalWafers Co., Ltd. Methods for assessing semiconductor structures
FR3066858B1 (fr) * 2017-05-23 2019-06-21 Soitec Procede pour minimiser une distorsion d'un signal dans un circuit radiofrequence
CN109103582A (zh) * 2018-08-29 2018-12-28 河海大学常州校区 薄膜体声波谐振器结构的纳米机械声学天线及制造方法
FI129826B (sv) * 2020-10-08 2022-09-15 Okmetic Oy Förfarande för framställning av en hög resistiv kiselskiva för en hybridsubstratkonstruktion
US20220115226A1 (en) * 2020-10-08 2022-04-14 Okmetic Oy Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure
TWI761255B (zh) * 2021-07-08 2022-04-11 環球晶圓股份有限公司 晶圓及晶圓的製造方法
US20230245922A1 (en) * 2022-01-17 2023-08-03 Psemi Corporation Methods for simultaneous generation of a trap-rich layer and a box layer

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US5559359A (en) * 1994-07-29 1996-09-24 Reyes; Adolfo C. Microwave integrated circuit passive element structure and method for reducing signal propagation losses
US6388290B1 (en) * 1998-06-10 2002-05-14 Agere Systems Guardian Corp. Single crystal silicon on polycrystalline silicon integrated circuits
KR20060118437A (ko) * 2003-09-26 2006-11-23 위니베르시트카솔리끄드루뱅 저항손을 감소시키는 다층 반도체 구조의 제조 방법
US7936043B2 (en) * 2006-03-17 2011-05-03 Sychip Inc. Integrated passive device substrates
US8378384B2 (en) 2007-09-28 2013-02-19 Infineon Technologies Ag Wafer and method for producing a wafer
US7868419B1 (en) * 2007-10-18 2011-01-11 Rf Micro Devices, Inc. Linearity improvements of semiconductor substrate based radio frequency devices
CN101447417A (zh) * 2007-11-27 2009-06-03 上海华虹Nec电子有限公司 高电阻多晶硅形成方法
US20090236689A1 (en) 2008-03-24 2009-09-24 Freescale Semiconductor, Inc. Integrated passive device and method with low cost substrate
JP2009252822A (ja) * 2008-04-02 2009-10-29 Sumco Corp シリコンウェーハ及びその製造方法
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
JP5922860B2 (ja) * 2009-06-19 2016-05-24 株式会社Sumco 高抵抗シリコンウェーハの製造方法
JP2010219210A (ja) 2009-03-16 2010-09-30 Renesas Electronics Corp 半導体装置およびその製造方法
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Also Published As

Publication number Publication date
US9312345B2 (en) 2016-04-12
JP2016541118A (ja) 2016-12-28
EP3075007A4 (en) 2017-06-07
JP6438024B2 (ja) 2018-12-19
EP3075007A1 (en) 2016-10-05
US20150145105A1 (en) 2015-05-28
TW201535716A (zh) 2015-09-16
KR20160089448A (ko) 2016-07-27
FI130149B (sv) 2023-03-15
CN105993072A (zh) 2016-10-05
FI20136180L (sv) 2015-05-27
KR102284688B1 (ko) 2021-08-02
TWI638454B (zh) 2018-10-11
WO2015079111A1 (en) 2015-06-04
EP3872856A1 (en) 2021-09-01
CN105993072B (zh) 2019-03-01

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