SG11201509256XA - Method of manufacturing bonded wafer - Google Patents

Method of manufacturing bonded wafer

Info

Publication number
SG11201509256XA
SG11201509256XA SG11201509256XA SG11201509256XA SG11201509256XA SG 11201509256X A SG11201509256X A SG 11201509256XA SG 11201509256X A SG11201509256X A SG 11201509256XA SG 11201509256X A SG11201509256X A SG 11201509256XA SG 11201509256X A SG11201509256X A SG 11201509256XA
Authority
SG
Singapore
Prior art keywords
bonded wafer
manufacturing bonded
manufacturing
wafer
bonded
Prior art date
Application number
SG11201509256XA
Other languages
English (en)
Inventor
Toru Ishizuka
Norihiro Kobayashi
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201509256XA publication Critical patent/SG11201509256XA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
SG11201509256XA 2013-05-29 2014-03-25 Method of manufacturing bonded wafer SG11201509256XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013113307A JP6086031B2 (ja) 2013-05-29 2013-05-29 貼り合わせウェーハの製造方法
PCT/JP2014/001680 WO2014192207A1 (ja) 2013-05-29 2014-03-25 貼り合わせウェーハの製造方法

Publications (1)

Publication Number Publication Date
SG11201509256XA true SG11201509256XA (en) 2015-12-30

Family

ID=51988262

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201509256XA SG11201509256XA (en) 2013-05-29 2014-03-25 Method of manufacturing bonded wafer

Country Status (8)

Country Link
US (1) US9735045B2 (ko)
EP (1) EP3007204B1 (ko)
JP (1) JP6086031B2 (ko)
KR (1) KR102022504B1 (ko)
CN (1) CN105264641B (ko)
SG (1) SG11201509256XA (ko)
TW (1) TWI549192B (ko)
WO (1) WO2014192207A1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3046877B1 (fr) * 2016-01-14 2018-01-19 Soitec Procede de lissage de la surface d'une structure
JP2019511834A (ja) * 2016-02-16 2019-04-25 ジーレイ スイッツァーランド エスアー 接合インターフェースを横断する電荷輸送のための構造、システムおよび方法
US20220048762A1 (en) * 2020-08-14 2022-02-17 Beijing Voyager Technology Co., Ltd. Void reduction on wafer bonding interface

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01307472A (ja) 1988-06-03 1989-12-12 Matsushita Electric Ind Co Ltd 押出コーティング装置
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3173926B2 (ja) * 1993-08-12 2001-06-04 株式会社半導体エネルギー研究所 薄膜状絶縁ゲイト型半導体装置の作製方法及びその半導体装置
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP4379943B2 (ja) * 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
WO2003009386A1 (fr) 2001-07-17 2003-01-30 Shin-Etsu Handotai Co.,Ltd. Procede de production de plaquettes de liaison
FR2858462B1 (fr) * 2003-07-29 2005-12-09 Soitec Silicon On Insulator Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique
EP1652230A2 (fr) * 2003-07-29 2006-05-03 S.O.I.Tec Silicon on Insulator Technologies Procede d' obtention d' une couche mince de qualite accrue par co-implantation et recuit thermique
FR2912258B1 (fr) 2007-02-01 2009-05-08 Soitec Silicon On Insulator "procede de fabrication d'un substrat du type silicium sur isolant"
JP5135935B2 (ja) * 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
TWI483350B (zh) * 2008-03-21 2015-05-01 Shinetsu Chemical Co SOI wafer manufacturing method and glass cleaning method
JP5276863B2 (ja) 2008-03-21 2013-08-28 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハ
JP5433567B2 (ja) 2008-04-01 2014-03-05 信越化学工業株式会社 Ｓｏｉ基板の製造方法
JP4666189B2 (ja) * 2008-08-28 2011-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
EP2161741B1 (en) * 2008-09-03 2014-06-11 Soitec Method for fabricating a semiconductor on insulator substrate with reduced SECCO defect density
JP2010098167A (ja) 2008-10-17 2010-04-30 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
US8043938B2 (en) 2009-05-14 2011-10-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and SOI substrate
JP2010278337A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 表面欠陥密度が少ないｓｏｓ基板
JP5703920B2 (ja) * 2011-04-13 2015-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
JP2013143407A (ja) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法

Also Published As

Publication number Publication date
KR102022504B1 (ko) 2019-09-18
EP3007204A4 (en) 2017-03-01
EP3007204B1 (en) 2021-09-29
JP6086031B2 (ja) 2017-03-01
KR20160013037A (ko) 2016-02-03
CN105264641A (zh) 2016-01-20
WO2014192207A1 (ja) 2014-12-04
CN105264641B (zh) 2018-01-12
US9735045B2 (en) 2017-08-15
TW201445636A (zh) 2014-12-01
EP3007204A1 (en) 2016-04-13
TWI549192B (zh) 2016-09-11
US20160079114A1 (en) 2016-03-17
JP2014232806A (ja) 2014-12-11

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