SG11201507884PA - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- SG11201507884PA SG11201507884PA SG11201507884PA SG11201507884PA SG11201507884PA SG 11201507884P A SG11201507884P A SG 11201507884PA SG 11201507884P A SG11201507884P A SG 11201507884PA SG 11201507884P A SG11201507884P A SG 11201507884PA SG 11201507884P A SG11201507884P A SG 11201507884PA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- manufacturing semiconductor
- manufacturing
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Adhesive Tapes (AREA)
- Adhesives Or Adhesive Processes (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013077167 | 2013-04-02 | ||
JP2014028129A JP2014210909A (en) | 2013-04-02 | 2014-02-18 | Manufacturing method of semiconductor device |
PCT/JP2014/058545 WO2014162951A1 (en) | 2013-04-02 | 2014-03-26 | Semiconductor device manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201507884PA true SG11201507884PA (en) | 2015-11-27 |
Family
ID=51658249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201507884PA SG11201507884PA (en) | 2013-04-02 | 2014-03-26 | Method of manufacturing semiconductor device |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP2014210909A (en) |
CN (1) | CN105074892A (en) |
SG (1) | SG11201507884PA (en) |
TW (1) | TW201501214A (en) |
WO (1) | WO2014162951A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5976073B2 (en) * | 2014-11-07 | 2016-08-23 | 日東電工株式会社 | Manufacturing method of semiconductor device |
EP3442010B1 (en) | 2016-03-29 | 2022-06-01 | Mitsui Chemicals Tohcello, Inc. | Adhesive film for use in semiconductor device manufacturing, and semiconductor device manufacturing method |
JP6849468B2 (en) | 2017-02-13 | 2021-03-24 | ファスフォードテクノロジ株式会社 | Semiconductor manufacturing equipment and manufacturing method of semiconductor equipment |
JP2019135753A (en) * | 2018-02-05 | 2019-08-15 | リンテック株式会社 | Adhesive sheet and method for manufacturing semiconductor device |
WO2019189142A1 (en) * | 2018-03-29 | 2019-10-03 | 住友ベークライト株式会社 | Particulate resin composition for sealing, semiconductor device and method for producing same |
WO2020217955A1 (en) * | 2019-04-26 | 2020-10-29 | 三井化学東セロ株式会社 | Adhesive film and method for manufacturing electronic device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5042297B2 (en) * | 2009-12-10 | 2012-10-03 | 日東電工株式会社 | Manufacturing method of semiconductor device |
JP5309352B2 (en) * | 2011-02-15 | 2013-10-09 | Tdk株式会社 | Interlayer insulation sheet for electronic component built-in module, electronic component built-in module, and method of manufacturing electronic component built-in module |
-
2014
- 2014-02-18 JP JP2014028129A patent/JP2014210909A/en active Pending
- 2014-03-26 WO PCT/JP2014/058545 patent/WO2014162951A1/en active Application Filing
- 2014-03-26 SG SG11201507884PA patent/SG11201507884PA/en unknown
- 2014-03-26 CN CN201480019319.7A patent/CN105074892A/en active Pending
- 2014-04-01 TW TW103112125A patent/TW201501214A/en unknown
Also Published As
Publication number | Publication date |
---|---|
CN105074892A (en) | 2015-11-18 |
TW201501214A (en) | 2015-01-01 |
WO2014162951A1 (en) | 2014-10-09 |
JP2014210909A (en) | 2014-11-13 |
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