SG11201508969QA - Method for producing hybrid substrate, and hybrid substrate - Google Patents

Method for producing hybrid substrate, and hybrid substrate

Info

Publication number
SG11201508969QA
SG11201508969QA SG11201508969QA SG11201508969QA SG11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA
Authority
SG
Singapore
Prior art keywords
hybrid substrate
producing
substrate
producing hybrid
hybrid
Prior art date
Application number
SG11201508969QA
Other languages
English (en)
Inventor
Yuji Tobisaka
Shoji Akiyama
Yoshihiro Kubota
Makoto Kawai
Kazutoshi Nagata
Original Assignee
Shinetsu Chemical Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Chemical Co filed Critical Shinetsu Chemical Co
Publication of SG11201508969QA publication Critical patent/SG11201508969QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
SG11201508969QA 2013-05-01 2014-04-21 Method for producing hybrid substrate, and hybrid substrate SG11201508969QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013096512 2013-05-01
PCT/JP2014/061807 WO2014178356A1 (ja) 2013-05-01 2014-04-21 ハイブリッド基板の製造方法及びハイブリッド基板

Publications (1)

Publication Number Publication Date
SG11201508969QA true SG11201508969QA (en) 2015-12-30

Family

ID=51843484

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201508969QA SG11201508969QA (en) 2013-05-01 2014-04-21 Method for producing hybrid substrate, and hybrid substrate

Country Status (7)

Country Link
US (1) US9741603B2 (zh)
EP (1) EP2993686B1 (zh)
JP (1) JP6168143B2 (zh)
KR (1) KR102229397B1 (zh)
CN (1) CN105190835B (zh)
SG (1) SG11201508969QA (zh)
WO (1) WO2014178356A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3034252B1 (fr) * 2015-03-24 2018-01-19 Soitec Procede de reduction de la contamination metallique sur la surface d'un substrat
US10014271B2 (en) * 2015-11-20 2018-07-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
JP6549054B2 (ja) 2016-02-02 2019-07-24 信越化学工業株式会社 複合基板および複合基板の製造方法
US11361969B2 (en) 2017-07-14 2022-06-14 Shin-Etsu Chemical Co., Ltd. Device substrate with high thermal conductivity and method of manufacturing the same
US11211259B2 (en) 2018-04-20 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for embedded gettering in a silicon on insulator wafer
FR3087297B1 (fr) * 2018-10-12 2021-01-08 Commissariat Energie Atomique Procede de transfert de film mince
US11232974B2 (en) * 2018-11-30 2022-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication method of metal-free SOI wafer
KR102250895B1 (ko) * 2019-12-23 2021-05-12 주식회사 현대케피코 반도체 소자의 제조방법
CN112599470A (zh) * 2020-12-08 2021-04-02 上海新昇半导体科技有限公司 一种绝缘体上硅结构及其方法
KR102427718B1 (ko) 2021-01-11 2022-08-01 주식회사 트랜스코스모스코리아 양방향 화면공유를 통한 보이는 고객상담서비스 시스템 및 방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
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JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
JP2895743B2 (ja) * 1994-03-25 1999-05-24 信越半導体株式会社 Ｓｏｉ基板の製造方法
US6417108B1 (en) * 1998-02-04 2002-07-09 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
KR100401655B1 (ko) * 2001-01-18 2003-10-17 주식회사 컴텍스 ALE를 이용한 알루미나(Al₂O₃) 유전체 층 형성에 의한 스마트 공정을 이용한 유니본드형 SOI 웨이퍼의 제조방법
JPWO2003046993A1 (ja) * 2001-11-29 2005-04-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP4720163B2 (ja) * 2004-12-02 2011-07-13 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの製造方法
FR2935536B1 (fr) * 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
FR2938702B1 (fr) * 2008-11-19 2011-03-04 Soitec Silicon On Insulator Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
FR2938975B1 (fr) * 2008-11-24 2010-12-31 Soitec Silicon On Insulator Procede de realisation d'une heterostructure de type silicium sur saphir
JP5443833B2 (ja) * 2009-05-29 2014-03-19 信越化学工業株式会社 貼り合わせｓｏｉ基板の製造方法
FR2950734B1 (fr) 2009-09-28 2011-12-09 Soitec Silicon On Insulator Procede de collage et de transfert d'une couche
FR2954585B1 (fr) * 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
FR2957190B1 (fr) * 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
CN102130037B (zh) * 2010-12-27 2013-03-13 上海新傲科技股份有限公司 采用吸杂工艺制备带有绝缘埋层的半导体衬底的方法
WO2012088710A1 (zh) * 2010-12-27 2012-07-05 上海新傲科技股份有限公司 采用吸杂工艺制备带有绝缘埋层的半导体衬底的方法
JP5926527B2 (ja) * 2011-10-17 2016-05-25 信越化学工業株式会社 透明ｓｏｉウェーハの製造方法
US10103021B2 (en) 2012-01-12 2018-10-16 Shin-Etsu Chemical Co., Ltd. Thermally oxidized heterogeneous composite substrate and method for manufacturing same
JP6160616B2 (ja) * 2012-07-25 2017-07-12 信越化学工業株式会社 Ｓｏｓ基板の製造方法及びｓｏｓ基板

Also Published As

Publication number Publication date
EP2993686B1 (en) 2021-05-26
US20160071761A1 (en) 2016-03-10
KR102229397B1 (ko) 2021-03-17
KR20160002814A (ko) 2016-01-08
WO2014178356A1 (ja) 2014-11-06
EP2993686A4 (en) 2016-11-30
US9741603B2 (en) 2017-08-22
EP2993686A1 (en) 2016-03-09
CN105190835B (zh) 2018-11-09
JP6168143B2 (ja) 2017-07-26
CN105190835A (zh) 2015-12-23
JPWO2014178356A1 (ja) 2017-02-23

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