SG11201407361PA - Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer - Google Patents

Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer

Info

Publication number
SG11201407361PA
SG11201407361PA SG11201407361PA SG11201407361PA SG11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA
Authority
SG
Singapore
Prior art keywords
semiconductor layer
international
thickness
semiconductor
layer
Prior art date
Application number
SG11201407361PA
Other languages
English (en)
Inventor
Walter Schwarzenbach
Carine Duret
François Boedt
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201407361PA publication Critical patent/SG11201407361PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
SG11201407361PA 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer SG11201407361PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1254841A FR2991099B1 (fr) 2012-05-25 2012-05-25 Procede de traitement d'une structure semi-conducteur sur isolant en vue d'uniformiser l'epaisseur de la couche semi-conductrice
PCT/IB2013/000857 WO2013175278A1 (fr) 2012-05-25 2013-05-01 Procédé de traitement d'une structure de semi-conducteur sur isolant afin d'améliorer l'uniformité de l'épaisseur de la couche semi-conductrice

Publications (1)

Publication Number Publication Date
SG11201407361PA true SG11201407361PA (en) 2014-12-30

Family

ID=48536940

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201407361PA SG11201407361PA (en) 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer

Country Status (7)

Country Link
US (1) US9190284B2 (fr)
KR (1) KR102068189B1 (fr)
CN (1) CN104380447B (fr)
DE (1) DE112013002675T5 (fr)
FR (1) FR2991099B1 (fr)
SG (1) SG11201407361PA (fr)
WO (1) WO2013175278A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2995444B1 (fr) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator Procede de detachement d'une couche
JP6354363B2 (ja) * 2014-06-12 2018-07-11 富士通セミコンダクター株式会社 半導体装置の製造方法
US10373838B2 (en) * 2015-12-08 2019-08-06 Elemental Scientific, Inc. Automatic sampling of hot phosphoric acid for the determination of chemical element concentrations and control of semiconductor processes
JP6673173B2 (ja) * 2016-12-12 2020-03-25 三菱電機株式会社 半導体装置の製造方法
FR3106236B1 (fr) 2020-01-15 2021-12-10 Soitec Silicon On Insulator Procédé de fabrication d’un capteur d’image

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213657A (en) * 1991-07-31 1993-05-25 Shin-Etsu Handotai Kabushiki Kaisha Method for making uniform the thickness of a si single crystal thin film
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP2000173976A (ja) * 1998-12-02 2000-06-23 Mitsubishi Electric Corp 半導体装置の製造方法
US20040087042A1 (en) * 2002-08-12 2004-05-06 Bruno Ghyselen Method and apparatus for adjusting the thickness of a layer of semiconductor material
JP4684650B2 (ja) 2002-08-12 2011-05-18 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ 薄層を形成する方法、犠牲酸化によって厚みを補正するステップを含む方法、及び関連する機械
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer
DE102004054566B4 (de) * 2004-11-11 2008-04-30 Siltronic Ag Verfahren und Vorrichtung zum Einebnen einer Halbleiterscheibe sowie Halbleiterscheibe mit verbesserter Ebenheit
JP2006216826A (ja) * 2005-02-04 2006-08-17 Sumco Corp Ｓｏｉウェーハの製造方法
EP2095406A1 (fr) * 2006-12-26 2009-09-02 S.O.I.Tec Silicon on Insulator Technologies Procédé de production d'une structure semiconducteur sur isolant
DE102007006151B4 (de) * 2007-02-07 2008-11-06 Siltronic Ag Verfahren zur Verringerung und Homogenisierung der Dicke einer Halbleiterschicht, die sich auf der Oberfläche eines elektrisch isolierenden Materials befindet
FR2912839B1 (fr) 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
US7972969B2 (en) * 2008-03-06 2011-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for thinning a substrate

Also Published As

Publication number Publication date
KR20150021499A (ko) 2015-03-02
WO2013175278A1 (fr) 2013-11-28
FR2991099A1 (fr) 2013-11-29
US9190284B2 (en) 2015-11-17
US20150118764A1 (en) 2015-04-30
FR2991099B1 (fr) 2014-05-23
CN104380447B (zh) 2017-05-03
DE112013002675T5 (de) 2015-03-19
CN104380447A (zh) 2015-02-25
KR102068189B1 (ko) 2020-01-20

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