SG11201407361PA - Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer - Google Patents

Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer

Info

Publication number
SG11201407361PA
SG11201407361PA SG11201407361PA SG11201407361PA SG11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA SG 11201407361P A SG11201407361P A SG 11201407361PA
Authority
SG
Singapore
Prior art keywords
semiconductor layer
international
thickness
semiconductor
layer
Prior art date
Application number
SG11201407361PA
Inventor
Walter Schwarzenbach
Carine Duret
François Boedt
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201407361PA publication Critical patent/SG11201407361PA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 28 November 2013 (28.11.2013) WIPOIPCT (10) International Publication Number WO 2013/175278 A1 (51) International Patent Classification: H01L 21/66 (2006.01) (21) International Application Number: (22) International Filing Date: (25) Filing Language: (26) Publication Language: PCT/IB2013/000857 1 May 2013 (01.05.2013) English English (30) Priority Data: 1254841 25 May 2012 (25.05.2012) FR (71) Applicant: SOITEC [FR/FR]; Chemin des Franques - Pare Technologique des Fontaines, F-38190 BERNIN (FR). (72) Inventors: SCHWARZENBACH, Walter; 19 CHEMIN DU MOLLARD, F-38330 SAINT NAZAIRE LES EYMES (FR). DURET, Carine; 18 av du General Cham- pon, F-38000 GRENOBLE (FR). BOEDT, Francois; 3 Allee des Frenes, F-38240 MEYLAN (FR). (81) Designated States (unless otherwise indicated, for every kind of national protection available)'. AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available)'. ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3)) (54) Title: PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE FOR IMPROVING THICK­ NESS UNIFORMITY OF THE SEMICONDUCTOR LAYER FIG. 5 30-, 20- 10- 0- ry -15 A -10 A r -5 A A oo i> CJ i> i-H cn i-H o CJ o & et +5 A o e mean (A) +10 A +15 A (57) Abstract: The invention relates to a process for treating structure of semiconductor-on-insulator type a successively comprising a support substrate (1), a dielectric layer (2) and a semiconductor layer (3) having a thickness of less than or equal to 100 nm, said semiconductor layer (3) being covered with a sacrificial oxide layer (4), comprising: measuring, at a plurality of points distributed over the surface of the, structure, the thickness of the sacrificial oxide layer (4) and of the semiconductor layer (3), so as to produce a mapping of the thickness of the semiconductor layer (3) and to determine, from said measurements, the average thickness of the semiconductor layer (3), selective etching of the sacrificial oxide layer (4) so as to expose the semiconductor layer (3), and carrying out chemical a etching of the semiconductor layer (3), the application, temperature and/or duration conditions of which are adjusted as a function of said mapping and/or of the mean thickness of the semiconductor layer (3), so as to thin, at least locally, said semi - conductor layer (3) by a thickness identified as being an overthickness at the end of the measurement step.
SG11201407361PA 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer SG11201407361PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1254841A FR2991099B1 (en) 2012-05-25 2012-05-25 PROCESS FOR PROCESSING A SEMICONDUCTOR STRUCTURE ON AN INSULATION FOR THE UNIFORMIZATION OF THE THICKNESS OF THE SEMICONDUCTOR LAYER
PCT/IB2013/000857 WO2013175278A1 (en) 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer

Publications (1)

Publication Number Publication Date
SG11201407361PA true SG11201407361PA (en) 2014-12-30

Family

ID=48536940

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201407361PA SG11201407361PA (en) 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer

Country Status (7)

Country Link
US (1) US9190284B2 (en)
KR (1) KR102068189B1 (en)
CN (1) CN104380447B (en)
DE (1) DE112013002675T5 (en)
FR (1) FR2991099B1 (en)
SG (1) SG11201407361PA (en)
WO (1) WO2013175278A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2995444B1 (en) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator METHOD FOR DETACHING A LAYER
JP6354363B2 (en) * 2014-06-12 2018-07-11 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US10373838B2 (en) * 2015-12-08 2019-08-06 Elemental Scientific, Inc. Automatic sampling of hot phosphoric acid for the determination of chemical element concentrations and control of semiconductor processes
JP6673173B2 (en) * 2016-12-12 2020-03-25 三菱電機株式会社 Method for manufacturing semiconductor device
FR3106236B1 (en) 2020-01-15 2021-12-10 Soitec Silicon On Insulator Manufacturing process of an image sensor

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213657A (en) * 1991-07-31 1993-05-25 Shin-Etsu Handotai Kabushiki Kaisha Method for making uniform the thickness of a si single crystal thin film
FR2777115B1 (en) * 1998-04-07 2001-07-13 Commissariat Energie Atomique PROCESS FOR TREATING SEMICONDUCTOR SUBSTRATES AND STRUCTURES OBTAINED BY THIS PROCESS
JP2000173976A (en) 1998-12-02 2000-06-23 Mitsubishi Electric Corp Manufacture of semiconductor device
US20040087042A1 (en) * 2002-08-12 2004-05-06 Bruno Ghyselen Method and apparatus for adjusting the thickness of a layer of semiconductor material
AU2003263391A1 (en) 2002-08-12 2004-02-25 S.O.I.Tec Silicon On Insulator Technologies A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer
DE102004054566B4 (en) * 2004-11-11 2008-04-30 Siltronic Ag Method and device for leveling a semiconductor wafer and semiconductor wafer with improved flatness
JP2006216826A (en) * 2005-02-04 2006-08-17 Sumco Corp Manufacturing method of soi wafer
EP2095406A1 (en) * 2006-12-26 2009-09-02 S.O.I.Tec Silicon on Insulator Technologies Method for producing a semiconductor-on-insulator structure
DE102007006151B4 (en) * 2007-02-07 2008-11-06 Siltronic Ag A method of reducing and homogenizing the thickness of a semiconductor layer located on the surface of an electrically insulating material
FR2912839B1 (en) 2007-02-16 2009-05-15 Soitec Silicon On Insulator IMPROVING THE QUALITY OF COLD CLEANING INTERFACE BY COLD CLEANING AND HOT COLLAGE
US7972969B2 (en) * 2008-03-06 2011-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for thinning a substrate

Also Published As

Publication number Publication date
DE112013002675T5 (en) 2015-03-19
KR102068189B1 (en) 2020-01-20
US9190284B2 (en) 2015-11-17
WO2013175278A1 (en) 2013-11-28
CN104380447B (en) 2017-05-03
FR2991099B1 (en) 2014-05-23
FR2991099A1 (en) 2013-11-29
US20150118764A1 (en) 2015-04-30
KR20150021499A (en) 2015-03-02
CN104380447A (en) 2015-02-25

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