SG11201809911WA - Method for fabricating a strained semiconductor-on-insulator substrate - Google Patents

Method for fabricating a strained semiconductor-on-insulator substrate

Info

Publication number
SG11201809911WA
SG11201809911WA SG11201809911WA SG11201809911WA SG11201809911WA SG 11201809911W A SG11201809911W A SG 11201809911WA SG 11201809911W A SG11201809911W A SG 11201809911WA SG 11201809911W A SG11201809911W A SG 11201809911WA SG 11201809911W A SG11201809911W A SG 11201809911WA
Authority
SG
Singapore
Prior art keywords
layer
international
substrate
strained
monocrystalline
Prior art date
Application number
SG11201809911WA
Inventor
Walter Schwarzenbach
Guillaume Chabanne
Nicolas Daval
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201809911WA publication Critical patent/SG11201809911WA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , Organization 03 1111111111111111111111111111111111111111111111111111111111111111111111111111111 International Bureau (10) International Publication Number (43) International Publication Date .....•\"\" WO 2017/198686 Al 23 November 2017 (23.11.2017) WI PO I PCT (51) International Patent Classification: LE TOUVET (FR). DAVAL, Nicolas; Fontcouvert, 38570 HO1L 21/762 (2006.01) GONCELIN (FR). (21) International Application Number: (74) Agent: REGIMBEAU; 139 Rue Vendome, 69577 LYON PCT/EP2017/061792 CEDEX 06 (FR). (22) International Filing Date: (81) Designated States (unless otherwise indicated, for every 17 May 2017 (17.05.2017) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (25) Filing Language: English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (26) Publication Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, (30) Priority Data: KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, 1654368 17 May 2016 (17.05.2016) FR MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, (71) Applicant: SOITEC [FR/FR]; Parc Technologique des PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, Fontaines Chemin des Franques, 38190 BERNIN (FR). SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (72) Inventors: SCHWARZENBACH, Walter; 19, Chemin du Mollard, 38330 SAINT NAZAIRE LES EYMES (FR). (84) Designated States (unless otherwise indicated, for every CHABANNE, Guillaume; 34 Rue des Gaillardes, 38660 kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (54) Title: METHOD FOR FABRICATING A STRAINED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE = T sS01 T = ' Ai 1 13 = 11 an 23 20 = = 21 = = FIGURE 3G = = = = = (57) : The invention relates to a method for fabricating a strained semiconductor-on-insulator substrate, comprising: (a) the provision of a donor substrate (1) comprising a monocrystalline semiconductor layer (13); (b) the provision of a receiving substrate (2) comprising a surface layer (20) of a strained monocrystalline semiconductor material; (c) the bonding of the donor substrate (1) to — the receiving substrate (2), a dielectric layer (11, 22) being at the interface; (d) the transfer of the monocrystalline semiconductor layer Il (13) from the donor substrate (1) to the receiving substrate (2); (e) the cutting of a portion from a stack formed from the transferred Q l monocrystalline semiconductor layer (13), from the dielectric layer (11, 22) and from the strained semiconductor material layer (20), ,t: said cutting operation resulting in the relaxation of the strain in the strained semiconductor material, and in the application of at least a GO part of said strain to the transferred monocrystalline semiconductor layer. Step (b) additionally comprises the formation, on the strained of semiconductor material layer (20) of the receiving substrate (2), of a dielectric bonding layer (22) or of a bonding layer consisting of ON the same relaxed, or at least partially relaxed, monocrystalline material (23) as the monocrystalline semiconductor layer (13) of the Il donor substrate (1), and in that in step (c) said bonding layer (22, 23) is at the bonding interface between the donor substrate and the --.... t -- - receiving substrate. 1-1 0 ei C [Continued on next page] WO 2017/198686 Al MIDEDIMOMOIDEIROIDEMOMOHHEIHE11101111111111111111111 UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3))
SG11201809911WA 2016-05-17 2017-05-17 Method for fabricating a strained semiconductor-on-insulator substrate SG11201809911WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1654368A FR3051595B1 (en) 2016-05-17 2016-05-17 METHOD FOR MANUFACTURING A STRESSED-ON-INSULATOR SEMICONDUCTOR-TYPE SUBSTRATE
PCT/EP2017/061792 WO2017198686A1 (en) 2016-05-17 2017-05-17 Method for fabricating a strained semiconductor-on-insulator substrate

Publications (1)

Publication Number Publication Date
SG11201809911WA true SG11201809911WA (en) 2018-12-28

Family

ID=56322202

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201809911WA SG11201809911WA (en) 2016-05-17 2017-05-17 Method for fabricating a strained semiconductor-on-insulator substrate

Country Status (8)

Country Link
US (1) US10672646B2 (en)
EP (1) EP3459106B1 (en)
JP (1) JP6888028B2 (en)
CN (1) CN109155277B (en)
FR (1) FR3051595B1 (en)
SG (1) SG11201809911WA (en)
TW (1) TWI746555B (en)
WO (1) WO2017198686A1 (en)

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US10833194B2 (en) 2010-08-27 2020-11-10 Acorn Semi, Llc SOI wafers and devices with buried stressor
FR3051596B1 (en) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A STRESSED-ON-INSULATOR SEMICONDUCTOR-TYPE SUBSTRATE
US10903332B2 (en) 2018-08-22 2021-01-26 International Business Machines Corporation Fully depleted SOI transistor with a buried ferroelectric layer in back-gate
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
WO2023049172A1 (en) 2021-09-22 2023-03-30 Acorn Semi, Llc MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRENCHES BETWEEN GATES

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JP4521542B2 (en) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor substrate
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
JP2003158250A (en) * 2001-10-30 2003-05-30 Sharp Corp CMOS OF SiGe/SOI AND ITS MANUFACTURING METHOD
EP1523775B1 (en) * 2002-06-28 2013-07-31 Advanced Micro Devices, Inc. SOI field effect transistor element having a recombination region and method of forming same
FR2842350B1 (en) * 2002-07-09 2005-05-13 METHOD FOR TRANSFERRING A LAYER OF CONCEALED SEMICONDUCTOR MATERIAL
US6995427B2 (en) * 2003-01-29 2006-02-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
DE602004011353T2 (en) * 2004-10-19 2008-05-15 S.O.I. Tec Silicon On Insulator Technologies S.A. Method for producing a strained silicon layer on a substrate and intermediate product
JP4757519B2 (en) * 2005-03-25 2011-08-24 株式会社Ｓｕｍｃｏ Manufacturing method of strained Si-SOI substrate and strained Si-SOI substrate manufactured by the method
US7485539B2 (en) * 2006-01-13 2009-02-03 International Business Machines Corporation Strained semiconductor-on-insulator (sSOI) by a simox method
FR2903808B1 (en) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator PROCESS FOR DIRECTLY BONDING TWO SUBSTRATES USED IN ELECTRONIC, OPTICAL OR OPTOELECTRONIC
FR2912550A1 (en) * 2007-02-14 2008-08-15 Soitec Silicon On Insulator Strained silicon on insulator structure/plate fabricating method, involves contacting germanium layer with silicon layer which presents germanium concentration of thirty percent and duration of over-etching phase lower than twenty seconds
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Also Published As

Publication number Publication date
FR3051595A1 (en) 2017-11-24
TWI746555B (en) 2021-11-21
TW201806074A (en) 2018-02-16
FR3051595B1 (en) 2022-11-18
EP3459106A1 (en) 2019-03-27
US20190181035A1 (en) 2019-06-13
EP3459106B1 (en) 2023-07-19
JP2019521509A (en) 2019-07-25
US10672646B2 (en) 2020-06-02
EP3459106C0 (en) 2023-07-19
WO2017198686A1 (en) 2017-11-23
JP6888028B2 (en) 2021-06-16
CN109155277B (en) 2023-10-24
CN109155277A (en) 2019-01-04

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