JP2003158250A - CMOS OF SiGe/SOI AND ITS MANUFACTURING METHOD - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the structure of a simple SiGe/SOI and its forming method. SOLUTION: A method to form a SiGe/SOI structure contains a process in which an on-insulator silicon substrate comprising a buried oxide layer is provided, a process in which a silicon germanium layer is deposited on the substrate and a process in which the silicon germanium layer on the substrate is annealed for a time of at least 1 sec at a temperature of at least 1,050 deg.C. The process in which the silicon germanium layer is annealed is conducted for the time within a range of 1 to 10 sec at the temperature of at least 1,100 deg.C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high speed CMOS integrated circuits, and more particularly to silicon on insulator (SO
I) A high speed CMOS integrated circuit including a relaxed silicon germanium (SiGe) layer on a buried oxide (BOX) and having a low defect density.

[0002]

Silicon germanium (SiGe) metal oxide semiconductor (MOS) transistors are fabricated on surface strained silicon and buried strained silicon structures.
The device typically consists of a thick film layer of graded Si _1-x Ge _x , with x varying between ₁ μm and 2 μm relaxed SiGe layer with 0.0 at the bottom and 0.3 at the top. In the case of a surface strained MOS transistor, a relaxed Si _1-x Ge _x layer of 50 nm to 150 nm is grown on the graded SiGe, and then a strained silicon epitaxial layer is grown.
For buried strained MOS transistors, an additional layer of SiGe is deposited on the strained silicon layer. With this structure, field effect mobility can be increased by 80% from that of pure silicon devices. 4 for pMOST devices
Field hole mobilities of 00 cm ² / Vs have been achieved.
In particular, Applicants have obtained an enhancement of more than 50% on the effective hole mobility in a silicon cap channel on pMOST with strained SiGe.

Similar structure, but with relaxed graded SiG
SiGe / SOI transistors fabricated on (including buried silicon oxide in the e-layer) have also been fabricated. The hole mobility and electron mobility gains of this SiGe / SOI structure are 45% and 60% higher than those of the comparable silicon transistor, respectively. This structure is very complicated and its crystal defect density is too high, which makes it unsuitable for large-scale integrated circuit applications.

S. T. Hsu and T.W. Nakada
, "Ge-Si," granted on March 10, 1998.
SOI MOS Transistor and M
method for Fabricating Sam
e ", U.S. Pat. No. 5,726,459
A device in which ion implantation is used to form a silicon layer doped with e is disclosed (see Patent Document 1). The Ge ion doping amount is very large, and the implantation time is long. Moreover, the silicon layer can be completely amorphized during Ge ion implantation and cannot be recrystallized. Therefore, a high quality SiGe film cannot be reliably obtained using the methods disclosed in the above patents.

[0005]

[Patent Document 1] US Pat. No. 5,726,459

[0006]

Therefore, a simple S
iGe / SOI structure is required. Further, there is a need for such a simple method of manufacturing a SiGe / SOI CMOS structure.

Therefore, the object of the present invention is to simplify SiGe.
/ SOI structure and method of generating it.

Another object of the present invention is to provide a high speed CMOS integrated circuit and a method of manufacturing the same, which circuit comprises relaxed silicon on silicon on insulator (SOI) oxide (BOX). Germanium (SiG
It is a structure including e).

[0009]

SiGe / according to the present invention
A method of forming an SOI structure includes providing a silicon-on-insulator substrate that includes a buried oxide layer, depositing a silicon germanium layer on the substrate, and depositing the silicon germanium layer on the substrate at a temperature of at least 1050 ° C. Annealing at temperature for a time of at least 1 second, thereby achieving the above objectives.

The step of annealing the silicon germanium layer is performed at a temperature of at least 1100 ° C. for 1-10.
The time may be in the range of seconds.

The step of annealing the silicon germanium layer is performed at a temperature of at least 1150 ° C. for 1-10.
The time may be in the range of seconds.

Prior to the step of annealing the silicon germanium layer on the substrate at a temperature of at least 1050 ° C., the silicon germanium layer is heated to 550 ° C. to 1050 ° C.
Annealing may be performed at a temperature in the range of 0.5 to 4.0 hours.

The silicon germanium layer is Si _1-X.
Ge _X is included, where x may range from 0.1 to 0.9.

The silicon germanium layer is Si _1-X.
Ge _X is included, where x may range from 0.2 to 0.5.

The method may further include growing a tensile strained silicon layer on the annealed silicon germanium layer.

The transistor produced by the above method according to the present invention comprises a relaxed silicon germanium layer and a tensile strained silicon layer located on the silicon germanium layer, thereby achieving the above object.

The method of forming a SiGe / SOI structure according to the present invention comprises providing a silicon-on-insulator substrate including a buried oxide layer, depositing the silicon-germanium layer on the substrate, and depositing the silicon-germanium layer on the substrate. The silicon germanium layer at a temperature in the range of 550 ° C. to 1050 ° C.
Performing a first annealing step including an annealing step for a time in the range of 4.0 hours, and annealing the silicon germanium layer on the substrate at a temperature of at least 1050 ° C. for a time of 1 to 10 seconds. Carrying out a second annealing step, which comprises:

The silicon germanium layer is Si _1-X.
Ge _X is included, where x may range from 0.1 to 0.9.

The method may further include growing a tensile strained silicon layer on the silicon germanium layer.

The method produces a transistor including the silicon germanium layer and the tensile strained silicon layer overlying the silicon germanium layer, which may be relaxed.

After the first annealing step, the silicon from the silicon germanium layer and the silicon-on-insulator substrate forms a silicon germanium layer defined by Si _1-y Ge _y (y is less than x). May be combined to

The second annealing step may be performed by a method selected from the group consisting of rapid thermal annealing, laser annealing, and optical annealing such as a flash lamp.

The method may produce a transistor including an upper silicon layer adapted for use as an nMOS channel.

The above method produces a transistor including an upper silicon layer overlying a silicon germanium layer,
The upper silicon layer and the silicon germanium layer may each be adapted for use as a pMOS channel.

The silicon germanium layer has a maximum thickness of 40 n
It may be deposited to a thickness of m.

According to the present invention, there is provided a transistor produced by the above method, thereby achieving the above object.

The present invention provides a simple SiGe / SOI structure and a method of manufacturing the same. In particular, a SiGe epitaxial layer is grown, followed by 550 ° C. to 105 ° C.
By performing diffusion annealing at a temperature in the range of 0 ° C., the upper silicon layer of SOI is transformed into Si _1-x Ge _x . The second annealing step, also referred to as the relaxation annealing step, is typically performed at a temperature in the range of 1050 ° C to 1200 ° C. This temperature treatment diffuses Ge, transforms the upper silicon layer into a relaxed SiGe layer and removes all defects in the SOI film. Therefore, a defect-free SiGe crystal is obtained. A cap epitaxial silicon layer is subsequently deposited on the SiGe layer. Since this silicon layer grows on relaxed SiGe, the upper silicon layer is a strained silicon layer. Therefore, higher electron and hole mobilities are obtained. The buried oxide interface functions as a buffer that relaxes SiGe. The graded SiGe layer is no longer needed. As a result, the defect density of this structure can be much lower than that of the prior art.

The manufacturing process is as follows. First,
The upper silicon layer of the SOI substrate is thinned to 10 nm to 30 nm. Second, Si _1-x Ge _x (0.2 <x <
The epitaxial layer of 0.5) is grown. This film thickness is usually 20 nm to 40 nm. Third, nMO
Boron and phosphorus are implanted into the p-well and n-well, respectively, to control the threshold voltage of ST and pMOST. Fourth, the above structure is added at 550 ° C.
Diffusion anneal at a temperature in the range of ° C for 0.5-4 hours.
Ge is diffused by this heat treatment, and the upper silicon film is changed to relaxed Si _1-x Ge _x . However, x need not be constant throughout this film. This heat treatment also
Remove some or all defects in the film. The second relaxation anneal step may be performed at a temperature in the range of 1050 ° C to 1200 ° C for a very short time of only a few seconds. Low defect density relaxed SiGe is obtained on an SOI wafer. Fifth, grow a cap silicon layer. Since the underlying SiGe is in a relaxed state, the cap silicon layer is in a tensile strain state in the lateral direction. Sixth,
A gate oxide is grown to form a first polysilicon layer (p
deposit ol y1). Seventh, photoresist is applied to protect the active areas. poly1, oxide and S
The iGe is then etched and the photoresist stripped. Eighth, a low temperature thermal oxide of 5 nm to 10 nm is grown. Then, CV of 50 nm to 200 nm
Deposit D oxide layer. Ninth, a plasma etch of oxide is performed to remove all oxide from the surface of poly1. This forms sidewall oxide in the active region. Tenth, 50 nm to 200 nm of polysilicon (poly2) is deposited. poly1 and pol
y2 combines to form the gate electrode. Eleventh, applying photoresist and etching the polysilicon gate electrode, the photoresist is stripped. In addition, photoresist is used for the source / drain implants. Twelfth, the passivation oxide and metallization layer are deposited. In this way, the final device is obtained.

During these steps, the amount of heat needs to be low to avoid Ge diffusion into the strained Si layer. Furthermore, it is well known that the reliability of thin film oxides grown on SiGe is not as good as the reliability of oxides grown on silicon. The amount of heat supplied by this process is low. Moreover, since there is no thin film gate oxide grown on the SiGe layer, the disadvantages of prior art processes and devices are avoided.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION The present application is filed on May 14, 2001, in "Enhanced Mobility N".
MOS and PMOS Transistor U
sing Strained Si / SiGe Lay
ers on Silicon-On-Insulat
or Substrates ", and claims priority to partially-pending US patent application Ser. No. 09 / 855,392.

FIG. 1 illustrates oxide, silicon and SiGe.
FIG. 6 is a cross-sectional view of the device during manufacture showing the layers. In particular, the method of the present invention grows a SiGe epitaxial layer and then deposits it at a temperature in the range of 550 ° C to 1050 ° C for 10 hours.
Minutes to 40 minutes by diffusion annealing.
A method of converting the upper silicon layer of the OI film into Si _1-x Ge _x is included. The second relaxation annealing step is 1050 ° C.
It can be carried out at temperatures in the range of up to 1200 ° C. for short times of a few seconds. The first annealing step diffuses Ge to form an at least partially relaxed, partially uniform SiGe layer. By the second annealing step, relaxed SiGe
A layer is obtained. This temperature treatment diffuses Ge, transforms the top silicon layer into a relaxed SiGe layer and minimizes any defects in the SOI film. In this way, a low defect density SiGe crystal is obtained. The SiGe is capped with an epitaxial silicon layer. Since this silicon layer grows on the relaxed SiGe layer, the upper silicon layer becomes a strained silicon layer. Therefore, higher electron and hole mobilities are obtained. The interface of the buried oxide functions as a buffer for relaxing SiGe. Tilt SiGe
Layers are no longer needed. As a result, the defect density of this structure is much lower than that of known structures of the prior art.

The first step of this manufacturing process involves providing a substrate 10 having an oxide layer 12 and a top silicon layer 14. The upper silicon layer 14 has a thickness of about 10 nm.
Thinned to a thickness 16 of 30 nm. Si _1-x Ge
_{The x} epitaxial layer 18 is grown on the upper silicon layer 14. However, x is in the range of 0.1 to 0.9, and preferably in the range of 0.2 to 0.5. Thickness of layer 18 20
Is usually about 20 nm to 40 nm.

FIG. 2 shows an oxide, pSiGe / nSiG.
FIG. 3E is a cross-sectional view of the device during fabrication showing the e, silicon oxide and polysilicon layers. This device is manufactured as follows. Boron and phosphorus ions are implanted to form p-well 22 and n-well 24, nM
The respective threshold voltages of the OST and pMOST are controlled. The structure is then diffusion annealed at a temperature in the range of 550 ° C to 1050 ° C for about 0.5 to 4 hours. This heat treatment diffuses Ge, and at least partially changes the upper silicon films 22 and 24 into relaxed Si _1-x Ge _x . However, x need not be constant throughout this film. A second relaxation anneal step is then typically performed 105
It is performed at a temperature in the range of 0 ° C to 1200 ° C for about 1 to 10 seconds. As a result of this step, the Si _1-y Ge _y layer becomes Si.
And a Si _1-x Ge _x layer. However, y
Is less than x. The Si _1-y Ge _y layer is usually relaxed. This second heat treatment also removes some or all defects in the SOI film. Furthermore, this second spike anneal relaxes the Si _1-y Ge _y layer. In this way, a relaxed SiGe layer with a low defect density is obtained on the SOI wafer. A thin film layer 25 of silicon having a thickness in the range of approximately 5 nm to 20 nm is epitaxially grown on the SiGe layer. Then, a gate oxide layer 26 is grown and a cap polysilicon layer 28 (po
ly1) is deposited on the SiGe layers 22 and 24.
The thickness of layer 28 is typically in the range 100 nm to 200 nm. The thin silicon layer 25 may be deposited before and after the second relaxation anneal step, also called the spike anneal step. In either method, the grown silicon layer 2
5 is typically a strained silicon layer 25.

FIG. 3 is a cross-sectional view of the device under fabrication showing the pMOS and nMOS regions. In particular, photoresist is applied to portions of active regions 22 and 24, poly1 layer 28, oxide layer 26, silicon layer 25.
And protect portions of these active regions 22 and 24 while etching the regions outside pSiGe region 22 and nSiGe region 24. Then, the photoresist is stripped off to obtain the active regions of the nMOS 30 and the pMOS 32.

In FIG. 4, the oxide layers are pMOS and nMO.
FIG. 5 is a cross-sectional view of the device during manufacturing showing the state of being deposited on the S region. Specifically, a low temperature calorific oxide layer is grown on the device of FIG. This low temperature calorific oxide layer is usually
It has a thickness of about 5 nm to 10 nm. The oxide layer 40 is
About 50 deposited by chemical vapor deposition (CVD)
It has a thickness 42 of nm to 200 nm.

FIG. 5 is a cross-sectional view of the device during fabrication showing the oxide layers on the pMOS and nMOS regions etched. Specifically, the oxide layer 40 is plasma etched to remove any oxide from the top surface of the poly1 layer 28. This forms sidewall oxide 44 on active regions 30 and 32.

FIG. 6 is a cross-sectional view of the device during fabrication showing the gate region. Specifically, a polysilicon layer 46 (poly2) is deposited on the device of FIG. poly
The bilayer 46 typically has a thickness 4 of about 100 nm to 200 nm.
Have eight. The poly2 and poly1 layers combine to form a gate electrode. A photoresist is then applied and the device is etched to provide polysilicon gate electrodes 50 and 52. Then, the photoresist is stripped. Additional photoresist may be used to implant the source and drain regions of layers 22 and 24. In one embodiment, each of source region 22a and drain region 22b of layer 22 is doped to be N +, while each of source region 24a and drain region 24b of layer 24 is doped to be P +.
You may Similarly, the gate electrode 50 may be N + and the gate electrode 52 may be P +.

FIG. 7 is a cross-sectional view of the device under fabrication showing the completed device. In particular, the process steps include depositing passivation oxide and then metallizing the device. As a result, the nMOS structure 6
0 and pMOS structure 62.

The amount of heat provided by the process of the present invention is
It should be low to avoid diffusion of Ge into the strained Si layer. Furthermore, it is well known that the reliability of oxide thin films grown on SiGe layers is not as good as those grown on silicon layers. The calorific value of the process disclosed herein is low and does not require a gate oxide thin film to be grown on SiGe. Therefore, a simple SiGe / SOI structure and its manufacturing method are provided. In particular, the present invention provides a high speed CMOS integrated circuit and method of manufacturing the same. The above circuit is formed by relaxing silicon germanium (S) on top of silicon-on-insulator (SOI) buried oxide (BOX).
iGe) layer, the defect density of this structure is low.

As mentioned above, a second relaxation annealing step is performed to provide a relaxed SiGe layer on top of the SOI buried oxide (BOX). The purpose of this method is also to relax the top silicon layer of the SOI wafer by Si.
_1-y Ge _y (where y is at least 0.15). The process begins with the step of growing a blanket Si _1-x Ge _x epitaxial layer, where x is greater than y. The film can then be patterned with photoresist and the top SiGe / Si film can be selectively etched down to the BOX. This leaves a separate SiGe / Si mesa, from which defects can be annealed and removed. Alternatively, the wafer may be unpatterned. Then, following this step, 550 ° C to 1050 ° C
Diffusion annealing is performed at a temperature in the range of about 0.5 to 4 hours. This temperature treatment diffuses Ge,
The upper silicon layer is transformed into a relaxed Si _1-y Ge _y layer.
Then, a second annealing step may be performed. In detail, a spike annealing process is then performed at a temperature in the range of 1050 ° C. to 1200 ° C. to completely diffuse,
Any defects in the SOI film can be eliminated or reduced. This spike or relaxation anneal step is typically performed for a short time, such as 10 seconds or less. In this way, a Si _1-y Ge _y crystal having a low defect density can be obtained. After this, Si _1-y Ge _y is capped with an epitaxial silicon layer. If the wafer is pre-patterned, it may be necessary to selectively deposit the epitaxial Si cap. Silicon layer is relaxed S
As grown on iGe, the top silicon layer is a strained silicon layer. Therefore, high electron and hole mobilities are obtained. The buried oxide interface functions as a buffer that relaxes SiGe. The graded SiGe layer is no longer needed. As a result, the defect density in this structure can be much lower than that of known structures in the prior art.

FIG. 8 is a flow chart showing the manufacturing process of the present invention. First, a substrate is provided. Step 70
Is about 10 nm to 30 nm on the upper silicon layer of the SOI substrate.
Including the step of thinning to a thickness of. Step 72 is Si
_The step of growing an epitaxial layer of _1-x Ge _x (0.2 <x <0.5) is included. This film thickness is usually 20n
It is m-40 nm. Step 74 consists of nMOST and p
For controlling the MOST threshold voltage, p-well and n-well
The step of implanting boron and phosphorus ions into each of the wells is included. Step 76 is 550 ° C. to 1050
Diffusion annealing the structure obtained in the above step at a temperature in the range of 0 ° C for a period of about 0.5-4 hours. Ge is diffused by this heat treatment, and the upper silicon layer is changed to a relaxed Si _{1- x} Ge _x layer. However, x need not be constant throughout the membrane. This heat treatment is also SOI
Remove or reduce some or all of the defects in the film. Second relaxation annealing step 78
Can be performed at temperatures in the range of 1050 ° C to 1200 ° C for a very short time of only a few seconds. The second relaxation annealing step may be performed by a method selected from the group consisting of rapid thermal annealing, laser annealing, and optical annealing such as flash lamps. A low defect density relaxed SiGe on an SOI wafer is obtained. Step 80 includes growing a cap silicon layer. In certain embodiments of the above method, the cap silicon layer 25 may be deposited prior to the second relaxation anneal step 78. Since the underlying SiGe is in a relaxed state, the cap silicon layer is laterally strained.
Step 82 includes growing a gate oxide and then depositing a first polysilicon layer (poly1).
Step 84 includes applying a photoresist to protect the active areas. Step 86 includes etching poly1, oxide and SiGe, then stripping the photoresist. Step 88 is 5 nm to 10 nm
Low temperature thermal oxide of 50 nm to 200 nm
nm deposition of a layer of CVD oxide. Process 9
0 includes the step of plasma etching the oxide to remove all oxide from the surface of poly1.
This forms a sidewall oxide on the active region. Process 9
2 is a 100 nm-200 nm polysilicon layer (po
ly2) is included. poly1 and po
ly2 joins to form the gate electrode. Step 94 includes applying a photoresist, etching the polysilicon gate electrode, and then stripping the photoresist. Additional resist is used for the source / drain implants. Step 96 includes depositing a passivation oxide and a metal layer. In this way, the final device is obtained.

During these steps, the amount of heat needs to be low to avoid Ge diffusion into the strained Si layer. Furthermore, it is well known that the reliability of thin film oxides grown on SiGe is not as good as the reliability of oxides grown on silicon. The amount of heat supplied by this process is low. Moreover, since there is no thin film gate oxide grown on the SiGe layer, the disadvantages of prior art processes and devices are avoided.

As described above, a transistor including a relaxed SiGe layer and a strained upper silicon layer on a silicon-on-insulator substrate and a method of manufacturing the same have been disclosed. While a preferred structure and method of manufacturing a device has been disclosed, it should be understood that further variations and modifications can be made without departing from the scope of the invention as defined by the claims set forth above. is there.

[0044]

As described above, the present invention provides a method of manufacturing a simple SiGe / SOI structure. In particular, a SiGe epitaxial layer is grown, followed by 55
By relaxation annealing at a temperature in the range of 0 ° C. to 1050 ° C., the upper silicon layer of SOI has a Si _1-x G 2 layer.
change to e _x . This temperature treatment relaxes the SiGe, transforms the top silicon layer into a relaxed SiGe layer and removes defects in the SOI film. Therefore, SiG with extremely low defect density
e crystals are obtained. This SiGe layer is capped with an epitaxial silicon layer. This silicon layer is relaxed Si
The upper silicon layer is a strained silicon layer because it is grown on Ge. Therefore, higher electron and hole mobilities are obtained. The buried oxide interface functions as a buffer that relaxes SiGe. The graded SiGe layer is no longer needed. As a result, the defect density of this structure is much lower than that of the prior art.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a device during manufacturing showing oxide, silicon and SiGe layers.

FIG. 2 is a cross-sectional view of a device during fabrication showing oxide, pSiGe / nSiGe, oxide and polysilicon layers.

FIG. 3 shows pMOS and nMOS regions,
FIG. 7 is a cross-sectional view of the device during manufacturing.

FIG. 4 is a cross-sectional view of the device during fabrication showing oxide layers deposited on the pMOS and nMOS regions.

FIG. 5 is a cross-sectional view of the device during fabrication showing the oxide layers on the pMOS and nMOS regions etched.

FIG. 6 is a cross-sectional view of the device during manufacturing showing the gate region.

FIG. 7 is a cross-sectional view of the device during manufacturing showing the completed device.

FIG. 8 is a flowchart showing a manufacturing process of the present invention.

[Explanation of symbols]

10 substrates 12 Oxide layer 22a source region 22b drain region 24a source area 24b drain region 25 Silicon thin layer 26 gate oxide layer 50, 52 Polysilicon gate electrode 60 nMOS structure 62 pMOS structure

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 27/092 H01L 29/78 618E 29/786 613A 618A (72) Inventor David Russell Evans United States Oregon 97007, Bi over Burton, S. W. over 179 tee Eichi Place 7574 F-term (reference) 5F048 AA07 AC03 BA02 BA14 BA16 BB05 BD04 BE03 5F052 JA04 KA01 5F110 AA01 AA26 BB04 CC02 DD05 DD13 EE09 EE14 EE32 EE33 EE42 FF02 GG01 GG02 GG06 GG19 GG25 GG32 GG42 GG52 GG58 HJ13 HL02 HL22 NN02 NN23 QQ11

Claims (18)

[Claims] 1. A method of forming a SiGe / SOI structure, comprising: providing a silicon-on-insulator substrate comprising a buried oxide layer; depositing a silicon-germanium layer on the substrate; At least 10 layers of said silicon germanium layer
Annealing at a temperature of 50 ° C. for a time of at least 1 second. 2. The step of annealing the silicon germanium layer comprises at least 1 to 1 at a temperature of at least 1100.degree.
The method of claim 1, wherein the method is performed for a time in the range of 0 seconds. 3. The step of annealing the silicon germanium layer comprises at least 1 to 1 at a temperature of 1150 ° C.
The method of claim 1, wherein the method is performed for a time in the range of 0 seconds. 4. The silicon germanium layer prior to the step of annealing the silicon germanium layer on the substrate at a temperature of at least 1050.degree.
The method of claim 1, wherein annealing is performed at a temperature in the range of 0 ° C. for a time in the range of 0.5 to 4.0 hours. 5. The silicon germanium layer is Si
The method of claim 1, comprising _1-X Ge _X , where x ranges from 0.1 to 0.9. 6. The silicon germanium layer is Si
The method of claim 1, comprising _1-X Ge _X , where x ranges from 0.2 to 0.5. 7. The method of claim 1, further comprising growing a tensile strained silicon layer on the annealed silicon germanium layer. 8. A transistor produced by the method of claim 1, wherein the transistor comprises a relaxed silicon germanium layer and a tensile strained silicon layer overlying the silicon germanium layer. 9. A method of forming a SiGe / SOI structure, comprising: providing a silicon-on-insulator substrate comprising a buried oxide layer; depositing the silicon-germanium layer on the substrate; The silicon germanium layer of 550 ° C. to 10 ° C.
Performing a first annealing step that includes annealing at a temperature in the range of 50 ° C. for a time in the range of 0.5 to 4.0 hours, and at least 10 layers of the silicon germanium layer on the substrate.
Performing a second annealing step comprising annealing at a temperature of 50 ° C. for a time of 1 to 10 seconds. 10. The silicon germanium layer is Si
10. The method of claim 9, comprising _1-X Ge _X , where x ranges from 0.1 to 0.9. 11. The method of claim 9, further comprising growing a tensile strained silicon layer on the silicon germanium layer. 12. The method produces a transistor comprising the silicon germanium layer and the tensile strained silicon layer overlying the silicon germanium layer,
The silicon germanium layer is relaxed.
The method according to 1. 13. After the first annealing step,
The silicon from the silicon germanium layer and the silicon-on-insulator substrate combine to form a silicon germanium layer defined by Si _1-y Ge _y (y is less than x). Method. 14. The method of claim 9, wherein the second annealing step is performed by a method selected from the group consisting of rapid thermal annealing, laser annealing, and optical annealing such as flash lamps. 15. The method of claim 9, wherein the method produces a transistor including an upper silicon layer adapted for use as an nMOS channel. 16. The method produces a transistor comprising a top silicon layer overlying a silicon germanium layer, the top silicon layer and the silicon germanium layer each adapted for use as a pMOS channel. The method according to claim 9. 17. The silicon germanium layer has a maximum of 4 layers.
The method of claim 9, wherein the method is deposited to a thickness of 0 nm. 18. A transistor produced by the method of claim 9.