WO2013175278A1 - Procédé de traitement d'une structure de semi-conducteur sur isolant afin d'améliorer l'uniformité de l'épaisseur de la couche semi-conductrice - Google Patents

Procédé de traitement d'une structure de semi-conducteur sur isolant afin d'améliorer l'uniformité de l'épaisseur de la couche semi-conductrice Download PDF

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Publication number
WO2013175278A1
WO2013175278A1 PCT/IB2013/000857 IB2013000857W WO2013175278A1 WO 2013175278 A1 WO2013175278 A1 WO 2013175278A1 IB 2013000857 W IB2013000857 W IB 2013000857W WO 2013175278 A1 WO2013175278 A1 WO 2013175278A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
thickness
layer
semiconductor
process according
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PCT/IB2013/000857
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English (en)
Inventor
Walter Schwarzenbach
Carine Duret
François Boedt
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Soitec
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Application filed by Soitec filed Critical Soitec
Priority to KR1020147032558A priority Critical patent/KR102068189B1/ko
Priority to US14/397,287 priority patent/US9190284B2/en
Priority to CN201380026524.1A priority patent/CN104380447B/zh
Priority to DE201311002675 priority patent/DE112013002675T5/de
Priority to SG11201407361PA priority patent/SG11201407361PA/en
Publication of WO2013175278A1 publication Critical patent/WO2013175278A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Definitions

  • the present invention relates to a process for treating a structure of semiconductor-on- insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, with a view to standardizing the thickness of the semiconductor layer.
  • a buried dielectric layer electrically insulates the semiconductor layer from the support substrate.
  • the buried dielectric layer is generally denoted by the acronym BOX of the term "Buried OXide".
  • the thickness of the buried dielectric layer is generally greater than 100 nm and is thus sufficient to ensure the electrical integrity and the quality of said layer.
  • the thickness of the semiconductor layer is then typically between 100 and 200 nm.
  • the semiconductor layer has an ultrathin thickness, that is to say of less than or equal to 50 nm, typically of the order of 12 nm and which may be reduced down to around 5 nm.
  • the thickness of the buried dielectric layer may also be reduced, by a typical thickness of the order of 150 nm, down to values of less than 50 nm, typically 25 nm and which may drop down to 5 nm.
  • Such structures are in particular intended for the manufacture of transistors, the channel layer being formed in or on the ultrathin semiconductor layer, which is not doped.
  • these FD SeOI structures have the advantage of enabling a precise control of the channel of the transistor, of improving the short channel effect and of reducing the variability of the transistor.
  • the total variability results from the gate line edge roughness (LER) from the variability of the work function and from the thickness of the channel.
  • LER gate line edge roughness
  • the channel is not doped, the total variability is not subjected to random dopant fluctuation (RDF). Consequently, the uniformity of the thickness of the semiconductor layer forming the channel is an important parameter for limiting the variability of an FD SeOI device.
  • the specifications include both an "intra-wafer” uniformity (that is to say on the surface of one and the same structure, said structure generally being in the form of a circular wafer) and a “wafer-to-wafer” uniformity (that is to say between all of the structures belonging to all of the production batches).
  • LTTV layer total thickness variability
  • a total thickness variability of the semiconductor layer of the order of ⁇ 0.5 nm is targeted, preferably with the order of ⁇ 0.2 nm wafer-to-wafer, that is to say between the various structures resulting from all of the production batches.
  • Document WO 2004/015759 relates to a process for correcting the thickness of the semiconductor layer of an SeOI based on a selective sacrificial oxidation of said layer.
  • the sacrificial oxidation consumes a greater or lesser thickness of the semiconductor layer.
  • the sacrificial oxide layer is then removed by selective etching, typically using hydrofluoric acid (HF).
  • HF hydrofluoric acid
  • the structures that are the subject of this process are not only FD SeOI structures but "conventional" PD SeOI structures.
  • the order of magnitude of the accuracy of the thinning obtained by the sacrificial oxidation in equipment of "batch" type that is to say equipment (for example an oven) in which a plurality of structures are treated simultaneously, is greater than the accuracy according to which it is desired to control the uniformity on an FD SeOI structure.
  • the oxidized thickness may vary within one and the same structure and/or from one structure to the next.
  • Figure 1 illustrates the distribution of the mean thickness e mean compared to a target thickness e t of the semiconductor layer that may be obtained at the end of a sacrificial oxidation process as described above and as applied to the manufacture of PD SeOls.
  • One objective of the invention is therefore to provide a process for treating structures of semiconductor-on-insulator type for "fully depleted” applications that make it possible to standardize the thickness of the semiconductor layer between various structures over the whole of a production volume (wafer-to-wafer thickness).
  • Another objective of the invention is to provide a process for manufacturing structures of semiconductor-on-insulator type that makes it possible to guarantee a good uniformity of the structures produced.
  • Proposed in accordance with the invention is a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, said semiconductor layer being covered with a sacrificial oxide layer, said process being characterized in that it comprises:
  • this process is applied to said batch of semiconductor-on-insulator structures.
  • the structures are sorted by mean thickness class of the semiconductor layer (a class being defined as being a mean thickness range between a given lower limit and a given upper limit), and a chemical etching is carried out under identical conditions for all the structures belonging to one and the same class.
  • mean thickness class of the semiconductor layer a class being defined as being a mean thickness range between a given lower limit and a given upper limit
  • said chemical etching is carried out by simultaneously immersing all the structures of one and the same class in a bath of a chemical etching solution.
  • mean thickness classes are defined beforehand, it being possible for said mean thickness classes to have a width of from 0.3 to 0.5 nm.
  • the invention which aims to standardize the thickness of the semiconductor layer within one structure, starting from the mapping of the thickness of the semiconductor layer, at least one region is determined that has an overthickness to be thinned in order to standardize the thickness of the semiconductor layer within said structure.
  • said at least one region to be thinned of the layer is heated locally so as to provide a greater thinning in said region.
  • the chemical etching solution is distributed selectively by a jet over the surface of the semiconductor layer, so as to deposit a greater amount of solution on said at least one region to be thinned.
  • the etching solution is applied to said region to be thinned for a duration greater than the duration of application to the rest of the layer.
  • the mean thickness of the semiconductor layer for the batch is calculated, a mean thickness class is allocated to said batch, and a chemical etching of the semiconductor layer is carried out for the whole of said batch, the application, temperature and/or duration conditions of which chemical etching are adjusted as a function of said mean thickness class.
  • said chemical etching of the semiconductor layer is of SC1 type (acronym for the expression Standard Clean 1 ).
  • the selective etching of the sacrificial oxide layer is carried out by hydrofluoric acid.
  • the thickness measurement is preferably carried out by ellipsometry.
  • Another subject relates to a process for manufacturing a structure of semiconductor-on- insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm.
  • Said process comprises the following steps:
  • a donor substrate comprising said semiconductor layer
  • FIG. 1 presents the distribution of the mean thickness of the semiconductor layer of a structure of PD SeOI type
  • Figure 2 is a diagram of a structure of semiconductor-on-insulator type to which the treatment according to the invention is applied,
  • FIGS 3A to 3E schematically illustrate the main steps of the Smart CutTM process that makes it possible to manufacture said structure
  • Figure 4 presents an example of the distribution of the measurement points, measured by ellipsometry, on a semiconductor-on-insulator structure
  • Figure 5 presents the distribution of the mean thickness of the semiconductor layer of a structure of FD SeOI type at the end of the treatment according to the invention.
  • Figure 2 schematically illustrates a structure of semiconductor-on-insulator type to which the treatment for standardizing the semiconductor layer is applied.
  • the structure successively comprises a support substrate 1 , a dielectric layer 2 and a semiconductor layer 3.
  • the support substrate 1 mainly acts as a mechanical support for the semiconductor layer which is very thin.
  • the support substrate may or may not be made of a semiconductor material (for example silicon).
  • the support substrate may be a solid substrate or a composite substrate, that is to say consisting of a stack of various materials.
  • the dielectric layer 2 may be made of any dielectric material, such as a layer of silicon dioxide, a layer of nitrided silicon dioxide, a layer of silicon oxynitride, and/or a stack of layers of silicon dioxide, of silicon nitride and/or of alumina.
  • the dielectric layer 2 is ultrathin, that is to say that its thickness is less than or equal to 150 nm, preferably less than or equal to 50 nm, more preferably less than or equal to 25 nm, or even of the order of 5 nm.
  • the semiconductor layer 3 is made of a semiconductor material.
  • the semiconductor layer 3 is made of silicon (in which case the structure is denoted by the acronym SOI (for the expression silicon-on-insulator), but it may also be made of strained silicon (sSi), of silicon-germanium (SiGe), of strained silicon-germanium (sSiGe), of germanium, of strained germanium (sGe) or of a semiconductor material from group lll-V.
  • SOI silicon-on-insulator
  • the thickness of the semiconductor layer 3 prior to the treatment is less than 100 nm.
  • a semiconductor layer is initially formed that is thicker than the targeted final thickness taking into account the removal of material caused by the thinning.
  • Such a structure may advantageously be manufactured by the Smart CutTM process, the steps of which are illustrated with reference to Figures 3A to 3D.
  • a substrate 30, referred to as a donor substrate, comprising the semiconductor layer 3 is provided.
  • the donor substrate 30 may be a solid substrate of the same material as that of the semiconductor layer 3, or a solid substrate of a material different from that of the semiconductor layer 3, or else may be a composite substrate comprising at least two layers of different materials, one of which comprises the layer 3.
  • a layer 2 of a dielectric material is formed on the donor substrate 30. Said dielectric layer will form all or part of the dielectric layer of the SeOI structure.
  • atomic species are introduced into the donor substrate 30, through said dielectric layer 2, so as to form, at a depth corresponding to the desired thickness of the layer 3, a weakened zone 31 .
  • said introduction of species is carried out by implantation.
  • the donor substrate 30 is adhesively bonded, by the face through which the species were introduced, to the support substrate 1 .
  • the support substrate may optionally be covered with a dielectric layer, for example an oxide layer (not illustrated).
  • this dielectric layer and the dielectric layer formed on the donor substrate 30 together form the buried dielectric layer 2 of the SeOI structure.
  • the donor substrate 30 is fractured along the weakened zone 31 , which results in the transfer of the semiconductor layer 3 to the support substrate 1 , the dielectric layer 2 being at the interface.
  • the remainder 32 of the donor substrate may advantageously be recycled with a view to other uses.
  • finishing operations aim in particular to thin the thickness of said layer 3 and to reduce the roughness due to the implantation of species and to the fracture.
  • Such a smoothing operation may typically be carried out by means of rapid thermal annealing (RTA).
  • RTA rapid thermal annealing
  • a sacrificial oxide layer 4 is formed on said layer (cf. Figure 2).
  • This oxide is preferably formed by thermal oxidation of the material of the semiconductor layer 3, which has the effect of consuming a superficial portion of said layer.
  • This oxidation may typically be carried out by placing a batch of SeOI structures to be treated into an oven and by implementing in this oven conditions that lead to a superficial oxidation of the semiconductor layer 3.
  • this thermal oxidation in particular its duration, its composition, depending on whether the oxidation will be in a dry or wet atmosphere, its pressure and its temperature), it is possible to adjust the thickness of the layer 3 which will be consumed, and consequently the extent to which said layer 3 is thinned.
  • the thickness of the sacrificial oxide layer 4 is typically between 10 and 500 nm.
  • a measurement via ellipsometry provides not only the thickness of the sacrificial oxide layer 4, but also that of the underlying semiconductor layer 3.
  • Ellipsometry is a technique known per se for monitoring the correct functioning of the oxidation oven.
  • This technique is conventionally used for measuring the values (minimum, mean and maximum values) of the thickness of the sacrificial oxide layer and, if these values are too far apart, alerting the maintenance service in order to adjust the control of the oven in order to standardize the thickness of the sacrificial oxide layer.
  • an ellipsometer suitable for this use is the machine sold under the reference ASET-F5x by the company KLA-Tencor.
  • Reflectometry and in particular X-ray reflectometry (generally denoted by the acronym XRR), are other appropriate techniques for measuring the thickness of the sacrificial oxide layer.
  • the measurement already regularly made for controlling the oxidation oven is thus taken advantage of in order to obtain supplementary information, namely the thickness of the semiconductor layer 3 at various points distributed over the surface of the structure.
  • Figure 4 illustrates an example of the positioning of the measurement points, measured by ellipsometry, on a circular substrate having a diameter of 300 mm. In this example, there are 41 measurement points.
  • a mapping of the thickness of the semiconductor layer 3 over the surface of the structure is therefore obtained.
  • the mean thickness of the semiconductor layer is determined.
  • This mapping and/or this mean thickness make it possible to determine one or more regions that have overthicknesses compared to a target thickness and that must consequently be subjected to a thinning operation in order to improve the uniformity of the thickness of the semiconductor layer 3.
  • the thickness measured is compared at each point with the target thickness of the desired final product, said target thickness being less than or equal to the mean thickness.
  • the region(s) to be thinned is(are) therefore the region(s) in which the thickness of the semiconductor layer 3 is greater than the target thickness, the overthickness(es) corresponding to the difference between the measured thickness and the target thickness. It is therefore then a question of one or more "local" overthickness(es) of the wafer.
  • the mean of the thicknesses of the semiconductor layer 3 measured at the various measurement points are compared with a target mean thickness.
  • a wafer to be thinned is therefore a wafer for which the mean thickness of the semiconductor layer 3 is greater than the target mean thickness, the overthickness corresponding to the difference between these two mean thicknesses. It is therefore then a question of a "total" overthickness of the wafer.
  • a selective etching of the sacrificial oxide layer 4 is firstly carried out.
  • HF hydrofluoric acid
  • said etching is an etching of SC1 type.
  • This SC1 etching is carried out with a solution containing a mixture of ammonium hydroxide ( ⁇ , ⁇ ), hydrogen peroxide (H 2 0 2 ) and water (H 2 0), in typical proportions of 1/1/1 to 4/4/1 as weight concentrations.
  • the solution is maintained at a temperature between 40°C and 80°C.
  • SC1 etching has the effect of giving rise to a superficial oxidation of the semiconductor layer 3, and consequently of consuming a small thickness of said layer, while at the same time consuming the oxide thus created.
  • the thickness consumed depends on the composition and on the temperature of the solution and also on the amount of solution applied to the layer 3 and on the duration of the etching.
  • a person skilled in the art is able to determine the composition of the SC1 solution, and also the temperature and duration of application, in order to thin the semiconductor layer by a desired thickness.
  • this consumed thickness is of the order of a few nanometres and may be controlled to within a fraction of a nanometer.
  • the SC1 solution is customarily used in the treatment of semiconductor substrates in order to clean their surface by eliminating the contaminants.
  • the SC1 solution is not however used with a view to cleaning the semiconductor layer but with a view to etching it in order to thin it.
  • One advantage of using the ellipsometric measurement through the sacrificial oxide layer 4 is that it is possible to carry out the steps of HF etching and of SC1 etching directly one after the other, which simplifies the process.
  • each wafer is immersed in a bath containing the etching solution.
  • This embodiment is more particularly suitable for the treatment of a wafer that it is desired to thin totally, the solution having the effect of consuming a substantially uniform thickness of the semiconductor layer over the entire surface of the wafer.
  • the conditions of this etching are not identical for all the wafers of one and the same production batch but are adjusted depending on the mean thickness of the semiconductor layer of each wafer.
  • structures resulting from one and the same batch are sorted so as to regroup them according to predetermined mean thickness classes.
  • mean thickness classes are defined, it being possible for the two extreme classes to be devoid of a lower limit and an upper limit, and the intermediate classes defining mean thickness ranges of equal amplitude, of a few fractions of nanometres of amplitude, for example from 0.3 to 0.5 nm of amplitude.
  • the wafers of one and the same class are simultaneously submerged in one and the same bath of a solution of SC1.
  • the table below indicates, for 5 mean thickness classes, the duration of the SC1 etching and the thickness of the semiconductor layer (which, in this example, is made of silicon) consumed by said treatment, which is determined experimentally.
  • Mean thickness x (A) Class Duration of the SC1 Theoretical thickness etching (s) consumed (A)
  • the SC1 etching only differs between two classes by its duration, but it goes without saying that it is also possible to vary other parameters of this etching, such as the temperature, the composition of the solution, etc. as a function of the thickness that it is desired to consume.
  • the number and the amplitude of the mean thickness classes are defined by a person skilled in the art as a function of the specifications of the wafers, of the industrial stresses (each class being associated with an etching under different conditions), etc.
  • the thickness of the semiconductor layer 3 is measured, for example by ellipsometry.
  • the average of the mean thicknesses measured for all of the wafers of the batch is then calculated and, depending on the value thus obtained, all of the wafers of the batch are allocated to a predetermined class.
  • Figure 5 illustrates the distribution of the mean thickness e mean of the semiconductor layer relative to a target thickness e,.
  • the Y-axis indicates the percentage of wafers having a given thickness of the semiconductor layer.
  • the distribution obtained with the process described above is much narrower since it provides a variability of less than or equal to ⁇ 0.5 nm, or even less than or equal to ⁇ 0.2 nm compared to the target thickness.
  • the conditions of the SC1 etching are adjusted in order to locally thin the region(s) identified as having an overthickness, from the mapping described above.
  • the etching solution is sprayed over each wafer, for example using a movable nozzle. This makes it possible to adjust the amount of solution applied to the surface of the wafer as a function of the amplitude of the overthickness to be eliminated.
  • a wafer comprises a first region having a first overthickness and a second region having a second overthickness less than the first, it is possible to spray onto the first region an amount of solution greater than the amount sprayed onto the second, which is itself greater than the amount optionally sprayed onto the remainder of the surface.
  • the duration of application of the etching solution is also adjusted.
  • the solution is applied for a greater duration in the region which has the greatest overthickness.
  • the application temperature of the etching solution is also adjusted.
  • the wafer is locally heated in the region(s) which has(have) overthicknesses.
  • This localized heating can be carried out typically by a localized infrared heating device, as described, for example, in document FR 2 912 839.
  • Such a heating has the effect of intensifying the effect of the etching and of consuming a greater amount of the semiconductor material of the layer 3.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
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Abstract

L'invention concerne un procédé de traitement d'une structure de type semi-conducteur sur isolant qui comporte successivement un substrat porteur (1), une couche diélectrique (2) et une couche semi-conductrice (3) ayant une épaisseur inférieure ou égale à 100 nm, ladite couche semi-conductrice (3) étant recouverte d'une couche d'oxyde sacrificielle (4), comprenant les étapes suivantes : en une pluralité de points distribués à la surface de la structure, mesurer l'épaisseur de la couche d'oxyde sacrificielle (4) et de la couche semi-conductrice (3), afin de produire une carte de l'épaisseur de la couche semi-conductrice (3) et de déterminer, à partir de ces mesures, l'épaisseur moyenne de la couche semi-conductrice (3); graver sélectivement la couche d'oxyde sacrificielle (4) afin d'exposer la couche semi-conductrice (3); et effectuer une gravure chimique de la couche semi-conductrice (3) dans des conditions d'application, de température et/ou de durée qui sont ajustées en fonction de ladite carte et/ou de l'épaisseur moyenne de la couche semi-conductrice (3) afin d'amincir, au moins localement, ladite couche semi-conductrice (3) d'une épaisseur qui est identifiée comme étant une surépaisseur à la fin de l'étape de mesure.
PCT/IB2013/000857 2012-05-25 2013-05-01 Procédé de traitement d'une structure de semi-conducteur sur isolant afin d'améliorer l'uniformité de l'épaisseur de la couche semi-conductrice WO2013175278A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020147032558A KR102068189B1 (ko) 2012-05-25 2013-05-01 반도체층의 두께 균일성을 개선하기 위한 절연체 상 반도체의 처리 방법
US14/397,287 US9190284B2 (en) 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer
CN201380026524.1A CN104380447B (zh) 2012-05-25 2013-05-01 用于处理绝缘体上半导体结构以提高半导体层厚度均匀度的工艺
DE201311002675 DE112013002675T5 (de) 2012-05-25 2013-05-01 Verfahren zur Behandlung einer Halbleiter-auf-Isolator-Struktur zur Verbesserung der Dickengleichmäßigkeit der Halbleiterschicht
SG11201407361PA SG11201407361PA (en) 2012-05-25 2013-05-01 Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1254841 2012-05-25
FR1254841A FR2991099B1 (fr) 2012-05-25 2012-05-25 Procede de traitement d'une structure semi-conducteur sur isolant en vue d'uniformiser l'epaisseur de la couche semi-conductrice

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WO2013175278A1 true WO2013175278A1 (fr) 2013-11-28

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US (1) US9190284B2 (fr)
KR (1) KR102068189B1 (fr)
CN (1) CN104380447B (fr)
DE (1) DE112013002675T5 (fr)
FR (1) FR2991099B1 (fr)
SG (1) SG11201407361PA (fr)
WO (1) WO2013175278A1 (fr)

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FR3106236A1 (fr) * 2020-01-15 2021-07-16 Soitec Procédé de fabrication d’un capteur d’image

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FR2995444B1 (fr) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator Procede de detachement d'une couche
JP6354363B2 (ja) * 2014-06-12 2018-07-11 富士通セミコンダクター株式会社 半導体装置の製造方法
US10373838B2 (en) * 2015-12-08 2019-08-06 Elemental Scientific, Inc. Automatic sampling of hot phosphoric acid for the determination of chemical element concentrations and control of semiconductor processes
JP6673173B2 (ja) * 2016-12-12 2020-03-25 三菱電機株式会社 半導体装置の製造方法

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SG11201407361PA (en) 2014-12-30
CN104380447B (zh) 2017-05-03
KR102068189B1 (ko) 2020-01-20
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