SG10201804116TA - Methods of operating memory devices based on sub-block positions and related memory systems - Google Patents

Methods of operating memory devices based on sub-block positions and related memory systems

Info

Publication number
SG10201804116TA
SG10201804116TA SG10201804116TA SG10201804116TA SG10201804116TA SG 10201804116T A SG10201804116T A SG 10201804116TA SG 10201804116T A SG10201804116T A SG 10201804116TA SG 10201804116T A SG10201804116T A SG 10201804116TA SG 10201804116T A SG10201804116T A SG 10201804116TA
Authority
SG
Singapore
Prior art keywords
sub
memory block
methods
devices based
block positions
Prior art date
Application number
SG10201804116TA
Other languages
English (en)
Inventor
Park Se-Hwan
Kim Wan-dong
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201804116TA publication Critical patent/SG10201804116TA/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
SG10201804116TA 2017-09-05 2018-05-16 Methods of operating memory devices based on sub-block positions and related memory systems SG10201804116TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170113343A KR102336659B1 (ko) 2017-09-05 2017-09-05 데이터 신뢰성을 향상시키기 위한 메모리 동작을 수행하는 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 장치의 동작 방법

Publications (1)

Publication Number Publication Date
SG10201804116TA true SG10201804116TA (en) 2019-04-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201804116TA SG10201804116TA (en) 2017-09-05 2018-05-16 Methods of operating memory devices based on sub-block positions and related memory systems

Country Status (4)

Country Link
US (3) US10614891B2 (zh)
KR (1) KR102336659B1 (zh)
CN (1) CN109427397B (zh)
SG (1) SG10201804116TA (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190012570A (ko) * 2017-07-27 2019-02-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR102336659B1 (ko) * 2017-09-05 2021-12-07 삼성전자 주식회사 데이터 신뢰성을 향상시키기 위한 메모리 동작을 수행하는 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 장치의 동작 방법
US11232841B2 (en) * 2017-09-05 2022-01-25 Samsung Electronics Co., Ltd. Methods of operating memory devices based on sub-block positions and related memory system
CN109979509B (zh) * 2019-03-29 2020-05-08 长江存储科技有限责任公司 一种三维存储器及其编程操作方法
US10978428B2 (en) * 2019-05-07 2021-04-13 SK Hynix Inc. Manufacturing method of semiconductor device
JP7180015B2 (ja) * 2019-11-13 2022-11-29 長江存儲科技有限責任公司 プログラミング動作を実行する方法および関連するメモリデバイス
US10943662B1 (en) * 2019-12-10 2021-03-09 Western Digital Technologies, Inc. Different word line programming orders in non-volatile memory for error recovery
US11107540B1 (en) * 2020-02-14 2021-08-31 Sandisk Technologies Llc Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation
KR20220019574A (ko) * 2020-08-10 2022-02-17 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR20220090210A (ko) 2020-12-22 2022-06-29 삼성전자주식회사 데이터 신뢰성을 보전하기 위한 소거 동작을 수행하는 메모리 장치
CN113345489B (zh) * 2021-06-28 2023-08-08 长江存储科技有限责任公司 存储器及其操作方法

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6098145A (en) * 1998-02-18 2000-08-01 Winbond Electronics Corporation Pulsed Y-decoders for improving bitline precharging in memories
JP3732111B2 (ja) * 2001-04-26 2006-01-05 株式会社ルネサステクノロジ 半導体装置
US6614695B2 (en) 2001-08-24 2003-09-02 Micron Technology, Inc. Non-volatile memory with block erase
JP2003123470A (ja) * 2001-10-05 2003-04-25 Mitsubishi Electric Corp 半導体記憶装置
KR100546342B1 (ko) * 2003-07-12 2006-01-26 삼성전자주식회사 반복적으로 배치되는 프리-디코딩된 신호선들의레이아웃을 개선시키는 로우 디코더 구조, 이를 구비한반도체 메모리 장치, 및 그 방법
JP4836487B2 (ja) * 2005-04-28 2011-12-14 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
CA2672245A1 (en) * 2007-02-07 2008-08-14 Mosaid Technologies Incorporated Source side asymmetrical precharge programming scheme
US7804718B2 (en) 2007-03-07 2010-09-28 Mosaid Technologies Incorporated Partial block erase architecture for flash memory
JP4907563B2 (ja) * 2008-01-16 2012-03-28 パナソニック株式会社 半導体記憶装置
US7949821B2 (en) 2008-06-12 2011-05-24 Micron Technology, Inc. Method of storing data on a flash memory device
JP5584895B2 (ja) * 2009-10-08 2014-09-10 ルネサスエレクトロニクス株式会社 半導体信号処理装置
KR101691092B1 (ko) * 2010-08-26 2016-12-30 삼성전자주식회사 불휘발성 메모리 장치, 그것의 동작 방법, 그리고 그것을 포함하는 메모리 시스템
TW201142869A (en) * 2010-02-09 2011-12-01 Samsung Electronics Co Ltd Memory device from which dummy edge memory block is removed
JP5788183B2 (ja) 2010-02-17 2015-09-30 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 不揮発性メモリ装置、それの動作方法、そしてそれを含むメモリシステム
KR20130038391A (ko) * 2010-07-21 2013-04-17 모사이드 테크놀로지스 인코퍼레이티드 플래시 메모리용 멀티페이지 프로그램 스킴
KR101703106B1 (ko) * 2011-01-04 2017-02-06 삼성전자주식회사 부분-이레이즈 동작을 수행할 수 있는 비휘발성 메모리 장치와 상기 비휘발성 메모리 장치를 포함하는 장치들
KR101748884B1 (ko) 2011-05-25 2017-06-19 에스케이하이닉스 주식회사 3차원 구조의 비휘발성 메모리 소자 및 그 동작 방법
KR101891164B1 (ko) 2012-04-17 2018-08-23 삼성전자주식회사 프로그램 스케줄러를 포함하는 플래시 메모리 장치
KR101967895B1 (ko) 2012-05-02 2019-04-11 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 비휘발성 메모리 장치의 구동 방법
US9589644B2 (en) * 2012-10-08 2017-03-07 Micron Technology, Inc. Reducing programming disturbance in memory devices
US8988937B2 (en) 2012-10-24 2015-03-24 Sandisk Technologies Inc. Pre-charge during programming for 3D memory using gate-induced drain leakage
KR20140088384A (ko) * 2013-01-02 2014-07-10 에스케이하이닉스 주식회사 반도체 메모리 장치
US9043537B1 (en) 2013-11-21 2015-05-26 Sandisk Technologies Inc. Update block programming order
JP2015176626A (ja) * 2014-03-17 2015-10-05 株式会社東芝 不揮発性半導体記憶装置
WO2016014731A1 (en) * 2014-07-22 2016-01-28 Aplus Flash Technology, Inc. Yukai vsl-based vt-compensation for nand memory
US9620217B2 (en) 2014-08-12 2017-04-11 Macronix International Co., Ltd. Sub-block erase
KR102272238B1 (ko) * 2014-09-02 2021-07-06 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
KR102151181B1 (ko) * 2014-09-05 2020-09-02 삼성전자주식회사 메모리 장치와 이를 포함하는 메모리 시스템
US9412451B2 (en) 2014-10-08 2016-08-09 Micron Technology, Inc. Apparatuses and methods using dummy cells programmed to different states
US9576667B2 (en) 2014-11-11 2017-02-21 Micron Technology, Inc. Apparatuses and methods for non-volatile memory programming schemes
KR102222594B1 (ko) * 2014-11-13 2021-03-08 삼성전자주식회사 비휘발성 메모리 장치, 그것의 소거 방법, 및 그것을 포함하는 메모리 시스템
US9236128B1 (en) * 2015-02-02 2016-01-12 Sandisk Technologies Inc. Voltage kick to non-selected word line during programming
KR102292642B1 (ko) * 2015-03-13 2021-08-23 삼성전자주식회사 비휘발성 메모리 장치 및 비휘발성 메모리 장치의 프로그램 방법
US9595319B2 (en) * 2015-04-24 2017-03-14 Peter Wung Lee Partial/full array/block erase for 2D/3D hierarchical NAND
KR102251815B1 (ko) * 2015-07-02 2021-05-13 삼성전자주식회사 메모리 장치 및 메모리 시스템
CN105070735B (zh) 2015-07-10 2017-08-11 清华大学 三维阻变存储器件及其操作方法
KR102312404B1 (ko) 2015-09-07 2021-10-13 에스케이하이닉스 주식회사 저장 장치 및 이의 동작 방법
ITUB20160956A1 (it) * 2016-02-22 2017-08-22 Sk Hynix Inc Memoria flash NAND comprendente un page buffer per il rilevamento di corrente
KR102571497B1 (ko) * 2016-05-10 2023-08-29 삼성전자주식회사 멀티 스택 칩 패키지를 포함하는 데이터 저장 장치 및 그것의 동작 방법
KR102432795B1 (ko) * 2016-06-15 2022-08-17 에스케이하이닉스 주식회사 반도체 장치 및 그 동작 방법
KR102621752B1 (ko) 2017-01-13 2024-01-05 삼성전자주식회사 Mram을 포함한 씨모스 이미지 센서
US10068657B1 (en) * 2017-02-10 2018-09-04 Sandisk Technologies Llc Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels
US10354737B2 (en) * 2017-06-22 2019-07-16 Western Digital Technologies, Inc. Non-volatile memory sub-block erasure disturb management scheme
KR102326558B1 (ko) * 2017-07-28 2021-11-15 삼성전자주식회사 낸드 스트링을 포함하는 메모리 장치 및 그 동작 방법
WO2019041082A1 (en) * 2017-08-28 2019-03-07 Micron Technology, Inc. ARCHITECTURE AND MEMORY OPERATION
KR102336659B1 (ko) * 2017-09-05 2021-12-07 삼성전자 주식회사 데이터 신뢰성을 향상시키기 위한 메모리 동작을 수행하는 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 장치의 동작 방법
US10614886B2 (en) * 2017-09-22 2020-04-07 Samsung Electronics Co., Ltd. Nonvolatile memory device and a method of programming the nonvolatile memory device
KR20190057701A (ko) * 2017-11-20 2019-05-29 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 소거 방법
KR102369391B1 (ko) * 2017-12-27 2022-03-02 삼성전자주식회사 비휘발성 메모리 장치의 데이터 소거 방법 및 이를 수행하는 비휘발성 메모리 장치
US11101001B2 (en) * 2018-05-08 2021-08-24 Sandisk Technologies Llc Non-volatile memory with multi-plane mixed sub-block programming
US10438671B1 (en) * 2018-06-22 2019-10-08 Sandisk Technologies Llc Reducing program disturb by modifying word line voltages at interface in two-tier stack during programming
US10726891B1 (en) * 2019-02-13 2020-07-28 Western Digital Technologies, Inc. Reducing post-read disturb in a nonvolatile memory device
US10636498B1 (en) * 2019-02-22 2020-04-28 Sandisk Technologies Llc Managing bit-line settling time in non-volatile memory
US10770157B1 (en) * 2019-05-21 2020-09-08 Sandisk Technologies Llc Method of reducing injection type of program disturb during program pre-charge in memory device
US11081162B1 (en) * 2020-02-24 2021-08-03 Sandisk Technologies Llc Source side precharge and boosting improvement for reverse order program

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Publication number Publication date
CN109427397B (zh) 2023-10-20
US20200234771A1 (en) 2020-07-23
US10614891B2 (en) 2020-04-07
US11276471B2 (en) 2022-03-15
KR20190026431A (ko) 2019-03-13
US20190074065A1 (en) 2019-03-07
CN109427397A (zh) 2019-03-05
US10971235B2 (en) 2021-04-06
US20210210147A1 (en) 2021-07-08
KR102336659B1 (ko) 2021-12-07

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