ITUB20160956A1 - Memoria flash NAND comprendente un page buffer per il rilevamento di corrente - Google Patents

Memoria flash NAND comprendente un page buffer per il rilevamento di corrente

Info

Publication number
ITUB20160956A1
ITUB20160956A1 ITUB2016A000956A ITUB20160956A ITUB20160956A1 IT UB20160956 A1 ITUB20160956 A1 IT UB20160956A1 IT UB2016A000956 A ITUB2016A000956 A IT UB2016A000956A IT UB20160956 A ITUB20160956 A IT UB20160956A IT UB20160956 A1 ITUB20160956 A1 IT UB20160956A1
Authority
IT
Italy
Prior art keywords
flash memory
current detection
nand flash
page buffer
memory including
Prior art date
Application number
ITUB2016A000956A
Other languages
English (en)
Inventor
Chiara Missiroli
Original Assignee
Sk Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sk Hynix Inc filed Critical Sk Hynix Inc
Priority to ITUB2016A000956A priority Critical patent/ITUB20160956A1/it
Priority to US15/432,147 priority patent/US9779824B2/en
Priority to KR1020170023024A priority patent/KR102681806B1/ko
Publication of ITUB20160956A1 publication Critical patent/ITUB20160956A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
ITUB2016A000956A 2016-02-22 2016-02-22 Memoria flash NAND comprendente un page buffer per il rilevamento di corrente ITUB20160956A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
ITUB2016A000956A ITUB20160956A1 (it) 2016-02-22 2016-02-22 Memoria flash NAND comprendente un page buffer per il rilevamento di corrente
US15/432,147 US9779824B2 (en) 2016-02-22 2017-02-14 NAND flash memory comprising current sensing page buffer
KR1020170023024A KR102681806B1 (ko) 2016-02-22 2017-02-21 반도체 메모리 장치 및 그것의 동작 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITUB2016A000956A ITUB20160956A1 (it) 2016-02-22 2016-02-22 Memoria flash NAND comprendente un page buffer per il rilevamento di corrente

Publications (1)

Publication Number Publication Date
ITUB20160956A1 true ITUB20160956A1 (it) 2017-08-22

Family

ID=55948998

Family Applications (1)

Application Number Title Priority Date Filing Date
ITUB2016A000956A ITUB20160956A1 (it) 2016-02-22 2016-02-22 Memoria flash NAND comprendente un page buffer per il rilevamento di corrente

Country Status (3)

Country Link
US (1) US9779824B2 (it)
KR (1) KR102681806B1 (it)
IT (1) ITUB20160956A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102672106B1 (ko) * 2015-11-12 2024-06-05 에스케이하이닉스 주식회사 전류 감지 페이지 버퍼를 포함하는 메모리 장치
KR102253836B1 (ko) * 2017-07-11 2021-05-20 삼성전자주식회사 페이지 버퍼 및 이를 포함하는 비휘발성 메모리 장치
KR102336659B1 (ko) * 2017-09-05 2021-12-07 삼성전자 주식회사 데이터 신뢰성을 향상시키기 위한 메모리 동작을 수행하는 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 장치의 동작 방법
US11232841B2 (en) 2017-09-05 2022-01-25 Samsung Electronics Co., Ltd. Methods of operating memory devices based on sub-block positions and related memory system
KR20210069262A (ko) 2019-12-03 2021-06-11 에스케이하이닉스 주식회사 메모리 장치 및 그것의 동작 방법
KR20220014546A (ko) 2020-07-29 2022-02-07 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
KR20220018353A (ko) 2020-08-06 2022-02-15 에스케이하이닉스 주식회사 페이지 버퍼 및 이를 포함하는 반도체 메모리 장치
KR20220045760A (ko) 2020-10-06 2022-04-13 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
KR20230027381A (ko) 2021-08-18 2023-02-28 삼성전자주식회사 메모리 장치, 메모리 장치의 동작 방법, 및 메모리 장치에 포함된 페이지 버퍼
US11575758B1 (en) 2021-09-13 2023-02-07 Amazon Technologies, Inc. Session-based device grouping

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221739A1 (en) * 2005-03-30 2006-10-05 Hynix Semiconductor Inc. Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof
US20080247241A1 (en) * 2007-04-05 2008-10-09 Hao Thai Nguyen Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise
US20140355354A1 (en) * 2013-05-31 2014-12-04 SK Hynix Inc. Integrated circuit and operation method thereof
US20160005490A1 (en) * 2014-07-03 2016-01-07 Dong-Kyo Shim Non-volatile memory device and operating method of the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100626371B1 (ko) * 2004-03-30 2006-09-20 삼성전자주식회사 캐쉬 읽기 동작을 수행하는 비휘발성 메모리 장치, 그것을포함한 메모리 시스템, 그리고 캐쉬 읽기 방법
KR100816155B1 (ko) * 2006-12-28 2008-03-21 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 멀티레벨 셀 프로그램 방법
KR101218896B1 (ko) * 2011-02-18 2013-01-08 에스케이하이닉스 주식회사 불휘발성 메모리 장치 및 이의 프로그램 검증 방법
US8576639B2 (en) * 2011-07-05 2013-11-05 Elpida Memory, Inc. Memory device having switch providing voltage to bit line
KR20140148132A (ko) * 2013-06-21 2014-12-31 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060221739A1 (en) * 2005-03-30 2006-10-05 Hynix Semiconductor Inc. Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof
US20080247241A1 (en) * 2007-04-05 2008-10-09 Hao Thai Nguyen Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise
US20140355354A1 (en) * 2013-05-31 2014-12-04 SK Hynix Inc. Integrated circuit and operation method thereof
US20160005490A1 (en) * 2014-07-03 2016-01-07 Dong-Kyo Shim Non-volatile memory device and operating method of the same

Also Published As

Publication number Publication date
KR20170098716A (ko) 2017-08-30
US9779824B2 (en) 2017-10-03
US20170243653A1 (en) 2017-08-24
KR102681806B1 (ko) 2024-07-05

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