SG10201803738UA - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
SG10201803738UA
SG10201803738UA SG10201803738UA SG10201803738UA SG10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA
Authority
SG
Singapore
Prior art keywords
dielectric layer
pad
chip
lower dielectric
region
Prior art date
Application number
SG10201803738UA
Other languages
English (en)
Inventor
Han Jung-Hoon
Kim Sungjin
Noh Junyong
Lim Heonjun
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201803738UA publication Critical patent/SG10201803738UA/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
SG10201803738UA 2017-07-26 2018-05-03 Semiconductor device SG10201803738UA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170094903A KR102428328B1 (ko) 2017-07-26 2017-07-26 반도체 장치

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SG10201803738UA true SG10201803738UA (en) 2019-02-27

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