SE451914B - Integrerad minnesanordning for en tidsomkopplare - Google Patents
Integrerad minnesanordning for en tidsomkopplareInfo
- Publication number
- SE451914B SE451914B SE8203553A SE8203553A SE451914B SE 451914 B SE451914 B SE 451914B SE 8203553 A SE8203553 A SE 8203553A SE 8203553 A SE8203553 A SE 8203553A SE 451914 B SE451914 B SE 451914B
- Authority
- SE
- Sweden
- Prior art keywords
- address
- generating
- read
- information
- response
- Prior art date
Links
- 230000003213 activating effect Effects 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000010276 construction Methods 0.000 description 5
- 235000013405 beer Nutrition 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 210000000056 organ Anatomy 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 108090000623 proteins and genes Proteins 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
- G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/08—Time only switching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56088375A JPS57203276A (en) | 1981-06-09 | 1981-06-09 | Information storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
SE8203553L SE8203553L (sv) | 1982-12-10 |
SE451914B true SE451914B (sv) | 1987-11-02 |
Family
ID=13941040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE8203553A SE451914B (sv) | 1981-06-09 | 1982-06-08 | Integrerad minnesanordning for en tidsomkopplare |
Country Status (8)
Country | Link |
---|---|
US (1) | US4564926A (sr) |
JP (1) | JPS57203276A (sr) |
CA (1) | CA1188425A (sr) |
DE (1) | DE3221872C2 (sr) |
FR (1) | FR2507372B1 (sr) |
GB (1) | GB2101372B (sr) |
NL (1) | NL8202302A (sr) |
SE (1) | SE451914B (sr) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58137391A (ja) * | 1982-02-10 | 1983-08-15 | Fujitsu Ltd | 時間スイツチ回路 |
JPS59180871A (ja) * | 1983-03-31 | 1984-10-15 | Fujitsu Ltd | 半導体メモリ装置 |
GB2138230B (en) * | 1983-04-12 | 1986-12-03 | Sony Corp | Dynamic random access memory arrangements |
FR2554952B1 (fr) * | 1983-11-15 | 1989-04-28 | Telecommunications Sa | Procede et systeme d'adressage pour memoire dynamique |
JPH0642263B2 (ja) * | 1984-11-26 | 1994-06-01 | 株式会社日立製作所 | デ−タ処理装置 |
US4742474A (en) * | 1985-04-05 | 1988-05-03 | Tektronix, Inc. | Variable access frame buffer memory |
US4685084A (en) * | 1985-06-07 | 1987-08-04 | Intel Corporation | Apparatus for selecting alternate addressing mode and read-only memory |
US4815033A (en) * | 1985-12-10 | 1989-03-21 | Advanced Micro Devices, Inc. | Method and apparatus for accessing a color palette synchronously during refreshing of a monitor and asynchronously during updating of the palette |
JPH0779514B2 (ja) * | 1986-01-24 | 1995-08-23 | 日本電気株式会社 | 時分割時間スイツチ制御方式 |
US5133062A (en) * | 1986-03-06 | 1992-07-21 | Advanced Micro Devices, Inc. | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
US4949301A (en) * | 1986-03-06 | 1990-08-14 | Advanced Micro Devices, Inc. | Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs |
JPH0221490A (ja) * | 1988-07-07 | 1990-01-24 | Oki Electric Ind Co Ltd | ダイナミック・ランダム・アクセス・メモリ |
US5005157A (en) * | 1989-11-13 | 1991-04-02 | Chips & Technologies, Inc. | Apparatus for selectively providing RAS signals or RAS timing and coded RAS address signals |
US5923604A (en) * | 1997-12-23 | 1999-07-13 | Micron Technology, Inc. | Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device |
TW430815B (en) * | 1998-06-03 | 2001-04-21 | Fujitsu Ltd | Semiconductor integrated circuit memory and, bus control method |
US7917825B2 (en) * | 2006-12-15 | 2011-03-29 | Joo-Sang Lee | Method and apparatus for selectively utilizing information within a semiconductor device |
CN107979127B (zh) * | 2017-11-21 | 2021-11-02 | 深圳艾斯特创新科技有限公司 | 一种基于单线通信的智能电池实现多电池并联通信的方案 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3638199A (en) * | 1969-12-19 | 1972-01-25 | Ibm | Data-processing system with a storage having a plurality of simultaneously accessible locations |
US3798617A (en) * | 1970-11-04 | 1974-03-19 | Gen Instrument Corp | Permanent storage memory and means for addressing |
GB1458526A (en) * | 1973-07-26 | 1976-12-15 | Gen Electric Co Ltd | Telecommunications switching networks |
US3956593B2 (en) * | 1974-10-15 | 1993-05-25 | Time space time(tst)switch with combined and distributed state store and control store | |
FR2341999A1 (fr) * | 1976-02-17 | 1977-09-16 | Thomson Csf | Matrice temporelle symetrique, et autocommutateur muni d'une telle matrice |
US4099256A (en) * | 1976-11-16 | 1978-07-04 | Bell Telephone Laboratories, Incorporated | Method and apparatus for establishing, reading, and rapidly clearing a translation table memory |
US4207618A (en) * | 1978-06-26 | 1980-06-10 | Texas Instruments Incorporated | On-chip refresh for dynamic memory |
FR2447660A1 (fr) * | 1979-01-26 | 1980-08-22 | Cit Alcatel | Dispositif commande de repartition de trafic pour un reseau de commutation temporelle |
US4347589A (en) * | 1979-05-15 | 1982-08-31 | Mostek Corporation | Refresh counter test |
DE3009872C2 (de) * | 1980-03-14 | 1984-05-30 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Regenerieren von in einem dynamischen MOS-Speicher gespeicherten Daten unter Berücksichtigung von Schreib- und Lesezyklen und Schaltungsanordnung zur Durchführung des Verfahrens |
JPS57212677A (en) * | 1981-06-24 | 1982-12-27 | Nec Corp | Storage element |
-
1981
- 1981-06-09 JP JP56088375A patent/JPS57203276A/ja active Pending
-
1982
- 1982-06-04 US US06/385,163 patent/US4564926A/en not_active Expired - Lifetime
- 1982-06-07 GB GB08216466A patent/GB2101372B/en not_active Expired
- 1982-06-08 NL NL8202302A patent/NL8202302A/nl active Search and Examination
- 1982-06-08 FR FR8209912A patent/FR2507372B1/fr not_active Expired
- 1982-06-08 SE SE8203553A patent/SE451914B/sv not_active IP Right Cessation
- 1982-06-09 DE DE3221872A patent/DE3221872C2/de not_active Expired
- 1982-06-09 CA CA000404796A patent/CA1188425A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB2101372B (en) | 1985-03-27 |
FR2507372A1 (fr) | 1982-12-10 |
US4564926A (en) | 1986-01-14 |
SE8203553L (sv) | 1982-12-10 |
DE3221872A1 (de) | 1983-03-03 |
GB2101372A (en) | 1983-01-12 |
CA1188425A (en) | 1985-06-04 |
JPS57203276A (en) | 1982-12-13 |
FR2507372B1 (fr) | 1987-04-24 |
NL8202302A (nl) | 1983-01-03 |
DE3221872C2 (de) | 1987-02-19 |
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