NL7700290A - Werkwijze voor het vervaardigen van een comple- mentaire geisoleerde poortveldeffekttransistor en veldeffekttransistor verkregen onder toepas- sing van deze werkwijze. - Google Patents

Werkwijze voor het vervaardigen van een comple- mentaire geisoleerde poortveldeffekttransistor en veldeffekttransistor verkregen onder toepas- sing van deze werkwijze.

Info

Publication number
NL7700290A
NL7700290A NL7700290A NL7700290A NL7700290A NL 7700290 A NL7700290 A NL 7700290A NL 7700290 A NL7700290 A NL 7700290A NL 7700290 A NL7700290 A NL 7700290A NL 7700290 A NL7700290 A NL 7700290A
Authority
NL
Netherlands
Prior art keywords
effect transistor
procedure
manufacturing
application
insulated gate
Prior art date
Application number
NL7700290A
Other languages
English (en)
Other versions
NL186355B (nl
NL186355C (nl
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of NL7700290A publication Critical patent/NL7700290A/nl
Publication of NL186355B publication Critical patent/NL186355B/nl
Application granted granted Critical
Publication of NL186355C publication Critical patent/NL186355C/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
NLAANVRAGE7700290,A 1976-01-12 1977-01-12 Werkwijze voor het vervaardigen van een veldeffekttransistor met geÿsoleerde poort van een paar complementaire transistors. NL186355C (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP205776A JPS5286083A (en) 1976-01-12 1976-01-12 Production of complimentary isolation gate field effect transistor

Publications (3)

Publication Number Publication Date
NL7700290A true NL7700290A (nl) 1977-07-14
NL186355B NL186355B (nl) 1990-06-01
NL186355C NL186355C (nl) 1990-11-01

Family

ID=11518695

Family Applications (1)

Application Number Title Priority Date Filing Date
NLAANVRAGE7700290,A NL186355C (nl) 1976-01-12 1977-01-12 Werkwijze voor het vervaardigen van een veldeffekttransistor met geÿsoleerde poort van een paar complementaire transistors.

Country Status (4)

Country Link
US (2) US4110899A (nl)
JP (1) JPS5286083A (nl)
DE (1) DE2700873C2 (nl)
NL (1) NL186355C (nl)

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US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
US4135955A (en) * 1977-09-21 1979-01-23 Harris Corporation Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation
JPS5529116A (en) * 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
US5252505A (en) * 1979-05-25 1993-10-12 Hitachi, Ltd. Method for manufacturing a semiconductor device
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device
JPS5643756A (en) * 1979-09-18 1981-04-22 Seiko Epson Corp Manufacture of semiconductor device
JPS5683078A (en) * 1979-12-11 1981-07-07 Mitsubishi Electric Corp Semiconductor device
JPS5691461A (en) * 1979-12-25 1981-07-24 Fujitsu Ltd Manufacturing of complementary mos integrated circuit
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process
NL186662C (nl) * 1980-04-29 1992-03-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS5766659A (en) * 1980-10-09 1982-04-22 Toshiba Corp Manufacture of complementary mos semiconductor device
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
US4385947A (en) * 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation
DE3133468A1 (de) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen in siliziumgate-technologie
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
US4426766A (en) * 1981-10-21 1984-01-24 Hughes Aircraft Company Method of fabricating high density high breakdown voltage CMOS devices
US4528581A (en) * 1981-10-21 1985-07-09 Hughes Aircraft Company High density CMOS devices with conductively interconnected wells
JPS5885559A (ja) * 1981-11-18 1983-05-21 Nec Corp Ｃｍｏｓ型半導体集積回路装置
US4435895A (en) * 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
IT1210872B (it) * 1982-04-08 1989-09-29 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.
JPS5955052A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体集積回路装置の製造方法
US4462151A (en) * 1982-12-03 1984-07-31 International Business Machines Corporation Method of making high density complementary transistors
US4480375A (en) * 1982-12-09 1984-11-06 International Business Machines Corporation Simple process for making complementary transistors
US4470191A (en) * 1982-12-09 1984-09-11 International Business Machines Corporation Process for making complementary transistors by sequential implantations using oxidation barrier masking layer
EP0123384A1 (en) * 1983-02-25 1984-10-31 Western Digital Corporation Complementary insulated gate field effect integrated circuit structure and process for fabricating the structure
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
DE3330851A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
EP0157926B1 (de) * 1984-03-21 1989-03-08 Siemens Aktiengesellschaft Verfahren zum Herstellen einer hochintegrierten MOS-Feld-effekttransistorschaltung
JPS60166156U (ja) * 1985-03-07 1985-11-05 セイコーエプソン株式会社 相補型ｍｏｓ集積回路装置
NL8501720A (nl) * 1985-06-14 1987-01-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een siliciumplak plaatselijk wordt voorzien van veldoxide met kanaalonderbreker.
US4685194A (en) * 1985-10-21 1987-08-11 The United States Of America As Represented By The Secretary Of The Air Force Direct moat self-aligned field oxide technique
JPS63147A (ja) * 1987-06-12 1988-01-05 Seiko Epson Corp 半導体装置
JPS63146A (ja) * 1987-06-12 1988-01-05 Seiko Epson Corp 半導体装置
JP2572653B2 (ja) * 1989-12-29 1997-01-16 セイコーエプソン株式会社 半導体装置の製造方法
JPH02224269A (ja) * 1989-12-29 1990-09-06 Seiko Epson Corp 半導体装置
US5212111A (en) * 1992-04-22 1993-05-18 Micron Technology, Inc. Local-oxidation of silicon (LOCOS) process using ceramic barrier layer
US5439842A (en) * 1992-09-21 1995-08-08 Siliconix Incorporated Low temperature oxide layer over field implant mask
US5328866A (en) * 1992-09-21 1994-07-12 Siliconix Incorporated Low temperature oxide layer over field implant mask
EP0637074A3 (en) * 1993-07-30 1995-06-21 Sgs Thomson Microelectronics Process for the production of active and isolated areas by split imaging.
US5622882A (en) * 1994-12-30 1997-04-22 Lsi Logic Corporation Method of making a CMOS dynamic random-access memory (DRAM)
US5679598A (en) * 1994-12-30 1997-10-21 Lsi Logic Corporation Method of making a CMOS dynamic random-access memory (DRAM)
US5648290A (en) * 1994-12-30 1997-07-15 Lsi Logic Corporation Method of making a CMOS dynamic random-access memory (DRAM)
US5783470A (en) * 1995-12-14 1998-07-21 Lsi Logic Corporation Method of making CMOS dynamic random-access memory structures and the like
US6090686A (en) 1997-06-18 2000-07-18 Lucent Technologies, Inc. Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same
US5907777A (en) * 1997-07-31 1999-05-25 International Business Machines Corporation Method for forming field effect transistors having different threshold voltages and devices formed thereby
US5981326A (en) * 1998-03-23 1999-11-09 Wanlass; Frank M. Damascene isolation of CMOS transistors
US7049669B2 (en) * 2003-09-15 2006-05-23 Infineon Technologies Ag LDMOS transistor

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NL160988C (nl) 1971-06-08 1979-12-17 Philips Nv Halfgeleiderinrichting met een halfgeleiderlichaam, be- vattende ten minste een eerste veldeffecttransistor met geisoleerde stuurelektrode en werkwijze voor de vervaar- diging van de halfgeleiderinrichting.
US3750268A (en) * 1971-09-10 1973-08-07 Motorola Inc Poly-silicon electrodes for c-igfets
US3712995A (en) * 1972-03-27 1973-01-23 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
JPS4991279A (nl) * 1972-12-29 1974-08-31
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
US3888706A (en) * 1973-08-06 1975-06-10 Rca Corp Method of making a compact guard-banded mos integrated circuit device using framelike diffusion-masking structure
US4027380A (en) * 1974-06-03 1977-06-07 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US3920481A (en) * 1974-06-03 1975-11-18 Fairchild Camera Instr Co Process for fabricating insulated gate field effect transistor structure
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US4047284A (en) * 1975-05-08 1977-09-13 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
US3983620A (en) * 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
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US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process

Also Published As

Publication number Publication date
DE2700873C2 (de) 1986-05-15
USRE31079E (en) 1982-11-16
DE2700873A1 (de) 1977-07-21
US4110899A (en) 1978-09-05
NL186355B (nl) 1990-06-01
NL186355C (nl) 1990-11-01
JPS5286083A (en) 1977-07-16
JPS638622B2 (nl) 1988-02-23

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Legal Events

Date Code Title Description
BC A request for examination has been filed
A85 Still pending on 85-01-01
V4 Lapsed because of reaching the maximum lifetime of a patent

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