MY102808A - Memory arbitration for video subsystems - Google Patents

Memory arbitration for video subsystems

Info

Publication number
MY102808A
MY102808A MYPI88000166A MYPI19880166A MY102808A MY 102808 A MY102808 A MY 102808A MY PI88000166 A MYPI88000166 A MY PI88000166A MY PI19880166 A MYPI19880166 A MY PI19880166A MY 102808 A MY102808 A MY 102808A
Authority
MY
Malaysia
Prior art keywords
cpu
display
video
cycles
access
Prior art date
Application number
MYPI88000166A
Other languages
English (en)
Inventor
Patrick Thompson Stephen
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MY102808A publication Critical patent/MY102808A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Bus Control (AREA)
MYPI88000166A 1987-03-20 1988-02-19 Memory arbitration for video subsystems MY102808A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2880187A 1987-03-20 1987-03-20

Publications (1)

Publication Number Publication Date
MY102808A true MY102808A (en) 1992-11-30

Family

ID=21845511

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI88000166A MY102808A (en) 1987-03-20 1988-02-19 Memory arbitration for video subsystems

Country Status (20)

Country Link
EP (1) EP0283565B1 (enExample)
JP (1) JPH0766319B2 (enExample)
KR (1) KR950005230B1 (enExample)
CN (1) CN1021152C (enExample)
AR (1) AR241460A1 (enExample)
AT (1) ATE84162T1 (enExample)
BE (1) BE1001181A3 (enExample)
BR (1) BR8801254A (enExample)
CA (1) CA1297601C (enExample)
DE (3) DE3783358T2 (enExample)
ES (1) ES2036559T3 (enExample)
FR (1) FR2612662B1 (enExample)
GB (1) GB2202719B (enExample)
HK (1) HK33592A (enExample)
IT (1) IT1216769B (enExample)
MY (1) MY102808A (enExample)
NL (1) NL186120C (enExample)
PH (1) PH27199A (enExample)
SG (1) SG5092G (enExample)
SU (1) SU1523058A3 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8908612D0 (en) * 1989-04-17 1989-06-01 Quantel Ltd Video graphics system
GB2247139B (en) * 1990-08-09 1994-07-20 Research Machines Ltd Scheduling drawing operations of moving images

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4117469A (en) * 1976-12-20 1978-09-26 Levine Michael R Computer assisted display processor having memory sharing by the computer and the processor
GB2084836B (en) * 1980-10-06 1984-05-23 Standard Microsyst Smc Video processor and controller
JPS588348A (ja) * 1981-07-07 1983-01-18 Sony Corp 出力表示用メモリの制御回路
US4408200A (en) * 1981-08-12 1983-10-04 International Business Machines Corporation Apparatus and method for reading and writing text characters in a graphics display
JPS5960478A (ja) * 1982-09-30 1984-04-06 キヤノン株式会社 ビデオ用記憶装置書き換え方式
JPS59116846A (ja) * 1982-12-23 1984-07-05 Matsushita Electric Ind Co Ltd 中央演算装置の制御装置
US4577344A (en) * 1983-01-17 1986-03-18 Automatix Incorporated Vision system
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
JPS6032089A (ja) * 1983-08-03 1985-02-19 松下電器産業株式会社 Ｃｒｔ表示端末装置
US4580135A (en) * 1983-08-12 1986-04-01 International Business Machines Corporation Raster scan display system
JPS60220386A (ja) * 1984-04-17 1985-11-05 三菱電機株式会社 フレ−ムメモリアクセス方式
EP0482678B1 (en) * 1984-07-23 1998-01-14 Texas Instruments Incorporated Video system
GB8608776D0 (en) * 1986-04-10 1986-05-14 Sinclair Res Ltd Video memory contention mechanism

Also Published As

Publication number Publication date
AR241460A1 (es) 1992-07-31
GB2202719B (en) 1991-07-24
NL186120B (nl) 1990-04-17
BR8801254A (pt) 1988-10-25
JPH0766319B2 (ja) 1995-07-19
DE8803581U1 (de) 1988-11-24
CN88100948A (zh) 1988-09-28
IT1216769B (it) 1990-03-08
EP0283565A3 (en) 1989-06-21
KR950005230B1 (ko) 1995-05-22
CA1297601C (en) 1992-03-17
DE3783358T2 (de) 1993-07-01
GB8725114D0 (en) 1987-12-02
ES2036559T3 (es) 1993-06-01
DE3808832A1 (de) 1988-09-29
DE3808832C2 (enExample) 1992-03-12
GB2202719A (en) 1988-09-28
KR880011645A (ko) 1988-10-29
EP0283565A2 (en) 1988-09-28
SU1523058A3 (ru) 1989-11-15
PH27199A (en) 1993-04-16
DE3783358D1 (de) 1993-02-11
EP0283565B1 (en) 1992-12-30
ATE84162T1 (de) 1993-01-15
BE1001181A3 (fr) 1989-08-08
NL186120C (nl) 1990-09-17
IT8819554A0 (it) 1988-02-26
FR2612662B1 (fr) 1990-06-01
NL8800626A (nl) 1988-10-17
JPS63231616A (ja) 1988-09-27
HK33592A (en) 1992-05-15
CN1021152C (zh) 1993-06-09
FR2612662A1 (fr) 1988-09-23
SG5092G (en) 1992-03-20

Similar Documents

Publication Publication Date Title
ES484612A1 (es) Un terminal de presentacion visual de datos de video
EP0393722A3 (en) Memory access control circuit for graphic controller
EP0359234A3 (en) Display control apparatus for converting crt resolution into pdp resolution by hardware
MY115313A (en) Method and apparatus for reducing discontinuities in an active addressing display system
AU5393590A (en) Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width
CA2034295A1 (en) Data processing apparatus with display device
DE69815339D1 (de) Bereitschaftssystem für Rechnerbildschirm mit niedrigem Energieverbrauch
US4575826B1 (enExample)
MY102808A (en) Memory arbitration for video subsystems
PT84986A (en) System management apparatus for a multiprocessor system
EP0198170A3 (en) A monitor circuit
DE3471187D1 (en) Computer with automatic switching of peripheral units, and peripheral unit suited for such a switching
GB2357947A (en) Fast processed screen image
EP0080043A3 (en) Method for data storage in an image refresh memory of a vdu
JPS5661087A (en) Control system for dynamic memory
JPS5439524A (en) Display unit with next screen display function
GB2016757A (en) Display Terminal
US4342989A (en) Dual CRT control unit synchronization system
JPS5790749A (en) Memory access system
JPS59116783A (ja) 表示用メモリのアクセス装置
CA1315889C (en) Computer workstation with interrupt signaling arrangement
JPS6433612A (en) Information processor
JP2659601B2 (ja) 液晶表示装置
KR910010286A (ko) 비디오 디스플레이 어뎁터
TESLIGTE Dimensioning analysis of DMANAGER parameters using simulation(direct memory access)